1 //===- AMDGPUMCInstLower.cpp - Lower AMDGPU MachineInstr to an MCInst -----===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 /// \file 11 /// \brief Code to lower AMDGPU MachineInstrs to their corresponding MCInst. 12 // 13 //===----------------------------------------------------------------------===// 14 // 15 16 #include "AMDGPUMCInstLower.h" 17 #include "AMDGPUAsmPrinter.h" 18 #include "AMDGPUSubtarget.h" 19 #include "AMDGPUTargetMachine.h" 20 #include "InstPrinter/AMDGPUInstPrinter.h" 21 #include "SIInstrInfo.h" 22 #include "llvm/CodeGen/MachineBasicBlock.h" 23 #include "llvm/CodeGen/MachineInstr.h" 24 #include "llvm/IR/Constants.h" 25 #include "llvm/IR/Function.h" 26 #include "llvm/IR/GlobalVariable.h" 27 #include "llvm/MC/MCCodeEmitter.h" 28 #include "llvm/MC/MCContext.h" 29 #include "llvm/MC/MCExpr.h" 30 #include "llvm/MC/MCInst.h" 31 #include "llvm/MC/MCObjectStreamer.h" 32 #include "llvm/MC/MCStreamer.h" 33 #include "llvm/Support/ErrorHandling.h" 34 #include "llvm/Support/Format.h" 35 #include <algorithm> 36 37 using namespace llvm; 38 39 AMDGPUMCInstLower::AMDGPUMCInstLower(MCContext &ctx, const AMDGPUSubtarget &st): 40 Ctx(ctx), ST(st) { } 41 42 static MCSymbolRefExpr::VariantKind getVariantKind(unsigned MOFlags) { 43 switch (MOFlags) { 44 default: return MCSymbolRefExpr::VK_None; 45 case SIInstrInfo::MO_GOTPCREL: return MCSymbolRefExpr::VK_GOTPCREL; 46 } 47 } 48 49 void AMDGPUMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const { 50 51 int MCOpcode = ST.getInstrInfo()->pseudoToMCOpcode(MI->getOpcode()); 52 53 if (MCOpcode == -1) { 54 LLVMContext &C = MI->getParent()->getParent()->getFunction()->getContext(); 55 C.emitError("AMDGPUMCInstLower::lower - Pseudo instruction doesn't have " 56 "a target-specific version: " + Twine(MI->getOpcode())); 57 } 58 59 OutMI.setOpcode(MCOpcode); 60 61 for (const MachineOperand &MO : MI->explicit_operands()) { 62 MCOperand MCOp; 63 switch (MO.getType()) { 64 default: 65 llvm_unreachable("unknown operand type"); 66 case MachineOperand::MO_Immediate: 67 MCOp = MCOperand::createImm(MO.getImm()); 68 break; 69 case MachineOperand::MO_Register: 70 MCOp = MCOperand::createReg(AMDGPU::getMCReg(MO.getReg(), ST)); 71 break; 72 case MachineOperand::MO_MachineBasicBlock: 73 MCOp = MCOperand::createExpr(MCSymbolRefExpr::create( 74 MO.getMBB()->getSymbol(), Ctx)); 75 break; 76 case MachineOperand::MO_GlobalAddress: { 77 const GlobalValue *GV = MO.getGlobal(); 78 MCSymbol *Sym = Ctx.getOrCreateSymbol(StringRef(GV->getName())); 79 const MCExpr *SymExpr = 80 MCSymbolRefExpr::create(Sym, getVariantKind(MO.getTargetFlags()),Ctx); 81 const MCExpr *Expr = MCBinaryExpr::createAdd(SymExpr, 82 MCConstantExpr::create(MO.getOffset(), Ctx), Ctx); 83 MCOp = MCOperand::createExpr(Expr); 84 break; 85 } 86 case MachineOperand::MO_ExternalSymbol: { 87 MCSymbol *Sym = Ctx.getOrCreateSymbol(StringRef(MO.getSymbolName())); 88 Sym->setExternal(true); 89 const MCSymbolRefExpr *Expr = MCSymbolRefExpr::create(Sym, Ctx); 90 MCOp = MCOperand::createExpr(Expr); 91 break; 92 } 93 } 94 OutMI.addOperand(MCOp); 95 } 96 } 97 98 void AMDGPUAsmPrinter::EmitInstruction(const MachineInstr *MI) { 99 const AMDGPUSubtarget &STI = MF->getSubtarget<AMDGPUSubtarget>(); 100 AMDGPUMCInstLower MCInstLowering(OutContext, STI); 101 102 StringRef Err; 103 if (!STI.getInstrInfo()->verifyInstruction(*MI, Err)) { 104 LLVMContext &C = MI->getParent()->getParent()->getFunction()->getContext(); 105 C.emitError("Illegal instruction detected: " + Err); 106 MI->dump(); 107 } 108 109 if (MI->isBundle()) { 110 const MachineBasicBlock *MBB = MI->getParent(); 111 MachineBasicBlock::const_instr_iterator I = ++MI->getIterator(); 112 while (I != MBB->instr_end() && I->isInsideBundle()) { 113 EmitInstruction(&*I); 114 ++I; 115 } 116 } else { 117 // We don't want SI_MASK_BRANCH/SI_RETURN encoded. They are placeholder 118 // terminator instructions and should only be printed as comments. 119 if (MI->getOpcode() == AMDGPU::SI_MASK_BRANCH) { 120 if (isVerbose()) { 121 SmallVector<char, 16> BBStr; 122 raw_svector_ostream Str(BBStr); 123 124 const MachineBasicBlock *MBB = MI->getOperand(0).getMBB(); 125 const MCSymbolRefExpr *Expr 126 = MCSymbolRefExpr::create(MBB->getSymbol(), OutContext); 127 Expr->print(Str, MAI); 128 OutStreamer->emitRawComment(" mask branch " + BBStr); 129 } 130 131 return; 132 } 133 134 if (MI->getOpcode() == AMDGPU::SI_RETURN) { 135 if (isVerbose()) 136 OutStreamer->emitRawComment(" return"); 137 return; 138 } 139 140 MCInst TmpInst; 141 MCInstLowering.lower(MI, TmpInst); 142 EmitToStreamer(*OutStreamer, TmpInst); 143 144 if (STI.dumpCode()) { 145 // Disassemble instruction/operands to text. 146 DisasmLines.resize(DisasmLines.size() + 1); 147 std::string &DisasmLine = DisasmLines.back(); 148 raw_string_ostream DisasmStream(DisasmLine); 149 150 AMDGPUInstPrinter InstPrinter(*TM.getMCAsmInfo(), 151 *STI.getInstrInfo(), 152 *STI.getRegisterInfo()); 153 InstPrinter.printInst(&TmpInst, DisasmStream, StringRef(), STI); 154 155 // Disassemble instruction/operands to hex representation. 156 SmallVector<MCFixup, 4> Fixups; 157 SmallVector<char, 16> CodeBytes; 158 raw_svector_ostream CodeStream(CodeBytes); 159 160 auto &ObjStreamer = static_cast<MCObjectStreamer&>(*OutStreamer); 161 MCCodeEmitter &InstEmitter = ObjStreamer.getAssembler().getEmitter(); 162 InstEmitter.encodeInstruction(TmpInst, CodeStream, Fixups, 163 MF->getSubtarget<MCSubtargetInfo>()); 164 HexLines.resize(HexLines.size() + 1); 165 std::string &HexLine = HexLines.back(); 166 raw_string_ostream HexStream(HexLine); 167 168 for (size_t i = 0; i < CodeBytes.size(); i += 4) { 169 unsigned int CodeDWord = *(unsigned int *)&CodeBytes[i]; 170 HexStream << format("%s%08X", (i > 0 ? " " : ""), CodeDWord); 171 } 172 173 DisasmStream.flush(); 174 DisasmLineMaxLen = std::max(DisasmLineMaxLen, DisasmLine.size()); 175 } 176 } 177 } 178
