1 //===-- ARMCallingConv.td - Calling Conventions for ARM ----*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // This describes the calling conventions for ARM architecture. 10 //===----------------------------------------------------------------------===// 11 12 /// CCIfAlign - Match of the original alignment of the arg 13 class CCIfAlign<string Align, CCAction A>: 14 CCIf<!strconcat("ArgFlags.getOrigAlign() == ", Align), A>; 15 16 //===----------------------------------------------------------------------===// 17 // ARM APCS Calling Convention 18 //===----------------------------------------------------------------------===// 19 def CC_ARM_APCS : CallingConv<[ 20 21 // Handles byval parameters. 22 CCIfByVal<CCPassByVal<4, 4>>, 23 24 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>, 25 26 // Pass SwiftSelf in a callee saved register. 27 CCIfSwiftSelf<CCIfType<[i32], CCAssignToReg<[R10]>>>, 28 29 // A SwiftError is passed in R6. 30 CCIfSwiftError<CCIfType<[i32], CCAssignToReg<[R6]>>>, 31 32 // Handle all vector types as either f64 or v2f64. 33 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>, 34 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>, 35 36 // f64 and v2f64 are passed in adjacent GPRs, possibly split onto the stack 37 CCIfType<[f64, v2f64], CCCustom<"CC_ARM_APCS_Custom_f64">>, 38 39 CCIfType<[f32], CCBitConvertToType<i32>>, 40 CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>, 41 42 CCIfType<[i32], CCAssignToStack<4, 4>>, 43 CCIfType<[f64], CCAssignToStack<8, 4>>, 44 CCIfType<[v2f64], CCAssignToStack<16, 4>> 45 ]>; 46 47 def RetCC_ARM_APCS : CallingConv<[ 48 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>, 49 CCIfType<[f32], CCBitConvertToType<i32>>, 50 51 // Pass SwiftSelf in a callee saved register. 52 CCIfSwiftSelf<CCIfType<[i32], CCAssignToReg<[R10]>>>, 53 54 // A SwiftError is returned in R6. 55 CCIfSwiftError<CCIfType<[i32], CCAssignToReg<[R6]>>>, 56 57 // Handle all vector types as either f64 or v2f64. 58 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>, 59 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>, 60 61 CCIfType<[f64, v2f64], CCCustom<"RetCC_ARM_APCS_Custom_f64">>, 62 63 CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>, 64 CCIfType<[i64], CCAssignToRegWithShadow<[R0, R2], [R1, R3]>> 65 ]>; 66 67 //===----------------------------------------------------------------------===// 68 // ARM APCS Calling Convention for FastCC (when VFP2 or later is available) 69 //===----------------------------------------------------------------------===// 70 def FastCC_ARM_APCS : CallingConv<[ 71 // Handle all vector types as either f64 or v2f64. 72 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>, 73 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>, 74 75 CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>, 76 CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>, 77 CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7, S8, 78 S9, S10, S11, S12, S13, S14, S15]>>, 79 80 // CPRCs may be allocated to co-processor registers or the stack - they 81 // may never be allocated to core registers. 82 CCIfType<[f32], CCAssignToStackWithShadow<4, 4, [Q0, Q1, Q2, Q3]>>, 83 CCIfType<[f64], CCAssignToStackWithShadow<8, 4, [Q0, Q1, Q2, Q3]>>, 84 CCIfType<[v2f64], CCAssignToStackWithShadow<16, 4, [Q0, Q1, Q2, Q3]>>, 85 86 CCDelegateTo<CC_ARM_APCS> 87 ]>; 88 89 def RetFastCC_ARM_APCS : CallingConv<[ 90 // Handle all vector types as either f64 or v2f64. 91 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>, 92 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>, 93 94 CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>, 95 CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>, 96 CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7, S8, 97 S9, S10, S11, S12, S13, S14, S15]>>, 98 CCDelegateTo<RetCC_ARM_APCS> 99 ]>; 100 101 //===----------------------------------------------------------------------===// 102 // ARM APCS Calling Convention for GHC 103 //===----------------------------------------------------------------------===// 104 105 def CC_ARM_APCS_GHC : CallingConv<[ 106 // Handle all vector types as either f64 or v2f64. 107 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>, 108 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>, 109 110 CCIfType<[v2f64], CCAssignToReg<[Q4, Q5]>>, 111 CCIfType<[f64], CCAssignToReg<[D8, D9, D10, D11]>>, 112 CCIfType<[f32], CCAssignToReg<[S16, S17, S18, S19, S20, S21, S22, S23]>>, 113 114 // Promote i8/i16 arguments to i32. 115 CCIfType<[i8, i16], CCPromoteToType<i32>>, 116 117 // Pass in STG registers: Base, Sp, Hp, R1, R2, R3, R4, SpLim 118 CCIfType<[i32], CCAssignToReg<[R4, R5, R6, R7, R8, R9, R10, R11]>> 119 ]>; 120 121 //===----------------------------------------------------------------------===// 122 // ARM AAPCS (EABI) Calling Convention, common parts 123 //===----------------------------------------------------------------------===// 124 125 def CC_ARM_AAPCS_Common : CallingConv<[ 126 127 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>, 128 129 // i64/f64 is passed in even pairs of GPRs 130 // i64 is 8-aligned i32 here, so we may need to eat R1 as a pad register 131 // (and the same is true for f64 if VFP is not enabled) 132 CCIfType<[i32], CCIfAlign<"8", CCAssignToRegWithShadow<[R0, R2], [R0, R1]>>>, 133 CCIfType<[i32], CCIf<"ArgFlags.getOrigAlign() != 8", 134 CCAssignToReg<[R0, R1, R2, R3]>>>, 135 136 CCIfType<[i32], CCIfAlign<"8", CCAssignToStackWithShadow<4, 8, [R0, R1, R2, R3]>>>, 137 CCIfType<[i32], CCAssignToStackWithShadow<4, 4, [R0, R1, R2, R3]>>, 138 CCIfType<[f32], CCAssignToStackWithShadow<4, 4, [Q0, Q1, Q2, Q3]>>, 139 CCIfType<[f64], CCAssignToStackWithShadow<8, 8, [Q0, Q1, Q2, Q3]>>, 140 CCIfType<[v2f64], CCIfAlign<"16", 141 CCAssignToStackWithShadow<16, 16, [Q0, Q1, Q2, Q3]>>>, 142 CCIfType<[v2f64], CCAssignToStackWithShadow<16, 8, [Q0, Q1, Q2, Q3]>> 143 ]>; 144 145 def RetCC_ARM_AAPCS_Common : CallingConv<[ 146 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>, 147 CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>, 148 CCIfType<[i64], CCAssignToRegWithShadow<[R0, R2], [R1, R3]>> 149 ]>; 150 151 //===----------------------------------------------------------------------===// 152 // ARM AAPCS (EABI) Calling Convention 153 //===----------------------------------------------------------------------===// 154 155 def CC_ARM_AAPCS : CallingConv<[ 156 // Handles byval parameters. 157 CCIfByVal<CCPassByVal<4, 4>>, 158 159 // The 'nest' parameter, if any, is passed in R12. 160 CCIfNest<CCAssignToReg<[R12]>>, 161 162 // Handle all vector types as either f64 or v2f64. 163 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>, 164 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>, 165 166 // Pass SwiftSelf in a callee saved register. 167 CCIfSwiftSelf<CCIfType<[i32], CCAssignToReg<[R10]>>>, 168 169 // A SwiftError is passed in R6. 170 CCIfSwiftError<CCIfType<[i32], CCAssignToReg<[R6]>>>, 171 172 CCIfType<[f64, v2f64], CCCustom<"CC_ARM_AAPCS_Custom_f64">>, 173 CCIfType<[f32], CCBitConvertToType<i32>>, 174 CCDelegateTo<CC_ARM_AAPCS_Common> 175 ]>; 176 177 def RetCC_ARM_AAPCS : CallingConv<[ 178 // Handle all vector types as either f64 or v2f64. 179 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>, 180 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>, 181 182 // Pass SwiftSelf in a callee saved register. 183 CCIfSwiftSelf<CCIfType<[i32], CCAssignToReg<[R10]>>>, 184 185 // A SwiftError is returned in R6. 186 CCIfSwiftError<CCIfType<[i32], CCAssignToReg<[R6]>>>, 187 188 CCIfType<[f64, v2f64], CCCustom<"RetCC_ARM_AAPCS_Custom_f64">>, 189 CCIfType<[f32], CCBitConvertToType<i32>>, 190 CCDelegateTo<RetCC_ARM_AAPCS_Common> 191 ]>; 192 193 //===----------------------------------------------------------------------===// 194 // ARM AAPCS-VFP (EABI) Calling Convention 195 // Also used for FastCC (when VFP2 or later is available) 196 //===----------------------------------------------------------------------===// 197 198 def CC_ARM_AAPCS_VFP : CallingConv<[ 199 // Handles byval parameters. 200 CCIfByVal<CCPassByVal<4, 4>>, 201 202 // Handle all vector types as either f64 or v2f64. 203 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>, 204 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>, 205 206 // Pass SwiftSelf in a callee saved register. 207 CCIfSwiftSelf<CCIfType<[i32], CCAssignToReg<[R10]>>>, 208 209 // A SwiftError is passed in R6. 210 CCIfSwiftError<CCIfType<[i32], CCAssignToReg<[R6]>>>, 211 212 // HFAs are passed in a contiguous block of registers, or on the stack 213 CCIfConsecutiveRegs<CCCustom<"CC_ARM_AAPCS_Custom_Aggregate">>, 214 215 CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>, 216 CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>, 217 CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7, S8, 218 S9, S10, S11, S12, S13, S14, S15]>>, 219 CCDelegateTo<CC_ARM_AAPCS_Common> 220 ]>; 221 222 def RetCC_ARM_AAPCS_VFP : CallingConv<[ 223 // Handle all vector types as either f64 or v2f64. 224 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>, 225 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>, 226 227 // Pass SwiftSelf in a callee saved register. 228 CCIfSwiftSelf<CCIfType<[i32], CCAssignToReg<[R10]>>>, 229 230 // A SwiftError is returned in R6. 231 CCIfSwiftError<CCIfType<[i32], CCAssignToReg<[R6]>>>, 232 233 CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>, 234 CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>, 235 CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7, S8, 236 S9, S10, S11, S12, S13, S14, S15]>>, 237 CCDelegateTo<RetCC_ARM_AAPCS_Common> 238 ]>; 239 240 //===----------------------------------------------------------------------===// 241 // Callee-saved register lists. 242 //===----------------------------------------------------------------------===// 243 244 def CSR_NoRegs : CalleeSavedRegs<(add)>; 245 246 def CSR_AAPCS : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6, R5, R4, 247 (sequence "D%u", 15, 8))>; 248 249 // The order of callee-saved registers needs to match the order we actually push 250 // them in FrameLowering, because this order is what's used by 251 // PrologEpilogInserter to allocate frame index slots. So when R7 is the frame 252 // pointer, we use this AAPCS alternative. 253 def CSR_AAPCS_SplitPush : CalleeSavedRegs<(add LR, R7, R6, R5, R4, 254 R11, R10, R9, R8, 255 (sequence "D%u", 15, 8))>; 256 257 // Constructors and destructors return 'this' in the ARM C++ ABI; since 'this' 258 // and the pointer return value are both passed in R0 in these cases, this can 259 // be partially modelled by treating R0 as a callee-saved register 260 // Only the resulting RegMask is used; the SaveList is ignored 261 def CSR_AAPCS_ThisReturn : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6, 262 R5, R4, (sequence "D%u", 15, 8), 263 R0)>; 264 265 // iOS ABI deviates from ARM standard ABI. R9 is not a callee-saved register. 266 // Also save R7-R4 first to match the stack frame fixed spill areas. 267 def CSR_iOS : CalleeSavedRegs<(add LR, R7, R6, R5, R4, (sub CSR_AAPCS, R9))>; 268 269 // R6 is used to pass swifterror, remove it from CSR. 270 def CSR_iOS_SwiftError : CalleeSavedRegs<(sub CSR_iOS, R6)>; 271 272 def CSR_iOS_ThisReturn : CalleeSavedRegs<(add LR, R7, R6, R5, R4, 273 (sub CSR_AAPCS_ThisReturn, R9))>; 274 275 def CSR_iOS_TLSCall : CalleeSavedRegs<(add LR, SP, 276 (sequence "R%u", 12, 1), 277 (sequence "D%u", 31, 0))>; 278 279 // C++ TLS access function saves all registers except SP. Try to match 280 // the order of CSRs in CSR_iOS. 281 def CSR_iOS_CXX_TLS : CalleeSavedRegs<(add CSR_iOS, (sequence "R%u", 12, 1), 282 (sequence "D%u", 31, 0))>; 283 284 // CSRs that are handled by prologue, epilogue. 285 def CSR_iOS_CXX_TLS_PE : CalleeSavedRegs<(add LR, R12, R11, R7, R5, R4)>; 286 287 // CSRs that are handled explicitly via copies. 288 def CSR_iOS_CXX_TLS_ViaCopy : CalleeSavedRegs<(sub CSR_iOS_CXX_TLS, 289 CSR_iOS_CXX_TLS_PE)>; 290 291 // The "interrupt" attribute is used to generate code that is acceptable in 292 // exception-handlers of various kinds. It makes us use a different return 293 // instruction (handled elsewhere) and affects which registers we must return to 294 // our "caller" in the same state as we receive them. 295 296 // For most interrupts, all registers except SP and LR are shared with 297 // user-space. We mark LR to be saved anyway, since this is what the ARM backend 298 // generally does rather than tracking its liveness as a normal register. 299 def CSR_GenericInt : CalleeSavedRegs<(add LR, (sequence "R%u", 12, 0))>; 300 301 // The fast interrupt handlers have more private state and get their own copies 302 // of R8-R12, in addition to SP and LR. As before, mark LR for saving too. 303 304 // FIXME: we mark R11 as callee-saved since it's often the frame-pointer, and 305 // current frame lowering expects to encounter it while processing callee-saved 306 // registers. 307 def CSR_FIQ : CalleeSavedRegs<(add LR, R11, (sequence "R%u", 7, 0))>; 308 309 310
