1 //==- HexagonInstrInfo.td - Target Description for Hexagon -*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes the Hexagon instructions in TableGen format. 11 // 12 //===----------------------------------------------------------------------===// 13 14 include "HexagonInstrFormats.td" 15 include "HexagonOperands.td" 16 include "HexagonInstrEnc.td" 17 // Pattern fragment that combines the value type and the register class 18 // into a single parameter. 19 // The pat frags in the definitions below need to have a named register, 20 // otherwise i32 will be assumed regardless of the register class. The 21 // name of the register does not matter. 22 def I1 : PatLeaf<(i1 PredRegs:$R)>; 23 def I32 : PatLeaf<(i32 IntRegs:$R)>; 24 def I64 : PatLeaf<(i64 DoubleRegs:$R)>; 25 def F32 : PatLeaf<(f32 IntRegs:$R)>; 26 def F64 : PatLeaf<(f64 DoubleRegs:$R)>; 27 28 // Pattern fragments to extract the low and high subregisters from a 29 // 64-bit value. 30 def LoReg: OutPatFrag<(ops node:$Rs), 31 (EXTRACT_SUBREG (i64 $Rs), subreg_loreg)>; 32 def HiReg: OutPatFrag<(ops node:$Rs), 33 (EXTRACT_SUBREG (i64 $Rs), subreg_hireg)>; 34 35 // SDNode for converting immediate C to C-1. 36 def DEC_CONST_SIGNED : SDNodeXForm<imm, [{ 37 // Return the byte immediate const-1 as an SDNode. 38 int32_t imm = N->getSExtValue(); 39 return XformSToSM1Imm(imm, SDLoc(N)); 40 }]>; 41 42 // SDNode for converting immediate C to C-2. 43 def DEC2_CONST_SIGNED : SDNodeXForm<imm, [{ 44 // Return the byte immediate const-2 as an SDNode. 45 int32_t imm = N->getSExtValue(); 46 return XformSToSM2Imm(imm, SDLoc(N)); 47 }]>; 48 49 // SDNode for converting immediate C to C-3. 50 def DEC3_CONST_SIGNED : SDNodeXForm<imm, [{ 51 // Return the byte immediate const-3 as an SDNode. 52 int32_t imm = N->getSExtValue(); 53 return XformSToSM3Imm(imm, SDLoc(N)); 54 }]>; 55 56 // SDNode for converting immediate C to C-1. 57 def DEC_CONST_UNSIGNED : SDNodeXForm<imm, [{ 58 // Return the byte immediate const-1 as an SDNode. 59 uint32_t imm = N->getZExtValue(); 60 return XformUToUM1Imm(imm, SDLoc(N)); 61 }]>; 62 63 //===----------------------------------------------------------------------===// 64 // Compare 65 //===----------------------------------------------------------------------===// 66 let hasSideEffects = 0, isCompare = 1, InputType = "imm", isExtendable = 1, 67 opExtendable = 2 in 68 class T_CMP <string mnemonic, bits<2> MajOp, bit isNot, Operand ImmOp> 69 : ALU32Inst <(outs PredRegs:$dst), 70 (ins IntRegs:$src1, ImmOp:$src2), 71 "$dst = "#!if(isNot, "!","")#mnemonic#"($src1, #$src2)", 72 [], "",ALU32_2op_tc_2early_SLOT0123 >, ImmRegRel { 73 bits<2> dst; 74 bits<5> src1; 75 bits<10> src2; 76 let CextOpcode = mnemonic; 77 let opExtentBits = !if(!eq(mnemonic, "cmp.gtu"), 9, 10); 78 let isExtentSigned = !if(!eq(mnemonic, "cmp.gtu"), 0, 1); 79 80 let IClass = 0b0111; 81 82 let Inst{27-24} = 0b0101; 83 let Inst{23-22} = MajOp; 84 let Inst{21} = !if(!eq(mnemonic, "cmp.gtu"), 0, src2{9}); 85 let Inst{20-16} = src1; 86 let Inst{13-5} = src2{8-0}; 87 let Inst{4} = isNot; 88 let Inst{3-2} = 0b00; 89 let Inst{1-0} = dst; 90 } 91 92 def C2_cmpeqi : T_CMP <"cmp.eq", 0b00, 0, s10Ext>; 93 def C2_cmpgti : T_CMP <"cmp.gt", 0b01, 0, s10Ext>; 94 def C2_cmpgtui : T_CMP <"cmp.gtu", 0b10, 0, u9Ext>; 95 96 class T_CMP_pat <InstHexagon MI, PatFrag OpNode, PatLeaf ImmPred> 97 : Pat<(i1 (OpNode (i32 IntRegs:$src1), ImmPred:$src2)), 98 (MI IntRegs:$src1, ImmPred:$src2)>; 99 100 def : T_CMP_pat <C2_cmpeqi, seteq, s10ImmPred>; 101 def : T_CMP_pat <C2_cmpgti, setgt, s10ImmPred>; 102 def : T_CMP_pat <C2_cmpgtui, setugt, u9ImmPred>; 103 104 //===----------------------------------------------------------------------===// 105 // ALU32/ALU + 106 //===----------------------------------------------------------------------===// 107 // Add. 108 109 def SDT_Int32Leaf : SDTypeProfile<1, 0, [SDTCisVT<0, i32>]>; 110 def SDT_Int32Unary : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 111 112 def SDTHexagonI64I32I32 : SDTypeProfile<1, 2, 113 [SDTCisVT<0, i64>, SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>; 114 115 def HexagonCOMBINE : SDNode<"HexagonISD::COMBINE", SDTHexagonI64I32I32>; 116 def HexagonPACKHL : SDNode<"HexagonISD::PACKHL", SDTHexagonI64I32I32>; 117 118 let hasSideEffects = 0, hasNewValue = 1, InputType = "reg" in 119 class T_ALU32_3op<string mnemonic, bits<3> MajOp, bits<3> MinOp, bit OpsRev, 120 bit IsComm> 121 : ALU32_rr<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt), 122 "$Rd = "#mnemonic#"($Rs, $Rt)", 123 [], "", ALU32_3op_tc_1_SLOT0123>, ImmRegRel, PredRel { 124 let isCommutable = IsComm; 125 let BaseOpcode = mnemonic#_rr; 126 let CextOpcode = mnemonic; 127 128 bits<5> Rs; 129 bits<5> Rt; 130 bits<5> Rd; 131 132 let IClass = 0b1111; 133 let Inst{27} = 0b0; 134 let Inst{26-24} = MajOp; 135 let Inst{23-21} = MinOp; 136 let Inst{20-16} = !if(OpsRev,Rt,Rs); 137 let Inst{12-8} = !if(OpsRev,Rs,Rt); 138 let Inst{4-0} = Rd; 139 } 140 141 let hasSideEffects = 0, hasNewValue = 1 in 142 class T_ALU32_3op_pred<string mnemonic, bits<3> MajOp, bits<3> MinOp, 143 bit OpsRev, bit PredNot, bit PredNew> 144 : ALU32_rr<(outs IntRegs:$Rd), (ins PredRegs:$Pu, IntRegs:$Rs, IntRegs:$Rt), 145 "if ("#!if(PredNot,"!","")#"$Pu"#!if(PredNew,".new","")#") "# 146 "$Rd = "#mnemonic#"($Rs, $Rt)", 147 [], "", ALU32_3op_tc_1_SLOT0123>, ImmRegRel, PredNewRel { 148 let isPredicated = 1; 149 let isPredicatedFalse = PredNot; 150 let isPredicatedNew = PredNew; 151 let BaseOpcode = mnemonic#_rr; 152 let CextOpcode = mnemonic; 153 154 bits<2> Pu; 155 bits<5> Rs; 156 bits<5> Rt; 157 bits<5> Rd; 158 159 let IClass = 0b1111; 160 let Inst{27} = 0b1; 161 let Inst{26-24} = MajOp; 162 let Inst{23-21} = MinOp; 163 let Inst{20-16} = !if(OpsRev,Rt,Rs); 164 let Inst{13} = PredNew; 165 let Inst{12-8} = !if(OpsRev,Rs,Rt); 166 let Inst{7} = PredNot; 167 let Inst{6-5} = Pu; 168 let Inst{4-0} = Rd; 169 } 170 171 class T_ALU32_combineh<string Op1, string Op2, bits<3> MajOp, bits<3> MinOp, 172 bit OpsRev> 173 : T_ALU32_3op<"", MajOp, MinOp, OpsRev, 0> { 174 let AsmString = "$Rd = combine($Rs"#Op1#", $Rt"#Op2#")"; 175 } 176 177 def A2_combine_hh : T_ALU32_combineh<".h", ".h", 0b011, 0b100, 1>; 178 def A2_combine_hl : T_ALU32_combineh<".h", ".l", 0b011, 0b101, 1>; 179 def A2_combine_lh : T_ALU32_combineh<".l", ".h", 0b011, 0b110, 1>; 180 def A2_combine_ll : T_ALU32_combineh<".l", ".l", 0b011, 0b111, 1>; 181 182 class T_ALU32_3op_sfx<string mnemonic, string suffix, bits<3> MajOp, 183 bits<3> MinOp, bit OpsRev, bit IsComm> 184 : T_ALU32_3op<"", MajOp, MinOp, OpsRev, IsComm> { 185 let AsmString = "$Rd = "#mnemonic#"($Rs, $Rt)"#suffix; 186 } 187 188 def A2_svaddh : T_ALU32_3op<"vaddh", 0b110, 0b000, 0, 1>; 189 def A2_svsubh : T_ALU32_3op<"vsubh", 0b110, 0b100, 1, 0>; 190 191 let Defs = [USR_OVF], Itinerary = ALU32_3op_tc_2_SLOT0123 in { 192 def A2_svaddhs : T_ALU32_3op_sfx<"vaddh", ":sat", 0b110, 0b001, 0, 1>; 193 def A2_addsat : T_ALU32_3op_sfx<"add", ":sat", 0b110, 0b010, 0, 1>; 194 def A2_svadduhs : T_ALU32_3op_sfx<"vadduh", ":sat", 0b110, 0b011, 0, 1>; 195 def A2_svsubhs : T_ALU32_3op_sfx<"vsubh", ":sat", 0b110, 0b101, 1, 0>; 196 def A2_subsat : T_ALU32_3op_sfx<"sub", ":sat", 0b110, 0b110, 1, 0>; 197 def A2_svsubuhs : T_ALU32_3op_sfx<"vsubuh", ":sat", 0b110, 0b111, 1, 0>; 198 } 199 200 let Itinerary = ALU32_3op_tc_2_SLOT0123 in 201 def A2_svavghs : T_ALU32_3op_sfx<"vavgh", ":rnd", 0b111, 0b001, 0, 1>; 202 203 def A2_svavgh : T_ALU32_3op<"vavgh", 0b111, 0b000, 0, 1>; 204 def A2_svnavgh : T_ALU32_3op<"vnavgh", 0b111, 0b011, 1, 0>; 205 206 multiclass T_ALU32_3op_p<string mnemonic, bits<3> MajOp, bits<3> MinOp, 207 bit OpsRev> { 208 def t : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 0, 0>; 209 def f : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 1, 0>; 210 def tnew : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 0, 1>; 211 def fnew : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 1, 1>; 212 } 213 214 multiclass T_ALU32_3op_A2<string mnemonic, bits<3> MajOp, bits<3> MinOp, 215 bit OpsRev, bit IsComm> { 216 let isPredicable = 1 in 217 def A2_#NAME : T_ALU32_3op <mnemonic, MajOp, MinOp, OpsRev, IsComm>; 218 defm A2_p#NAME : T_ALU32_3op_p<mnemonic, MajOp, MinOp, OpsRev>; 219 } 220 221 defm add : T_ALU32_3op_A2<"add", 0b011, 0b000, 0, 1>; 222 defm and : T_ALU32_3op_A2<"and", 0b001, 0b000, 0, 1>; 223 defm or : T_ALU32_3op_A2<"or", 0b001, 0b001, 0, 1>; 224 defm sub : T_ALU32_3op_A2<"sub", 0b011, 0b001, 1, 0>; 225 defm xor : T_ALU32_3op_A2<"xor", 0b001, 0b011, 0, 1>; 226 227 // Pats for instruction selection. 228 class BinOp32_pat<SDNode Op, InstHexagon MI, ValueType ResT> 229 : Pat<(ResT (Op (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))), 230 (ResT (MI IntRegs:$Rs, IntRegs:$Rt))>; 231 232 def: BinOp32_pat<add, A2_add, i32>; 233 def: BinOp32_pat<and, A2_and, i32>; 234 def: BinOp32_pat<or, A2_or, i32>; 235 def: BinOp32_pat<sub, A2_sub, i32>; 236 def: BinOp32_pat<xor, A2_xor, i32>; 237 238 // A few special cases producing register pairs: 239 let OutOperandList = (outs DoubleRegs:$Rd), hasNewValue = 0 in { 240 def S2_packhl : T_ALU32_3op <"packhl", 0b101, 0b100, 0, 0>; 241 242 let isPredicable = 1 in 243 def A2_combinew : T_ALU32_3op <"combine", 0b101, 0b000, 0, 0>; 244 245 // Conditional combinew uses "newt/f" instead of "t/fnew". 246 def C2_ccombinewt : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 0, 0>; 247 def C2_ccombinewf : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 1, 0>; 248 def C2_ccombinewnewt : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 0, 1>; 249 def C2_ccombinewnewf : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 1, 1>; 250 } 251 252 def: BinOp32_pat<HexagonCOMBINE, A2_combinew, i64>; 253 def: BinOp32_pat<HexagonPACKHL, S2_packhl, i64>; 254 255 let hasSideEffects = 0, hasNewValue = 1, isCompare = 1, InputType = "reg" in 256 class T_ALU32_3op_cmp<string mnemonic, bits<2> MinOp, bit IsNeg, bit IsComm> 257 : ALU32_rr<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt), 258 "$Pd = "#mnemonic#"($Rs, $Rt)", 259 [], "", ALU32_3op_tc_1_SLOT0123>, ImmRegRel { 260 let CextOpcode = mnemonic; 261 let isCommutable = IsComm; 262 bits<5> Rs; 263 bits<5> Rt; 264 bits<2> Pd; 265 266 let IClass = 0b1111; 267 let Inst{27-24} = 0b0010; 268 let Inst{22-21} = MinOp; 269 let Inst{20-16} = Rs; 270 let Inst{12-8} = Rt; 271 let Inst{4} = IsNeg; 272 let Inst{3-2} = 0b00; 273 let Inst{1-0} = Pd; 274 } 275 276 let Itinerary = ALU32_3op_tc_2early_SLOT0123 in { 277 def C2_cmpeq : T_ALU32_3op_cmp< "cmp.eq", 0b00, 0, 1>; 278 def C2_cmpgt : T_ALU32_3op_cmp< "cmp.gt", 0b10, 0, 0>; 279 def C2_cmpgtu : T_ALU32_3op_cmp< "cmp.gtu", 0b11, 0, 0>; 280 } 281 282 // Patfrag to convert the usual comparison patfrags (e.g. setlt) to ones 283 // that reverse the order of the operands. 284 class RevCmp<PatFrag F> : PatFrag<(ops node:$rhs, node:$lhs), F.Fragment>; 285 286 // Pats for compares. They use PatFrags as operands, not SDNodes, 287 // since seteq/setgt/etc. are defined as ParFrags. 288 class T_cmp32_rr_pat<InstHexagon MI, PatFrag Op, ValueType VT> 289 : Pat<(VT (Op (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))), 290 (VT (MI IntRegs:$Rs, IntRegs:$Rt))>; 291 292 def: T_cmp32_rr_pat<C2_cmpeq, seteq, i1>; 293 def: T_cmp32_rr_pat<C2_cmpgt, setgt, i1>; 294 def: T_cmp32_rr_pat<C2_cmpgtu, setugt, i1>; 295 296 def: T_cmp32_rr_pat<C2_cmpgt, RevCmp<setlt>, i1>; 297 def: T_cmp32_rr_pat<C2_cmpgtu, RevCmp<setult>, i1>; 298 299 let CextOpcode = "MUX", InputType = "reg", hasNewValue = 1 in 300 def C2_mux: ALU32_rr<(outs IntRegs:$Rd), 301 (ins PredRegs:$Pu, IntRegs:$Rs, IntRegs:$Rt), 302 "$Rd = mux($Pu, $Rs, $Rt)", [], "", ALU32_3op_tc_1_SLOT0123>, ImmRegRel { 303 bits<5> Rd; 304 bits<2> Pu; 305 bits<5> Rs; 306 bits<5> Rt; 307 308 let CextOpcode = "mux"; 309 let InputType = "reg"; 310 let hasSideEffects = 0; 311 let IClass = 0b1111; 312 313 let Inst{27-24} = 0b0100; 314 let Inst{20-16} = Rs; 315 let Inst{12-8} = Rt; 316 let Inst{6-5} = Pu; 317 let Inst{4-0} = Rd; 318 } 319 320 def: Pat<(i32 (select (i1 PredRegs:$Pu), (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))), 321 (C2_mux PredRegs:$Pu, IntRegs:$Rs, IntRegs:$Rt)>; 322 323 // Combines the two immediates into a double register. 324 // Increase complexity to make it greater than any complexity of a combine 325 // that involves a register. 326 327 let isReMaterializable = 1, isMoveImm = 1, isAsCheapAsAMove = 1, 328 isExtentSigned = 1, isExtendable = 1, opExtentBits = 8, opExtendable = 1, 329 AddedComplexity = 75 in 330 def A2_combineii: ALU32Inst <(outs DoubleRegs:$Rdd), (ins s8Ext:$s8, s8Imm:$S8), 331 "$Rdd = combine(#$s8, #$S8)", 332 [(set (i64 DoubleRegs:$Rdd), 333 (i64 (HexagonCOMBINE(i32 s32ImmPred:$s8), (i32 s8ImmPred:$S8))))]> { 334 bits<5> Rdd; 335 bits<8> s8; 336 bits<8> S8; 337 338 let IClass = 0b0111; 339 let Inst{27-23} = 0b11000; 340 let Inst{22-16} = S8{7-1}; 341 let Inst{13} = S8{0}; 342 let Inst{12-5} = s8; 343 let Inst{4-0} = Rdd; 344 } 345 346 //===----------------------------------------------------------------------===// 347 // Template class for predicated ADD of a reg and an Immediate value. 348 //===----------------------------------------------------------------------===// 349 let hasNewValue = 1, hasSideEffects = 0 in 350 class T_Addri_Pred <bit PredNot, bit PredNew> 351 : ALU32_ri <(outs IntRegs:$Rd), 352 (ins PredRegs:$Pu, IntRegs:$Rs, s8Ext:$s8), 353 !if(PredNot, "if (!$Pu", "if ($Pu")#!if(PredNew,".new) $Rd = ", 354 ") $Rd = ")#"add($Rs, #$s8)"> { 355 bits<5> Rd; 356 bits<2> Pu; 357 bits<5> Rs; 358 bits<8> s8; 359 360 let isPredicatedNew = PredNew; 361 let IClass = 0b0111; 362 363 let Inst{27-24} = 0b0100; 364 let Inst{23} = PredNot; 365 let Inst{22-21} = Pu; 366 let Inst{20-16} = Rs; 367 let Inst{13} = PredNew; 368 let Inst{12-5} = s8; 369 let Inst{4-0} = Rd; 370 } 371 372 //===----------------------------------------------------------------------===// 373 // A2_addi: Add a signed immediate to a register. 374 //===----------------------------------------------------------------------===// 375 let hasNewValue = 1, hasSideEffects = 0 in 376 class T_Addri <Operand immOp> 377 : ALU32_ri <(outs IntRegs:$Rd), 378 (ins IntRegs:$Rs, immOp:$s16), 379 "$Rd = add($Rs, #$s16)", [], "", ALU32_ADDI_tc_1_SLOT0123> { 380 bits<5> Rd; 381 bits<5> Rs; 382 bits<16> s16; 383 384 let IClass = 0b1011; 385 386 let Inst{27-21} = s16{15-9}; 387 let Inst{20-16} = Rs; 388 let Inst{13-5} = s16{8-0}; 389 let Inst{4-0} = Rd; 390 } 391 392 //===----------------------------------------------------------------------===// 393 // Multiclass for ADD of a register and an immediate value. 394 //===----------------------------------------------------------------------===// 395 multiclass Addri_Pred<string mnemonic, bit PredNot> { 396 let isPredicatedFalse = PredNot in { 397 def NAME : T_Addri_Pred<PredNot, 0>; 398 // Predicate new 399 def NAME#new : T_Addri_Pred<PredNot, 1>; 400 } 401 } 402 403 let isExtendable = 1, isExtentSigned = 1, InputType = "imm" in 404 multiclass Addri_base<string mnemonic, SDNode OpNode> { 405 let CextOpcode = mnemonic, BaseOpcode = mnemonic#_ri in { 406 let opExtendable = 2, opExtentBits = 16, isPredicable = 1 in 407 def A2_#NAME : T_Addri<s16Ext>; 408 409 let opExtendable = 3, opExtentBits = 8, isPredicated = 1 in { 410 defm A2_p#NAME#t : Addri_Pred<mnemonic, 0>; 411 defm A2_p#NAME#f : Addri_Pred<mnemonic, 1>; 412 } 413 } 414 } 415 416 defm addi : Addri_base<"add", add>, ImmRegRel, PredNewRel; 417 418 def: Pat<(i32 (add I32:$Rs, s32ImmPred:$s16)), 419 (i32 (A2_addi I32:$Rs, imm:$s16))>; 420 421 let hasNewValue = 1, hasSideEffects = 0, isPseudo = 1 in 422 def A2_iconst 423 : ALU32_ri <(outs IntRegs:$Rd), 424 (ins s23_2Imm:$s23_2), 425 "$Rd = iconst(#$s23_2)"> {} 426 427 //===----------------------------------------------------------------------===// 428 // Template class used for the following ALU32 instructions. 429 // Rd=and(Rs,#s10) 430 // Rd=or(Rs,#s10) 431 //===----------------------------------------------------------------------===// 432 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 10, 433 InputType = "imm", hasNewValue = 1 in 434 class T_ALU32ri_logical <string mnemonic, SDNode OpNode, bits<2> MinOp> 435 : ALU32_ri <(outs IntRegs:$Rd), 436 (ins IntRegs:$Rs, s10Ext:$s10), 437 "$Rd = "#mnemonic#"($Rs, #$s10)" , 438 [(set (i32 IntRegs:$Rd), (OpNode (i32 IntRegs:$Rs), s32ImmPred:$s10))]> { 439 bits<5> Rd; 440 bits<5> Rs; 441 bits<10> s10; 442 let CextOpcode = mnemonic; 443 444 let IClass = 0b0111; 445 446 let Inst{27-24} = 0b0110; 447 let Inst{23-22} = MinOp; 448 let Inst{21} = s10{9}; 449 let Inst{20-16} = Rs; 450 let Inst{13-5} = s10{8-0}; 451 let Inst{4-0} = Rd; 452 } 453 454 def A2_orir : T_ALU32ri_logical<"or", or, 0b10>, ImmRegRel; 455 def A2_andir : T_ALU32ri_logical<"and", and, 0b00>, ImmRegRel; 456 457 // Subtract register from immediate 458 // Rd32=sub(#s10,Rs32) 459 let isExtendable = 1, CextOpcode = "sub", opExtendable = 1, isExtentSigned = 1, 460 opExtentBits = 10, InputType = "imm", hasNewValue = 1, hasSideEffects = 0 in 461 def A2_subri: ALU32_ri <(outs IntRegs:$Rd), (ins s10Ext:$s10, IntRegs:$Rs), 462 "$Rd = sub(#$s10, $Rs)", []>, ImmRegRel { 463 bits<5> Rd; 464 bits<10> s10; 465 bits<5> Rs; 466 467 let IClass = 0b0111; 468 469 let Inst{27-22} = 0b011001; 470 let Inst{21} = s10{9}; 471 let Inst{20-16} = Rs; 472 let Inst{13-5} = s10{8-0}; 473 let Inst{4-0} = Rd; 474 } 475 476 // Nop. 477 let hasSideEffects = 0 in 478 def A2_nop: ALU32Inst <(outs), (ins), "nop" > { 479 let IClass = 0b0111; 480 let Inst{27-24} = 0b1111; 481 } 482 483 def: Pat<(sub s32ImmPred:$s10, IntRegs:$Rs), 484 (A2_subri imm:$s10, IntRegs:$Rs)>; 485 486 // Rd = not(Rs) gets mapped to Rd=sub(#-1, Rs). 487 def: Pat<(not (i32 IntRegs:$src1)), 488 (A2_subri -1, IntRegs:$src1)>; 489 490 let hasSideEffects = 0, hasNewValue = 1 in 491 class T_tfr16<bit isHi> 492 : ALU32Inst <(outs IntRegs:$Rx), (ins IntRegs:$src1, u16Imm:$u16), 493 "$Rx"#!if(isHi, ".h", ".l")#" = #$u16", 494 [], "$src1 = $Rx" > { 495 bits<5> Rx; 496 bits<16> u16; 497 498 let IClass = 0b0111; 499 let Inst{27-26} = 0b00; 500 let Inst{25-24} = !if(isHi, 0b10, 0b01); 501 let Inst{23-22} = u16{15-14}; 502 let Inst{21} = 0b1; 503 let Inst{20-16} = Rx; 504 let Inst{13-0} = u16{13-0}; 505 } 506 507 def A2_tfril: T_tfr16<0>; 508 def A2_tfrih: T_tfr16<1>; 509 510 // Conditional transfer is an alias to conditional "Rd = add(Rs, #0)". 511 let isPredicated = 1, hasNewValue = 1, opNewValue = 0 in 512 class T_tfr_pred<bit isPredNot, bit isPredNew> 513 : ALU32Inst<(outs IntRegs:$dst), 514 (ins PredRegs:$src1, IntRegs:$src2), 515 "if ("#!if(isPredNot, "!", "")# 516 "$src1"#!if(isPredNew, ".new", "")# 517 ") $dst = $src2"> { 518 bits<5> dst; 519 bits<2> src1; 520 bits<5> src2; 521 522 let isPredicatedFalse = isPredNot; 523 let isPredicatedNew = isPredNew; 524 let IClass = 0b0111; 525 526 let Inst{27-24} = 0b0100; 527 let Inst{23} = isPredNot; 528 let Inst{13} = isPredNew; 529 let Inst{12-5} = 0; 530 let Inst{4-0} = dst; 531 let Inst{22-21} = src1; 532 let Inst{20-16} = src2; 533 } 534 535 let isPredicable = 1 in 536 class T_tfr : ALU32Inst<(outs IntRegs:$dst), (ins IntRegs:$src), 537 "$dst = $src"> { 538 bits<5> dst; 539 bits<5> src; 540 541 let IClass = 0b0111; 542 543 let Inst{27-21} = 0b0000011; 544 let Inst{20-16} = src; 545 let Inst{13} = 0b0; 546 let Inst{4-0} = dst; 547 } 548 549 let InputType = "reg", hasNewValue = 1, hasSideEffects = 0 in 550 multiclass tfr_base<string CextOp> { 551 let CextOpcode = CextOp, BaseOpcode = CextOp in { 552 def NAME : T_tfr; 553 554 // Predicate 555 def t : T_tfr_pred<0, 0>; 556 def f : T_tfr_pred<1, 0>; 557 // Predicate new 558 def tnew : T_tfr_pred<0, 1>; 559 def fnew : T_tfr_pred<1, 1>; 560 } 561 } 562 563 // Assembler mapped to C2_ccombinew[t|f|newt|newf]. 564 // Please don't add bits to this instruction as it'll be converted into 565 // 'combine' before object code emission. 566 let isPredicated = 1 in 567 class T_tfrp_pred<bit PredNot, bit PredNew> 568 : ALU32_rr <(outs DoubleRegs:$dst), 569 (ins PredRegs:$src1, DoubleRegs:$src2), 570 "if ("#!if(PredNot, "!", "")#"$src1" 571 #!if(PredNew, ".new", "")#") $dst = $src2" > { 572 let isPredicatedFalse = PredNot; 573 let isPredicatedNew = PredNew; 574 } 575 576 // Assembler mapped to A2_combinew. 577 // Please don't add bits to this instruction as it'll be converted into 578 // 'combine' before object code emission. 579 class T_tfrp : ALU32Inst <(outs DoubleRegs:$dst), 580 (ins DoubleRegs:$src), 581 "$dst = $src">; 582 583 let hasSideEffects = 0 in 584 multiclass TFR64_base<string BaseName> { 585 let BaseOpcode = BaseName in { 586 let isPredicable = 1 in 587 def NAME : T_tfrp; 588 // Predicate 589 def t : T_tfrp_pred <0, 0>; 590 def f : T_tfrp_pred <1, 0>; 591 // Predicate new 592 def tnew : T_tfrp_pred <0, 1>; 593 def fnew : T_tfrp_pred <1, 1>; 594 } 595 } 596 597 let InputType = "imm", isExtendable = 1, isExtentSigned = 1, opExtentBits = 12, 598 isMoveImm = 1, opExtendable = 2, BaseOpcode = "TFRI", CextOpcode = "TFR", 599 hasSideEffects = 0, isPredicated = 1, hasNewValue = 1 in 600 class T_TFRI_Pred<bit PredNot, bit PredNew> 601 : ALU32_ri<(outs IntRegs:$Rd), (ins PredRegs:$Pu, s12Ext:$s12), 602 "if ("#!if(PredNot,"!","")#"$Pu"#!if(PredNew,".new","")#") $Rd = #$s12", 603 [], "", ALU32_2op_tc_1_SLOT0123>, ImmRegRel, PredNewRel { 604 let isPredicatedFalse = PredNot; 605 let isPredicatedNew = PredNew; 606 607 bits<5> Rd; 608 bits<2> Pu; 609 bits<12> s12; 610 611 let IClass = 0b0111; 612 let Inst{27-24} = 0b1110; 613 let Inst{23} = PredNot; 614 let Inst{22-21} = Pu; 615 let Inst{20} = 0b0; 616 let Inst{19-16,12-5} = s12; 617 let Inst{13} = PredNew; 618 let Inst{4-0} = Rd; 619 } 620 621 def C2_cmoveit : T_TFRI_Pred<0, 0>; 622 def C2_cmoveif : T_TFRI_Pred<1, 0>; 623 def C2_cmovenewit : T_TFRI_Pred<0, 1>; 624 def C2_cmovenewif : T_TFRI_Pred<1, 1>; 625 626 let InputType = "imm", isExtendable = 1, isExtentSigned = 1, 627 CextOpcode = "TFR", BaseOpcode = "TFRI", hasNewValue = 1, opNewValue = 0, 628 isAsCheapAsAMove = 1 , opExtendable = 1, opExtentBits = 16, isMoveImm = 1, 629 isPredicated = 0, isPredicable = 1, isReMaterializable = 1 in 630 def A2_tfrsi : ALU32Inst<(outs IntRegs:$Rd), (ins s16Ext:$s16), "$Rd = #$s16", 631 [(set (i32 IntRegs:$Rd), s32ImmPred:$s16)], "", ALU32_2op_tc_1_SLOT0123>, 632 ImmRegRel, PredRel { 633 bits<5> Rd; 634 bits<16> s16; 635 636 let IClass = 0b0111; 637 let Inst{27-24} = 0b1000; 638 let Inst{23-22,20-16,13-5} = s16; 639 let Inst{4-0} = Rd; 640 } 641 642 defm A2_tfr : tfr_base<"TFR">, ImmRegRel, PredNewRel; 643 let isAsmParserOnly = 1 in 644 defm A2_tfrp : TFR64_base<"TFR64">, PredNewRel; 645 646 // Assembler mapped 647 let isReMaterializable = 1, isMoveImm = 1, isAsCheapAsAMove = 1, 648 isAsmParserOnly = 1 in 649 def A2_tfrpi : ALU64_rr<(outs DoubleRegs:$dst), (ins s8Imm64:$src1), 650 "$dst = #$src1", 651 [(set (i64 DoubleRegs:$dst), s8Imm64Pred:$src1)]>; 652 653 // TODO: see if this instruction can be deleted.. 654 let isExtendable = 1, opExtendable = 1, opExtentBits = 6, 655 isAsmParserOnly = 1 in { 656 def TFRI64_V4 : ALU64_rr<(outs DoubleRegs:$dst), (ins u64Imm:$src1), 657 "$dst = #$src1">; 658 def TFRI64_V2_ext : ALU64_rr<(outs DoubleRegs:$dst), 659 (ins s8Ext:$src1, s8Imm:$src2), 660 "$dst = combine(##$src1, #$src2)">; 661 } 662 663 //===----------------------------------------------------------------------===// 664 // ALU32/ALU - 665 //===----------------------------------------------------------------------===// 666 667 668 //===----------------------------------------------------------------------===// 669 // ALU32/PERM + 670 //===----------------------------------------------------------------------===// 671 // Scalar mux register immediate. 672 let hasSideEffects = 0, isExtentSigned = 1, CextOpcode = "MUX", 673 InputType = "imm", hasNewValue = 1, isExtendable = 1, opExtentBits = 8 in 674 class T_MUX1 <bit MajOp, dag ins, string AsmStr> 675 : ALU32Inst <(outs IntRegs:$Rd), ins, AsmStr>, ImmRegRel { 676 bits<5> Rd; 677 bits<2> Pu; 678 bits<8> s8; 679 bits<5> Rs; 680 681 let IClass = 0b0111; 682 let Inst{27-24} = 0b0011; 683 let Inst{23} = MajOp; 684 let Inst{22-21} = Pu; 685 let Inst{20-16} = Rs; 686 let Inst{13} = 0b0; 687 let Inst{12-5} = s8; 688 let Inst{4-0} = Rd; 689 } 690 691 let opExtendable = 2 in 692 def C2_muxri : T_MUX1<0b1, (ins PredRegs:$Pu, s8Ext:$s8, IntRegs:$Rs), 693 "$Rd = mux($Pu, #$s8, $Rs)">; 694 695 let opExtendable = 3 in 696 def C2_muxir : T_MUX1<0b0, (ins PredRegs:$Pu, IntRegs:$Rs, s8Ext:$s8), 697 "$Rd = mux($Pu, $Rs, #$s8)">; 698 699 def : Pat<(i32 (select I1:$Pu, s32ImmPred:$s8, I32:$Rs)), 700 (C2_muxri I1:$Pu, s32ImmPred:$s8, I32:$Rs)>; 701 702 def : Pat<(i32 (select I1:$Pu, I32:$Rs, s32ImmPred:$s8)), 703 (C2_muxir I1:$Pu, I32:$Rs, s32ImmPred:$s8)>; 704 705 // C2_muxii: Scalar mux immediates. 706 let isExtentSigned = 1, hasNewValue = 1, isExtendable = 1, 707 opExtentBits = 8, opExtendable = 2 in 708 def C2_muxii: ALU32Inst <(outs IntRegs:$Rd), 709 (ins PredRegs:$Pu, s8Ext:$s8, s8Imm:$S8), 710 "$Rd = mux($Pu, #$s8, #$S8)" , 711 [(set (i32 IntRegs:$Rd), 712 (i32 (select I1:$Pu, s32ImmPred:$s8, s8ImmPred:$S8)))] > { 713 bits<5> Rd; 714 bits<2> Pu; 715 bits<8> s8; 716 bits<8> S8; 717 718 let IClass = 0b0111; 719 720 let Inst{27-25} = 0b101; 721 let Inst{24-23} = Pu; 722 let Inst{22-16} = S8{7-1}; 723 let Inst{13} = S8{0}; 724 let Inst{12-5} = s8; 725 let Inst{4-0} = Rd; 726 } 727 728 let isCodeGenOnly = 1, isPseudo = 1 in 729 def MUX64_rr : ALU64_rr<(outs DoubleRegs:$Rd), 730 (ins PredRegs:$Pu, DoubleRegs:$Rs, DoubleRegs:$Rt), 731 ".error \"should not emit\" ", []>; 732 733 734 //===----------------------------------------------------------------------===// 735 // template class for non-predicated alu32_2op instructions 736 // - aslh, asrh, sxtb, sxth, zxth 737 //===----------------------------------------------------------------------===// 738 let hasNewValue = 1, opNewValue = 0 in 739 class T_ALU32_2op <string mnemonic, bits<3> minOp> : 740 ALU32Inst <(outs IntRegs:$Rd), (ins IntRegs:$Rs), 741 "$Rd = "#mnemonic#"($Rs)", [] > { 742 bits<5> Rd; 743 bits<5> Rs; 744 745 let IClass = 0b0111; 746 747 let Inst{27-24} = 0b0000; 748 let Inst{23-21} = minOp; 749 let Inst{13} = 0b0; 750 let Inst{4-0} = Rd; 751 let Inst{20-16} = Rs; 752 } 753 754 //===----------------------------------------------------------------------===// 755 // template class for predicated alu32_2op instructions 756 // - aslh, asrh, sxtb, sxth, zxtb, zxth 757 //===----------------------------------------------------------------------===// 758 let hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in 759 class T_ALU32_2op_Pred <string mnemonic, bits<3> minOp, bit isPredNot, 760 bit isPredNew > : 761 ALU32Inst <(outs IntRegs:$Rd), (ins PredRegs:$Pu, IntRegs:$Rs), 762 !if(isPredNot, "if (!$Pu", "if ($Pu") 763 #!if(isPredNew, ".new) ",") ")#"$Rd = "#mnemonic#"($Rs)"> { 764 bits<5> Rd; 765 bits<2> Pu; 766 bits<5> Rs; 767 768 let IClass = 0b0111; 769 770 let Inst{27-24} = 0b0000; 771 let Inst{23-21} = minOp; 772 let Inst{13} = 0b1; 773 let Inst{11} = isPredNot; 774 let Inst{10} = isPredNew; 775 let Inst{4-0} = Rd; 776 let Inst{9-8} = Pu; 777 let Inst{20-16} = Rs; 778 } 779 780 multiclass ALU32_2op_Pred<string mnemonic, bits<3> minOp, bit PredNot> { 781 let isPredicatedFalse = PredNot in { 782 def NAME : T_ALU32_2op_Pred<mnemonic, minOp, PredNot, 0>; 783 784 // Predicate new 785 let isPredicatedNew = 1 in 786 def NAME#new : T_ALU32_2op_Pred<mnemonic, minOp, PredNot, 1>; 787 } 788 } 789 790 multiclass ALU32_2op_base<string mnemonic, bits<3> minOp> { 791 let BaseOpcode = mnemonic in { 792 let isPredicable = 1, hasSideEffects = 0 in 793 def A2_#NAME : T_ALU32_2op<mnemonic, minOp>; 794 795 let isPredicated = 1, hasSideEffects = 0 in { 796 defm A4_p#NAME#t : ALU32_2op_Pred<mnemonic, minOp, 0>; 797 defm A4_p#NAME#f : ALU32_2op_Pred<mnemonic, minOp, 1>; 798 } 799 } 800 } 801 802 defm aslh : ALU32_2op_base<"aslh", 0b000>, PredNewRel; 803 defm asrh : ALU32_2op_base<"asrh", 0b001>, PredNewRel; 804 defm sxtb : ALU32_2op_base<"sxtb", 0b101>, PredNewRel; 805 defm sxth : ALU32_2op_base<"sxth", 0b111>, PredNewRel; 806 defm zxth : ALU32_2op_base<"zxth", 0b110>, PredNewRel; 807 808 // Rd=zxtb(Rs): assembler mapped to Rd=and(Rs,#255). 809 // Compiler would want to generate 'zxtb' instead of 'and' becuase 'zxtb' has 810 // predicated forms while 'and' doesn't. Since integrated assembler can't 811 // handle 'mapped' instructions, we need to encode 'zxtb' same as 'and' where 812 // immediate operand is set to '255'. 813 814 let hasNewValue = 1, opNewValue = 0 in 815 class T_ZXTB: ALU32Inst < (outs IntRegs:$Rd), (ins IntRegs:$Rs), 816 "$Rd = zxtb($Rs)", [] > { // Rd = and(Rs,255) 817 bits<5> Rd; 818 bits<5> Rs; 819 bits<10> s10 = 255; 820 821 let IClass = 0b0111; 822 823 let Inst{27-22} = 0b011000; 824 let Inst{4-0} = Rd; 825 let Inst{20-16} = Rs; 826 let Inst{21} = s10{9}; 827 let Inst{13-5} = s10{8-0}; 828 } 829 830 //Rd=zxtb(Rs): assembler mapped to "Rd=and(Rs,#255) 831 multiclass ZXTB_base <string mnemonic, bits<3> minOp> { 832 let BaseOpcode = mnemonic in { 833 let isPredicable = 1, hasSideEffects = 0 in 834 def A2_#NAME : T_ZXTB; 835 836 let isPredicated = 1, hasSideEffects = 0 in { 837 defm A4_p#NAME#t : ALU32_2op_Pred<mnemonic, minOp, 0>; 838 defm A4_p#NAME#f : ALU32_2op_Pred<mnemonic, minOp, 1>; 839 } 840 } 841 } 842 843 defm zxtb : ZXTB_base<"zxtb",0b100>, PredNewRel; 844 845 def: Pat<(shl I32:$src1, (i32 16)), (A2_aslh I32:$src1)>; 846 def: Pat<(sra I32:$src1, (i32 16)), (A2_asrh I32:$src1)>; 847 def: Pat<(sext_inreg I32:$src1, i8), (A2_sxtb I32:$src1)>; 848 def: Pat<(sext_inreg I32:$src1, i16), (A2_sxth I32:$src1)>; 849 850 //===----------------------------------------------------------------------===// 851 // Template class for vector add and avg 852 //===----------------------------------------------------------------------===// 853 854 class T_VectALU_64 <string opc, bits<3> majOp, bits<3> minOp, 855 bit isSat, bit isRnd, bit isCrnd, bit SwapOps > 856 : ALU64_rr < (outs DoubleRegs:$Rdd), 857 (ins DoubleRegs:$Rss, DoubleRegs:$Rtt), 858 "$Rdd = "#opc#"($Rss, $Rtt)"#!if(isRnd, ":rnd", "") 859 #!if(isCrnd,":crnd","") 860 #!if(isSat, ":sat", ""), 861 [], "", ALU64_tc_2_SLOT23 > { 862 bits<5> Rdd; 863 bits<5> Rss; 864 bits<5> Rtt; 865 866 let IClass = 0b1101; 867 868 let Inst{27-24} = 0b0011; 869 let Inst{23-21} = majOp; 870 let Inst{20-16} = !if (SwapOps, Rtt, Rss); 871 let Inst{12-8} = !if (SwapOps, Rss, Rtt); 872 let Inst{7-5} = minOp; 873 let Inst{4-0} = Rdd; 874 } 875 876 // ALU64 - Vector add 877 // Rdd=vadd[u][bhw](Rss,Rtt) 878 let Itinerary = ALU64_tc_1_SLOT23 in { 879 def A2_vaddub : T_VectALU_64 < "vaddub", 0b000, 0b000, 0, 0, 0, 0>; 880 def A2_vaddh : T_VectALU_64 < "vaddh", 0b000, 0b010, 0, 0, 0, 0>; 881 def A2_vaddw : T_VectALU_64 < "vaddw", 0b000, 0b101, 0, 0, 0, 0>; 882 } 883 884 // Rdd=vadd[u][bhw](Rss,Rtt):sat 885 let Defs = [USR_OVF] in { 886 def A2_vaddubs : T_VectALU_64 < "vaddub", 0b000, 0b001, 1, 0, 0, 0>; 887 def A2_vaddhs : T_VectALU_64 < "vaddh", 0b000, 0b011, 1, 0, 0, 0>; 888 def A2_vadduhs : T_VectALU_64 < "vadduh", 0b000, 0b100, 1, 0, 0, 0>; 889 def A2_vaddws : T_VectALU_64 < "vaddw", 0b000, 0b110, 1, 0, 0, 0>; 890 } 891 892 // ALU64 - Vector average 893 // Rdd=vavg[u][bhw](Rss,Rtt) 894 let Itinerary = ALU64_tc_1_SLOT23 in { 895 def A2_vavgub : T_VectALU_64 < "vavgub", 0b010, 0b000, 0, 0, 0, 0>; 896 def A2_vavgh : T_VectALU_64 < "vavgh", 0b010, 0b010, 0, 0, 0, 0>; 897 def A2_vavguh : T_VectALU_64 < "vavguh", 0b010, 0b101, 0, 0, 0, 0>; 898 def A2_vavgw : T_VectALU_64 < "vavgw", 0b011, 0b000, 0, 0, 0, 0>; 899 def A2_vavguw : T_VectALU_64 < "vavguw", 0b011, 0b011, 0, 0, 0, 0>; 900 } 901 902 // Rdd=vavg[u][bhw](Rss,Rtt)[:rnd|:crnd] 903 def A2_vavgubr : T_VectALU_64 < "vavgub", 0b010, 0b001, 0, 1, 0, 0>; 904 def A2_vavghr : T_VectALU_64 < "vavgh", 0b010, 0b011, 0, 1, 0, 0>; 905 def A2_vavghcr : T_VectALU_64 < "vavgh", 0b010, 0b100, 0, 0, 1, 0>; 906 def A2_vavguhr : T_VectALU_64 < "vavguh", 0b010, 0b110, 0, 1, 0, 0>; 907 908 def A2_vavgwr : T_VectALU_64 < "vavgw", 0b011, 0b001, 0, 1, 0, 0>; 909 def A2_vavgwcr : T_VectALU_64 < "vavgw", 0b011, 0b010, 0, 0, 1, 0>; 910 def A2_vavguwr : T_VectALU_64 < "vavguw", 0b011, 0b100, 0, 1, 0, 0>; 911 912 // Rdd=vnavg[bh](Rss,Rtt) 913 let Itinerary = ALU64_tc_1_SLOT23 in { 914 def A2_vnavgh : T_VectALU_64 < "vnavgh", 0b100, 0b000, 0, 0, 0, 1>; 915 def A2_vnavgw : T_VectALU_64 < "vnavgw", 0b100, 0b011, 0, 0, 0, 1>; 916 } 917 918 // Rdd=vnavg[bh](Rss,Rtt)[:rnd|:crnd]:sat 919 let Defs = [USR_OVF] in { 920 def A2_vnavghr : T_VectALU_64 < "vnavgh", 0b100, 0b001, 1, 1, 0, 1>; 921 def A2_vnavghcr : T_VectALU_64 < "vnavgh", 0b100, 0b010, 1, 0, 1, 1>; 922 def A2_vnavgwr : T_VectALU_64 < "vnavgw", 0b100, 0b100, 1, 1, 0, 1>; 923 def A2_vnavgwcr : T_VectALU_64 < "vnavgw", 0b100, 0b110, 1, 0, 1, 1>; 924 } 925 926 // Rdd=vsub[u][bh](Rss,Rtt) 927 let Itinerary = ALU64_tc_1_SLOT23 in { 928 def A2_vsubub : T_VectALU_64 < "vsubub", 0b001, 0b000, 0, 0, 0, 1>; 929 def A2_vsubh : T_VectALU_64 < "vsubh", 0b001, 0b010, 0, 0, 0, 1>; 930 def A2_vsubw : T_VectALU_64 < "vsubw", 0b001, 0b101, 0, 0, 0, 1>; 931 } 932 933 // Rdd=vsub[u][bh](Rss,Rtt):sat 934 let Defs = [USR_OVF] in { 935 def A2_vsububs : T_VectALU_64 < "vsubub", 0b001, 0b001, 1, 0, 0, 1>; 936 def A2_vsubhs : T_VectALU_64 < "vsubh", 0b001, 0b011, 1, 0, 0, 1>; 937 def A2_vsubuhs : T_VectALU_64 < "vsubuh", 0b001, 0b100, 1, 0, 0, 1>; 938 def A2_vsubws : T_VectALU_64 < "vsubw", 0b001, 0b110, 1, 0, 0, 1>; 939 } 940 941 // Rdd=vmax[u][bhw](Rss,Rtt) 942 def A2_vmaxb : T_VectALU_64 < "vmaxb", 0b110, 0b110, 0, 0, 0, 1>; 943 def A2_vmaxub : T_VectALU_64 < "vmaxub", 0b110, 0b000, 0, 0, 0, 1>; 944 def A2_vmaxh : T_VectALU_64 < "vmaxh", 0b110, 0b001, 0, 0, 0, 1>; 945 def A2_vmaxuh : T_VectALU_64 < "vmaxuh", 0b110, 0b010, 0, 0, 0, 1>; 946 def A2_vmaxw : T_VectALU_64 < "vmaxw", 0b110, 0b011, 0, 0, 0, 1>; 947 def A2_vmaxuw : T_VectALU_64 < "vmaxuw", 0b101, 0b101, 0, 0, 0, 1>; 948 949 // Rdd=vmin[u][bhw](Rss,Rtt) 950 def A2_vminb : T_VectALU_64 < "vminb", 0b110, 0b111, 0, 0, 0, 1>; 951 def A2_vminub : T_VectALU_64 < "vminub", 0b101, 0b000, 0, 0, 0, 1>; 952 def A2_vminh : T_VectALU_64 < "vminh", 0b101, 0b001, 0, 0, 0, 1>; 953 def A2_vminuh : T_VectALU_64 < "vminuh", 0b101, 0b010, 0, 0, 0, 1>; 954 def A2_vminw : T_VectALU_64 < "vminw", 0b101, 0b011, 0, 0, 0, 1>; 955 def A2_vminuw : T_VectALU_64 < "vminuw", 0b101, 0b100, 0, 0, 0, 1>; 956 957 //===----------------------------------------------------------------------===// 958 // Template class for vector compare 959 //===----------------------------------------------------------------------===// 960 let hasSideEffects = 0 in 961 class T_vcmp <string Str, bits<4> minOp> 962 : ALU64_rr <(outs PredRegs:$Pd), 963 (ins DoubleRegs:$Rss, DoubleRegs:$Rtt), 964 "$Pd = "#Str#"($Rss, $Rtt)", [], 965 "", ALU64_tc_2early_SLOT23> { 966 bits<2> Pd; 967 bits<5> Rss; 968 bits<5> Rtt; 969 970 let IClass = 0b1101; 971 972 let Inst{27-23} = 0b00100; 973 let Inst{13} = minOp{3}; 974 let Inst{7-5} = minOp{2-0}; 975 let Inst{1-0} = Pd; 976 let Inst{20-16} = Rss; 977 let Inst{12-8} = Rtt; 978 } 979 980 class T_vcmp_pat<InstHexagon MI, PatFrag Op, ValueType T> 981 : Pat<(i1 (Op (T DoubleRegs:$Rss), (T DoubleRegs:$Rtt))), 982 (i1 (MI DoubleRegs:$Rss, DoubleRegs:$Rtt))>; 983 984 // Vector compare bytes 985 def A2_vcmpbeq : T_vcmp <"vcmpb.eq", 0b0110>; 986 def A2_vcmpbgtu : T_vcmp <"vcmpb.gtu", 0b0111>; 987 988 // Vector compare halfwords 989 def A2_vcmpheq : T_vcmp <"vcmph.eq", 0b0011>; 990 def A2_vcmphgt : T_vcmp <"vcmph.gt", 0b0100>; 991 def A2_vcmphgtu : T_vcmp <"vcmph.gtu", 0b0101>; 992 993 // Vector compare words 994 def A2_vcmpweq : T_vcmp <"vcmpw.eq", 0b0000>; 995 def A2_vcmpwgt : T_vcmp <"vcmpw.gt", 0b0001>; 996 def A2_vcmpwgtu : T_vcmp <"vcmpw.gtu", 0b0010>; 997 998 def: T_vcmp_pat<A2_vcmpbeq, seteq, v8i8>; 999 def: T_vcmp_pat<A2_vcmpbgtu, setugt, v8i8>; 1000 def: T_vcmp_pat<A2_vcmpheq, seteq, v4i16>; 1001 def: T_vcmp_pat<A2_vcmphgt, setgt, v4i16>; 1002 def: T_vcmp_pat<A2_vcmphgtu, setugt, v4i16>; 1003 def: T_vcmp_pat<A2_vcmpweq, seteq, v2i32>; 1004 def: T_vcmp_pat<A2_vcmpwgt, setgt, v2i32>; 1005 def: T_vcmp_pat<A2_vcmpwgtu, setugt, v2i32>; 1006 1007 //===----------------------------------------------------------------------===// 1008 // ALU32/PERM - 1009 //===----------------------------------------------------------------------===// 1010 1011 1012 //===----------------------------------------------------------------------===// 1013 // ALU32/PRED + 1014 //===----------------------------------------------------------------------===// 1015 // No bits needed. If cmp.ge is found the assembler parser will 1016 // transform it to cmp.gt subtracting 1 from the immediate. 1017 let isPseudo = 1 in { 1018 def C2_cmpgei: ALU32Inst < 1019 (outs PredRegs:$Pd), (ins IntRegs:$Rs, s8Ext:$s8), 1020 "$Pd = cmp.ge($Rs, #$s8)">; 1021 def C2_cmpgeui: ALU32Inst < 1022 (outs PredRegs:$Pd), (ins IntRegs:$Rs, u8Ext:$s8), 1023 "$Pd = cmp.geu($Rs, #$s8)">; 1024 } 1025 1026 1027 //===----------------------------------------------------------------------===// 1028 // ALU32/PRED - 1029 //===----------------------------------------------------------------------===// 1030 1031 1032 //===----------------------------------------------------------------------===// 1033 // ALU64/ALU + 1034 //===----------------------------------------------------------------------===// 1035 // Add. 1036 //===----------------------------------------------------------------------===// 1037 // Template Class 1038 // Add/Subtract halfword 1039 // Rd=add(Rt.L,Rs.[HL])[:sat] 1040 // Rd=sub(Rt.L,Rs.[HL])[:sat] 1041 // Rd=add(Rt.[LH],Rs.[HL])[:sat][:<16] 1042 // Rd=sub(Rt.[LH],Rs.[HL])[:sat][:<16] 1043 //===----------------------------------------------------------------------===// 1044 1045 let hasNewValue = 1, opNewValue = 0 in 1046 class T_XTYPE_ADD_SUB <bits<2> LHbits, bit isSat, bit hasShift, bit isSub> 1047 : ALU64Inst <(outs IntRegs:$Rd), (ins IntRegs:$Rt, IntRegs:$Rs), 1048 "$Rd = "#!if(isSub,"sub","add")#"($Rt." 1049 #!if(hasShift, !if(LHbits{1},"h","l"),"l") #", $Rs." 1050 #!if(hasShift, !if(LHbits{0},"h)","l)"), !if(LHbits{1},"h)","l)")) 1051 #!if(isSat,":sat","") 1052 #!if(hasShift,":<<16",""), [], "", ALU64_tc_1_SLOT23> { 1053 bits<5> Rd; 1054 bits<5> Rt; 1055 bits<5> Rs; 1056 let IClass = 0b1101; 1057 1058 let Inst{27-23} = 0b01010; 1059 let Inst{22} = hasShift; 1060 let Inst{21} = isSub; 1061 let Inst{7} = isSat; 1062 let Inst{6-5} = LHbits; 1063 let Inst{4-0} = Rd; 1064 let Inst{12-8} = Rt; 1065 let Inst{20-16} = Rs; 1066 } 1067 1068 //Rd=sub(Rt.L,Rs.[LH]) 1069 def A2_subh_l16_ll : T_XTYPE_ADD_SUB <0b00, 0, 0, 1>; 1070 def A2_subh_l16_hl : T_XTYPE_ADD_SUB <0b10, 0, 0, 1>; 1071 1072 //Rd=add(Rt.L,Rs.[LH]) 1073 def A2_addh_l16_ll : T_XTYPE_ADD_SUB <0b00, 0, 0, 0>; 1074 def A2_addh_l16_hl : T_XTYPE_ADD_SUB <0b10, 0, 0, 0>; 1075 1076 let Itinerary = ALU64_tc_2_SLOT23, Defs = [USR_OVF] in { 1077 //Rd=sub(Rt.L,Rs.[LH]):sat 1078 def A2_subh_l16_sat_ll : T_XTYPE_ADD_SUB <0b00, 1, 0, 1>; 1079 def A2_subh_l16_sat_hl : T_XTYPE_ADD_SUB <0b10, 1, 0, 1>; 1080 1081 //Rd=add(Rt.L,Rs.[LH]):sat 1082 def A2_addh_l16_sat_ll : T_XTYPE_ADD_SUB <0b00, 1, 0, 0>; 1083 def A2_addh_l16_sat_hl : T_XTYPE_ADD_SUB <0b10, 1, 0, 0>; 1084 } 1085 1086 //Rd=sub(Rt.[LH],Rs.[LH]):<<16 1087 def A2_subh_h16_ll : T_XTYPE_ADD_SUB <0b00, 0, 1, 1>; 1088 def A2_subh_h16_lh : T_XTYPE_ADD_SUB <0b01, 0, 1, 1>; 1089 def A2_subh_h16_hl : T_XTYPE_ADD_SUB <0b10, 0, 1, 1>; 1090 def A2_subh_h16_hh : T_XTYPE_ADD_SUB <0b11, 0, 1, 1>; 1091 1092 //Rd=add(Rt.[LH],Rs.[LH]):<<16 1093 def A2_addh_h16_ll : T_XTYPE_ADD_SUB <0b00, 0, 1, 0>; 1094 def A2_addh_h16_lh : T_XTYPE_ADD_SUB <0b01, 0, 1, 0>; 1095 def A2_addh_h16_hl : T_XTYPE_ADD_SUB <0b10, 0, 1, 0>; 1096 def A2_addh_h16_hh : T_XTYPE_ADD_SUB <0b11, 0, 1, 0>; 1097 1098 let Itinerary = ALU64_tc_2_SLOT23, Defs = [USR_OVF] in { 1099 //Rd=sub(Rt.[LH],Rs.[LH]):sat:<<16 1100 def A2_subh_h16_sat_ll : T_XTYPE_ADD_SUB <0b00, 1, 1, 1>; 1101 def A2_subh_h16_sat_lh : T_XTYPE_ADD_SUB <0b01, 1, 1, 1>; 1102 def A2_subh_h16_sat_hl : T_XTYPE_ADD_SUB <0b10, 1, 1, 1>; 1103 def A2_subh_h16_sat_hh : T_XTYPE_ADD_SUB <0b11, 1, 1, 1>; 1104 1105 //Rd=add(Rt.[LH],Rs.[LH]):sat:<<16 1106 def A2_addh_h16_sat_ll : T_XTYPE_ADD_SUB <0b00, 1, 1, 0>; 1107 def A2_addh_h16_sat_lh : T_XTYPE_ADD_SUB <0b01, 1, 1, 0>; 1108 def A2_addh_h16_sat_hl : T_XTYPE_ADD_SUB <0b10, 1, 1, 0>; 1109 def A2_addh_h16_sat_hh : T_XTYPE_ADD_SUB <0b11, 1, 1, 0>; 1110 } 1111 1112 // Add halfword. 1113 def: Pat<(sext_inreg (add I32:$src1, I32:$src2), i16), 1114 (A2_addh_l16_ll I32:$src1, I32:$src2)>; 1115 1116 def: Pat<(sra (add (shl I32:$src1, (i32 16)), I32:$src2), (i32 16)), 1117 (A2_addh_l16_hl I32:$src1, I32:$src2)>; 1118 1119 def: Pat<(shl (add I32:$src1, I32:$src2), (i32 16)), 1120 (A2_addh_h16_ll I32:$src1, I32:$src2)>; 1121 1122 // Subtract halfword. 1123 def: Pat<(sext_inreg (sub I32:$src1, I32:$src2), i16), 1124 (A2_subh_l16_ll I32:$src1, I32:$src2)>; 1125 1126 def: Pat<(shl (sub I32:$src1, I32:$src2), (i32 16)), 1127 (A2_subh_h16_ll I32:$src1, I32:$src2)>; 1128 1129 let hasSideEffects = 0, hasNewValue = 1 in 1130 def S2_parityp: ALU64Inst<(outs IntRegs:$Rd), 1131 (ins DoubleRegs:$Rs, DoubleRegs:$Rt), 1132 "$Rd = parity($Rs, $Rt)", [], "", ALU64_tc_2_SLOT23> { 1133 bits<5> Rd; 1134 bits<5> Rs; 1135 bits<5> Rt; 1136 1137 let IClass = 0b1101; 1138 let Inst{27-24} = 0b0000; 1139 let Inst{20-16} = Rs; 1140 let Inst{12-8} = Rt; 1141 let Inst{4-0} = Rd; 1142 } 1143 1144 let hasNewValue = 1, opNewValue = 0, hasSideEffects = 0 in 1145 class T_XTYPE_MIN_MAX < bit isMax, bit isUnsigned > 1146 : ALU64Inst < (outs IntRegs:$Rd), (ins IntRegs:$Rt, IntRegs:$Rs), 1147 "$Rd = "#!if(isMax,"max","min")#!if(isUnsigned,"u","") 1148 #"($Rt, $Rs)", [], "", ALU64_tc_2_SLOT23> { 1149 bits<5> Rd; 1150 bits<5> Rt; 1151 bits<5> Rs; 1152 1153 let IClass = 0b1101; 1154 1155 let Inst{27-23} = 0b01011; 1156 let Inst{22-21} = !if(isMax, 0b10, 0b01); 1157 let Inst{7} = isUnsigned; 1158 let Inst{4-0} = Rd; 1159 let Inst{12-8} = !if(isMax, Rs, Rt); 1160 let Inst{20-16} = !if(isMax, Rt, Rs); 1161 } 1162 1163 def A2_min : T_XTYPE_MIN_MAX < 0, 0 >; 1164 def A2_minu : T_XTYPE_MIN_MAX < 0, 1 >; 1165 def A2_max : T_XTYPE_MIN_MAX < 1, 0 >; 1166 def A2_maxu : T_XTYPE_MIN_MAX < 1, 1 >; 1167 1168 // Here, depending on the operand being selected, we'll either generate a 1169 // min or max instruction. 1170 // Ex: 1171 // (a>b)?a:b --> max(a,b) => Here check performed is '>' and the value selected 1172 // is the larger of two. So, the corresponding HexagonInst is passed in 'Inst'. 1173 // (a>b)?b:a --> min(a,b) => Here check performed is '>' but the smaller value 1174 // is selected and the corresponding HexagonInst is passed in 'SwapInst'. 1175 1176 multiclass T_MinMax_pats <PatFrag Op, RegisterClass RC, ValueType VT, 1177 InstHexagon Inst, InstHexagon SwapInst> { 1178 def: Pat<(select (i1 (Op (VT RC:$src1), (VT RC:$src2))), 1179 (VT RC:$src1), (VT RC:$src2)), 1180 (Inst RC:$src1, RC:$src2)>; 1181 def: Pat<(select (i1 (Op (VT RC:$src1), (VT RC:$src2))), 1182 (VT RC:$src2), (VT RC:$src1)), 1183 (SwapInst RC:$src1, RC:$src2)>; 1184 } 1185 1186 1187 multiclass MinMax_pats <PatFrag Op, InstHexagon Inst, InstHexagon SwapInst> { 1188 defm: T_MinMax_pats<Op, IntRegs, i32, Inst, SwapInst>; 1189 1190 def: Pat<(sext_inreg (i32 (select (i1 (Op (i32 PositiveHalfWord:$src1), 1191 (i32 PositiveHalfWord:$src2))), 1192 (i32 PositiveHalfWord:$src1), 1193 (i32 PositiveHalfWord:$src2))), i16), 1194 (Inst IntRegs:$src1, IntRegs:$src2)>; 1195 1196 def: Pat<(sext_inreg (i32 (select (i1 (Op (i32 PositiveHalfWord:$src1), 1197 (i32 PositiveHalfWord:$src2))), 1198 (i32 PositiveHalfWord:$src2), 1199 (i32 PositiveHalfWord:$src1))), i16), 1200 (SwapInst IntRegs:$src1, IntRegs:$src2)>; 1201 } 1202 1203 let AddedComplexity = 200 in { 1204 defm: MinMax_pats<setge, A2_max, A2_min>; 1205 defm: MinMax_pats<setgt, A2_max, A2_min>; 1206 defm: MinMax_pats<setle, A2_min, A2_max>; 1207 defm: MinMax_pats<setlt, A2_min, A2_max>; 1208 defm: MinMax_pats<setuge, A2_maxu, A2_minu>; 1209 defm: MinMax_pats<setugt, A2_maxu, A2_minu>; 1210 defm: MinMax_pats<setule, A2_minu, A2_maxu>; 1211 defm: MinMax_pats<setult, A2_minu, A2_maxu>; 1212 } 1213 1214 class T_cmp64_rr<string mnemonic, bits<3> MinOp, bit IsComm> 1215 : ALU64_rr<(outs PredRegs:$Pd), (ins DoubleRegs:$Rs, DoubleRegs:$Rt), 1216 "$Pd = "#mnemonic#"($Rs, $Rt)", [], "", ALU64_tc_2early_SLOT23> { 1217 let isCompare = 1; 1218 let isCommutable = IsComm; 1219 let hasSideEffects = 0; 1220 1221 bits<2> Pd; 1222 bits<5> Rs; 1223 bits<5> Rt; 1224 1225 let IClass = 0b1101; 1226 let Inst{27-21} = 0b0010100; 1227 let Inst{20-16} = Rs; 1228 let Inst{12-8} = Rt; 1229 let Inst{7-5} = MinOp; 1230 let Inst{1-0} = Pd; 1231 } 1232 1233 def C2_cmpeqp : T_cmp64_rr<"cmp.eq", 0b000, 1>; 1234 def C2_cmpgtp : T_cmp64_rr<"cmp.gt", 0b010, 0>; 1235 def C2_cmpgtup : T_cmp64_rr<"cmp.gtu", 0b100, 0>; 1236 1237 class T_cmp64_rr_pat<InstHexagon MI, PatFrag CmpOp> 1238 : Pat<(i1 (CmpOp (i64 DoubleRegs:$Rs), (i64 DoubleRegs:$Rt))), 1239 (i1 (MI DoubleRegs:$Rs, DoubleRegs:$Rt))>; 1240 1241 def: T_cmp64_rr_pat<C2_cmpeqp, seteq>; 1242 def: T_cmp64_rr_pat<C2_cmpgtp, setgt>; 1243 def: T_cmp64_rr_pat<C2_cmpgtup, setugt>; 1244 def: T_cmp64_rr_pat<C2_cmpgtp, RevCmp<setlt>>; 1245 def: T_cmp64_rr_pat<C2_cmpgtup, RevCmp<setult>>; 1246 1247 def C2_vmux : ALU64_rr<(outs DoubleRegs:$Rd), 1248 (ins PredRegs:$Pu, DoubleRegs:$Rs, DoubleRegs:$Rt), 1249 "$Rd = vmux($Pu, $Rs, $Rt)", [], "", ALU64_tc_1_SLOT23> { 1250 let hasSideEffects = 0; 1251 1252 bits<5> Rd; 1253 bits<2> Pu; 1254 bits<5> Rs; 1255 bits<5> Rt; 1256 1257 let IClass = 0b1101; 1258 let Inst{27-24} = 0b0001; 1259 let Inst{20-16} = Rs; 1260 let Inst{12-8} = Rt; 1261 let Inst{6-5} = Pu; 1262 let Inst{4-0} = Rd; 1263 } 1264 1265 class T_ALU64_rr<string mnemonic, string suffix, bits<4> RegType, 1266 bits<3> MajOp, bits<3> MinOp, bit OpsRev, bit IsComm, 1267 string Op2Pfx> 1268 : ALU64_rr<(outs DoubleRegs:$Rd), (ins DoubleRegs:$Rs, DoubleRegs:$Rt), 1269 "$Rd = " #mnemonic# "($Rs, " #Op2Pfx# "$Rt)" #suffix, [], 1270 "", ALU64_tc_1_SLOT23> { 1271 let hasSideEffects = 0; 1272 let isCommutable = IsComm; 1273 1274 bits<5> Rs; 1275 bits<5> Rt; 1276 bits<5> Rd; 1277 1278 let IClass = 0b1101; 1279 let Inst{27-24} = RegType; 1280 let Inst{23-21} = MajOp; 1281 let Inst{20-16} = !if (OpsRev,Rt,Rs); 1282 let Inst{12-8} = !if (OpsRev,Rs,Rt); 1283 let Inst{7-5} = MinOp; 1284 let Inst{4-0} = Rd; 1285 } 1286 1287 class T_ALU64_arith<string mnemonic, bits<3> MajOp, bits<3> MinOp, bit IsSat, 1288 bit OpsRev, bit IsComm> 1289 : T_ALU64_rr<mnemonic, !if(IsSat,":sat",""), 0b0011, MajOp, MinOp, OpsRev, 1290 IsComm, "">; 1291 1292 def A2_addp : T_ALU64_arith<"add", 0b000, 0b111, 0, 0, 1>; 1293 def A2_subp : T_ALU64_arith<"sub", 0b001, 0b111, 0, 1, 0>; 1294 1295 def: Pat<(i64 (add I64:$Rs, I64:$Rt)), (A2_addp I64:$Rs, I64:$Rt)>; 1296 def: Pat<(i64 (sub I64:$Rs, I64:$Rt)), (A2_subp I64:$Rs, I64:$Rt)>; 1297 1298 class T_ALU64_logical<string mnemonic, bits<3> MinOp, bit OpsRev, bit IsComm, 1299 bit IsNeg> 1300 : T_ALU64_rr<mnemonic, "", 0b0011, 0b111, MinOp, OpsRev, IsComm, 1301 !if(IsNeg,"~","")>; 1302 1303 def A2_andp : T_ALU64_logical<"and", 0b000, 0, 1, 0>; 1304 def A2_orp : T_ALU64_logical<"or", 0b010, 0, 1, 0>; 1305 def A2_xorp : T_ALU64_logical<"xor", 0b100, 0, 1, 0>; 1306 1307 def: Pat<(i64 (and I64:$Rs, I64:$Rt)), (A2_andp I64:$Rs, I64:$Rt)>; 1308 def: Pat<(i64 (or I64:$Rs, I64:$Rt)), (A2_orp I64:$Rs, I64:$Rt)>; 1309 def: Pat<(i64 (xor I64:$Rs, I64:$Rt)), (A2_xorp I64:$Rs, I64:$Rt)>; 1310 1311 //===----------------------------------------------------------------------===// 1312 // ALU64/ALU - 1313 //===----------------------------------------------------------------------===// 1314 1315 //===----------------------------------------------------------------------===// 1316 // ALU64/BIT + 1317 //===----------------------------------------------------------------------===// 1318 // 1319 //===----------------------------------------------------------------------===// 1320 // ALU64/BIT - 1321 //===----------------------------------------------------------------------===// 1322 1323 //===----------------------------------------------------------------------===// 1324 // ALU64/PERM + 1325 //===----------------------------------------------------------------------===// 1326 // 1327 //===----------------------------------------------------------------------===// 1328 // ALU64/PERM - 1329 //===----------------------------------------------------------------------===// 1330 1331 //===----------------------------------------------------------------------===// 1332 // CR + 1333 //===----------------------------------------------------------------------===// 1334 // Logical reductions on predicates. 1335 1336 // Looping instructions. 1337 1338 // Pipelined looping instructions. 1339 1340 // Logical operations on predicates. 1341 let hasSideEffects = 0 in 1342 class T_LOGICAL_1OP<string MnOp, bits<2> OpBits> 1343 : CRInst<(outs PredRegs:$Pd), (ins PredRegs:$Ps), 1344 "$Pd = " # MnOp # "($Ps)", [], "", CR_tc_2early_SLOT23> { 1345 bits<2> Pd; 1346 bits<2> Ps; 1347 1348 let IClass = 0b0110; 1349 let Inst{27-23} = 0b10111; 1350 let Inst{22-21} = OpBits; 1351 let Inst{20} = 0b0; 1352 let Inst{17-16} = Ps; 1353 let Inst{13} = 0b0; 1354 let Inst{1-0} = Pd; 1355 } 1356 1357 def C2_any8 : T_LOGICAL_1OP<"any8", 0b00>; 1358 def C2_all8 : T_LOGICAL_1OP<"all8", 0b01>; 1359 def C2_not : T_LOGICAL_1OP<"not", 0b10>; 1360 1361 def: Pat<(i1 (not (i1 PredRegs:$Ps))), 1362 (C2_not PredRegs:$Ps)>; 1363 1364 let hasSideEffects = 0 in 1365 class T_LOGICAL_2OP<string MnOp, bits<3> OpBits, bit IsNeg, bit Rev> 1366 : CRInst<(outs PredRegs:$Pd), (ins PredRegs:$Ps, PredRegs:$Pt), 1367 "$Pd = " # MnOp # "($Ps, " # !if (IsNeg,"!","") # "$Pt)", 1368 [], "", CR_tc_2early_SLOT23> { 1369 bits<2> Pd; 1370 bits<2> Ps; 1371 bits<2> Pt; 1372 1373 let IClass = 0b0110; 1374 let Inst{27-24} = 0b1011; 1375 let Inst{23-21} = OpBits; 1376 let Inst{20} = 0b0; 1377 let Inst{17-16} = !if(Rev,Pt,Ps); // Rs and Rt are reversed for some 1378 let Inst{13} = 0b0; // instructions. 1379 let Inst{9-8} = !if(Rev,Ps,Pt); 1380 let Inst{1-0} = Pd; 1381 } 1382 1383 def C2_and : T_LOGICAL_2OP<"and", 0b000, 0, 1>; 1384 def C2_or : T_LOGICAL_2OP<"or", 0b001, 0, 1>; 1385 def C2_xor : T_LOGICAL_2OP<"xor", 0b010, 0, 0>; 1386 def C2_andn : T_LOGICAL_2OP<"and", 0b011, 1, 1>; 1387 def C2_orn : T_LOGICAL_2OP<"or", 0b111, 1, 1>; 1388 1389 def: Pat<(i1 (and I1:$Ps, I1:$Pt)), (C2_and I1:$Ps, I1:$Pt)>; 1390 def: Pat<(i1 (or I1:$Ps, I1:$Pt)), (C2_or I1:$Ps, I1:$Pt)>; 1391 def: Pat<(i1 (xor I1:$Ps, I1:$Pt)), (C2_xor I1:$Ps, I1:$Pt)>; 1392 def: Pat<(i1 (and I1:$Ps, (not I1:$Pt))), (C2_andn I1:$Ps, I1:$Pt)>; 1393 def: Pat<(i1 (or I1:$Ps, (not I1:$Pt))), (C2_orn I1:$Ps, I1:$Pt)>; 1394 1395 let hasSideEffects = 0, hasNewValue = 1 in 1396 def C2_vitpack : SInst<(outs IntRegs:$Rd), (ins PredRegs:$Ps, PredRegs:$Pt), 1397 "$Rd = vitpack($Ps, $Pt)", [], "", S_2op_tc_1_SLOT23> { 1398 bits<5> Rd; 1399 bits<2> Ps; 1400 bits<2> Pt; 1401 1402 let IClass = 0b1000; 1403 let Inst{27-24} = 0b1001; 1404 let Inst{22-21} = 0b00; 1405 let Inst{17-16} = Ps; 1406 let Inst{9-8} = Pt; 1407 let Inst{4-0} = Rd; 1408 } 1409 1410 let hasSideEffects = 0 in 1411 def C2_mask : SInst<(outs DoubleRegs:$Rd), (ins PredRegs:$Pt), 1412 "$Rd = mask($Pt)", [], "", S_2op_tc_1_SLOT23> { 1413 bits<5> Rd; 1414 bits<2> Pt; 1415 1416 let IClass = 0b1000; 1417 let Inst{27-24} = 0b0110; 1418 let Inst{9-8} = Pt; 1419 let Inst{4-0} = Rd; 1420 } 1421 1422 // User control register transfer. 1423 //===----------------------------------------------------------------------===// 1424 // CR - 1425 //===----------------------------------------------------------------------===// 1426 1427 //===----------------------------------------------------------------------===// 1428 // JR + 1429 //===----------------------------------------------------------------------===// 1430 1431 def retflag : SDNode<"HexagonISD::RET_FLAG", SDTNone, 1432 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 1433 def eh_return: SDNode<"HexagonISD::EH_RETURN", SDTNone, [SDNPHasChain]>; 1434 1435 class CondStr<string CReg, bit True, bit New> { 1436 string S = "if (" # !if(True,"","!") # CReg # !if(New,".new","") # ") "; 1437 } 1438 class JumpOpcStr<string Mnemonic, bit New, bit Taken> { 1439 string S = Mnemonic # !if(Taken, ":t", ":nt"); 1440 } 1441 1442 let isBranch = 1, isBarrier = 1, Defs = [PC], hasSideEffects = 0, 1443 isPredicable = 1, 1444 isExtendable = 1, opExtendable = 0, isExtentSigned = 1, 1445 opExtentBits = 24, opExtentAlign = 2, InputType = "imm" in 1446 class T_JMP<string ExtStr> 1447 : JInst<(outs), (ins brtarget:$dst), 1448 "jump " # ExtStr # "$dst", 1449 [], "", J_tc_2early_SLOT23> { 1450 bits<24> dst; 1451 let IClass = 0b0101; 1452 1453 let Inst{27-25} = 0b100; 1454 let Inst{24-16} = dst{23-15}; 1455 let Inst{13-1} = dst{14-2}; 1456 } 1457 1458 let isBranch = 1, Defs = [PC], hasSideEffects = 0, isPredicated = 1, 1459 isExtendable = 1, opExtendable = 1, isExtentSigned = 1, 1460 opExtentBits = 17, opExtentAlign = 2, InputType = "imm" in 1461 class T_JMP_c<bit PredNot, bit isPredNew, bit isTak, string ExtStr> 1462 : JInst<(outs), (ins PredRegs:$src, brtarget:$dst), 1463 CondStr<"$src", !if(PredNot,0,1), isPredNew>.S # 1464 JumpOpcStr<"jump", isPredNew, isTak>.S # " " # 1465 ExtStr # "$dst", 1466 [], "", J_tc_2early_SLOT23>, ImmRegRel { 1467 let isTaken = isTak; 1468 let isPredicatedFalse = PredNot; 1469 let isPredicatedNew = isPredNew; 1470 bits<2> src; 1471 bits<17> dst; 1472 1473 let IClass = 0b0101; 1474 1475 let Inst{27-24} = 0b1100; 1476 let Inst{21} = PredNot; 1477 let Inst{12} = isTak; 1478 let Inst{11} = isPredNew; 1479 let Inst{9-8} = src; 1480 let Inst{23-22} = dst{16-15}; 1481 let Inst{20-16} = dst{14-10}; 1482 let Inst{13} = dst{9}; 1483 let Inst{7-1} = dst{8-2}; 1484 } 1485 1486 multiclass JMP_Pred<bit PredNot, string ExtStr> { 1487 def NAME : T_JMP_c<PredNot, 0, 0, ExtStr>; // not taken 1488 // Predicate new 1489 def NAME#newpt : T_JMP_c<PredNot, 1, 1, ExtStr>; // taken 1490 def NAME#new : T_JMP_c<PredNot, 1, 0, ExtStr>; // not taken 1491 } 1492 1493 multiclass JMP_base<string BaseOp, string ExtStr> { 1494 let BaseOpcode = BaseOp in { 1495 def NAME : T_JMP<ExtStr>; 1496 defm t : JMP_Pred<0, ExtStr>; 1497 defm f : JMP_Pred<1, ExtStr>; 1498 } 1499 } 1500 1501 // Jumps to address stored in a register, JUMPR_MISC 1502 // if ([[!]P[.new]]) jumpr[:t/nt] Rs 1503 let isBranch = 1, isIndirectBranch = 1, isBarrier = 1, Defs = [PC], 1504 isPredicable = 1, hasSideEffects = 0, InputType = "reg" in 1505 class T_JMPr 1506 : JRInst<(outs), (ins IntRegs:$dst), 1507 "jumpr $dst", [], "", J_tc_2early_SLOT2> { 1508 bits<5> dst; 1509 1510 let IClass = 0b0101; 1511 let Inst{27-21} = 0b0010100; 1512 let Inst{20-16} = dst; 1513 } 1514 1515 let isBranch = 1, isIndirectBranch = 1, Defs = [PC], isPredicated = 1, 1516 hasSideEffects = 0, InputType = "reg" in 1517 class T_JMPr_c <bit PredNot, bit isPredNew, bit isTak> 1518 : JRInst <(outs), (ins PredRegs:$src, IntRegs:$dst), 1519 CondStr<"$src", !if(PredNot,0,1), isPredNew>.S # 1520 JumpOpcStr<"jumpr", isPredNew, isTak>.S # " $dst", [], 1521 "", J_tc_2early_SLOT2> { 1522 1523 let isTaken = isTak; 1524 let isPredicatedFalse = PredNot; 1525 let isPredicatedNew = isPredNew; 1526 bits<2> src; 1527 bits<5> dst; 1528 1529 let IClass = 0b0101; 1530 1531 let Inst{27-22} = 0b001101; 1532 let Inst{21} = PredNot; 1533 let Inst{20-16} = dst; 1534 let Inst{12} = isTak; 1535 let Inst{11} = isPredNew; 1536 let Inst{9-8} = src; 1537 } 1538 1539 multiclass JMPR_Pred<bit PredNot> { 1540 def NAME : T_JMPr_c<PredNot, 0, 0>; // not taken 1541 // Predicate new 1542 def NAME#newpt : T_JMPr_c<PredNot, 1, 1>; // taken 1543 def NAME#new : T_JMPr_c<PredNot, 1, 0>; // not taken 1544 } 1545 1546 multiclass JMPR_base<string BaseOp> { 1547 let BaseOpcode = BaseOp in { 1548 def NAME : T_JMPr; 1549 defm t : JMPR_Pred<0>; 1550 defm f : JMPR_Pred<1>; 1551 } 1552 } 1553 1554 let isCall = 1, hasSideEffects = 1 in 1555 class JUMPR_MISC_CALLR<bit isPred, bit isPredNot, 1556 dag InputDag = (ins IntRegs:$Rs)> 1557 : JRInst<(outs), InputDag, 1558 !if(isPred, !if(isPredNot, "if (!$Pu) callr $Rs", 1559 "if ($Pu) callr $Rs"), 1560 "callr $Rs"), 1561 [], "", J_tc_2early_SLOT2> { 1562 bits<5> Rs; 1563 bits<2> Pu; 1564 let isPredicated = isPred; 1565 let isPredicatedFalse = isPredNot; 1566 1567 let IClass = 0b0101; 1568 let Inst{27-25} = 0b000; 1569 let Inst{24-23} = !if (isPred, 0b10, 0b01); 1570 let Inst{22} = 0; 1571 let Inst{21} = isPredNot; 1572 let Inst{9-8} = !if (isPred, Pu, 0b00); 1573 let Inst{20-16} = Rs; 1574 1575 } 1576 1577 let Defs = VolatileV3.Regs in { 1578 def J2_callrt : JUMPR_MISC_CALLR<1, 0, (ins PredRegs:$Pu, IntRegs:$Rs)>; 1579 def J2_callrf : JUMPR_MISC_CALLR<1, 1, (ins PredRegs:$Pu, IntRegs:$Rs)>; 1580 } 1581 1582 let isTerminator = 1, hasSideEffects = 0 in { 1583 defm J2_jump : JMP_base<"JMP", "">, PredNewRel; 1584 1585 defm J2_jumpr : JMPR_base<"JMPr">, PredNewRel; 1586 1587 let isReturn = 1, isCodeGenOnly = 1 in 1588 defm JMPret : JMPR_base<"JMPret">, PredNewRel; 1589 } 1590 1591 let validSubTargets = HasV60SubT in 1592 multiclass JMPpt_base<string BaseOp> { 1593 let BaseOpcode = BaseOp in { 1594 def tpt : T_JMP_c <0, 0, 1, "">; // Predicate true - taken 1595 def fpt : T_JMP_c <1, 0, 1, "">; // Predicate false - taken 1596 } 1597 } 1598 1599 let validSubTargets = HasV60SubT in 1600 multiclass JMPRpt_base<string BaseOp> { 1601 let BaseOpcode = BaseOp in { 1602 def tpt : T_JMPr_c<0, 0, 1>; // predicate true - taken 1603 def fpt : T_JMPr_c<1, 0, 1>; // predicate false - taken 1604 } 1605 } 1606 1607 defm J2_jumpr : JMPRpt_base<"JMPr">; 1608 defm J2_jump : JMPpt_base<"JMP">; 1609 1610 def: Pat<(br bb:$dst), 1611 (J2_jump brtarget:$dst)>; 1612 def: Pat<(retflag), 1613 (JMPret (i32 R31))>; 1614 def: Pat<(brcond (i1 PredRegs:$src1), bb:$offset), 1615 (J2_jumpt PredRegs:$src1, bb:$offset)>; 1616 1617 // A return through builtin_eh_return. 1618 let isReturn = 1, isTerminator = 1, isBarrier = 1, hasSideEffects = 0, 1619 isCodeGenOnly = 1, Defs = [PC], Uses = [R28], isPredicable = 0 in 1620 def EH_RETURN_JMPR : T_JMPr; 1621 1622 def: Pat<(eh_return), 1623 (EH_RETURN_JMPR (i32 R31))>; 1624 def: Pat<(brind (i32 IntRegs:$dst)), 1625 (J2_jumpr IntRegs:$dst)>; 1626 1627 //===----------------------------------------------------------------------===// 1628 // JR - 1629 //===----------------------------------------------------------------------===// 1630 1631 //===----------------------------------------------------------------------===// 1632 // LD + 1633 //===----------------------------------------------------------------------===// 1634 1635 // Load - Base with Immediate offset addressing mode 1636 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, AddedComplexity = 20 in 1637 class T_load_io <string mnemonic, RegisterClass RC, bits<4> MajOp, 1638 Operand ImmOp> 1639 : LDInst<(outs RC:$dst), (ins IntRegs:$src1, ImmOp:$offset), 1640 "$dst = "#mnemonic#"($src1 + #$offset)", []>, AddrModeRel { 1641 bits<4> name; 1642 bits<5> dst; 1643 bits<5> src1; 1644 bits<14> offset; 1645 bits<11> offsetBits; 1646 1647 string ImmOpStr = !cast<string>(ImmOp); 1648 let offsetBits = !if (!eq(ImmOpStr, "s11_3Ext"), offset{13-3}, 1649 !if (!eq(ImmOpStr, "s11_2Ext"), offset{12-2}, 1650 !if (!eq(ImmOpStr, "s11_1Ext"), offset{11-1}, 1651 /* s11_0Ext */ offset{10-0}))); 1652 let opExtentBits = !if (!eq(ImmOpStr, "s11_3Ext"), 14, 1653 !if (!eq(ImmOpStr, "s11_2Ext"), 13, 1654 !if (!eq(ImmOpStr, "s11_1Ext"), 12, 1655 /* s11_0Ext */ 11))); 1656 let hasNewValue = !if (!eq(!cast<string>(RC), "DoubleRegs"), 0, 1); 1657 1658 let IClass = 0b1001; 1659 1660 let Inst{27} = 0b0; 1661 let Inst{26-25} = offsetBits{10-9}; 1662 let Inst{24-21} = MajOp; 1663 let Inst{20-16} = src1; 1664 let Inst{13-5} = offsetBits{8-0}; 1665 let Inst{4-0} = dst; 1666 } 1667 1668 let opExtendable = 3, isExtentSigned = 0, isPredicated = 1 in 1669 class T_pload_io <string mnemonic, RegisterClass RC, bits<4>MajOp, 1670 Operand ImmOp, bit isNot, bit isPredNew> 1671 : LDInst<(outs RC:$dst), 1672 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset), 1673 "if ("#!if(isNot, "!$src1", "$src1") 1674 #!if(isPredNew, ".new", "") 1675 #") $dst = "#mnemonic#"($src2 + #$offset)", 1676 [],"", V2LDST_tc_ld_SLOT01> , AddrModeRel { 1677 bits<5> dst; 1678 bits<2> src1; 1679 bits<5> src2; 1680 bits<9> offset; 1681 bits<6> offsetBits; 1682 string ImmOpStr = !cast<string>(ImmOp); 1683 1684 let offsetBits = !if (!eq(ImmOpStr, "u6_3Ext"), offset{8-3}, 1685 !if (!eq(ImmOpStr, "u6_2Ext"), offset{7-2}, 1686 !if (!eq(ImmOpStr, "u6_1Ext"), offset{6-1}, 1687 /* u6_0Ext */ offset{5-0}))); 1688 let opExtentBits = !if (!eq(ImmOpStr, "u6_3Ext"), 9, 1689 !if (!eq(ImmOpStr, "u6_2Ext"), 8, 1690 !if (!eq(ImmOpStr, "u6_1Ext"), 7, 1691 /* u6_0Ext */ 6))); 1692 let hasNewValue = !if (!eq(ImmOpStr, "u6_3Ext"), 0, 1); 1693 let isPredicatedNew = isPredNew; 1694 let isPredicatedFalse = isNot; 1695 1696 let IClass = 0b0100; 1697 1698 let Inst{27} = 0b0; 1699 let Inst{27} = 0b0; 1700 let Inst{26} = isNot; 1701 let Inst{25} = isPredNew; 1702 let Inst{24-21} = MajOp; 1703 let Inst{20-16} = src2; 1704 let Inst{13} = 0b0; 1705 let Inst{12-11} = src1; 1706 let Inst{10-5} = offsetBits; 1707 let Inst{4-0} = dst; 1708 } 1709 1710 let isExtendable = 1, hasSideEffects = 0, addrMode = BaseImmOffset in 1711 multiclass LD_Idxd<string mnemonic, string CextOp, RegisterClass RC, 1712 Operand ImmOp, Operand predImmOp, bits<4>MajOp> { 1713 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in { 1714 let isPredicable = 1 in 1715 def L2_#NAME#_io : T_load_io <mnemonic, RC, MajOp, ImmOp>; 1716 1717 // Predicated 1718 def L2_p#NAME#t_io : T_pload_io <mnemonic, RC, MajOp, predImmOp, 0, 0>; 1719 def L2_p#NAME#f_io : T_pload_io <mnemonic, RC, MajOp, predImmOp, 1, 0>; 1720 1721 // Predicated new 1722 def L2_p#NAME#tnew_io : T_pload_io <mnemonic, RC, MajOp, predImmOp, 0, 1>; 1723 def L2_p#NAME#fnew_io : T_pload_io <mnemonic, RC, MajOp, predImmOp, 1, 1>; 1724 } 1725 } 1726 1727 let accessSize = ByteAccess in { 1728 defm loadrb: LD_Idxd <"memb", "LDrib", IntRegs, s11_0Ext, u6_0Ext, 0b1000>; 1729 defm loadrub: LD_Idxd <"memub", "LDriub", IntRegs, s11_0Ext, u6_0Ext, 0b1001>; 1730 } 1731 1732 let accessSize = HalfWordAccess, opExtentAlign = 1 in { 1733 defm loadrh: LD_Idxd <"memh", "LDrih", IntRegs, s11_1Ext, u6_1Ext, 0b1010>; 1734 defm loadruh: LD_Idxd <"memuh", "LDriuh", IntRegs, s11_1Ext, u6_1Ext, 0b1011>; 1735 } 1736 1737 let accessSize = WordAccess, opExtentAlign = 2 in 1738 defm loadri: LD_Idxd <"memw", "LDriw", IntRegs, s11_2Ext, u6_2Ext, 0b1100>; 1739 1740 let accessSize = DoubleWordAccess, opExtentAlign = 3 in 1741 defm loadrd: LD_Idxd <"memd", "LDrid", DoubleRegs, s11_3Ext, u6_3Ext, 0b1110>; 1742 1743 let accessSize = HalfWordAccess, opExtentAlign = 1 in { 1744 def L2_loadbsw2_io: T_load_io<"membh", IntRegs, 0b0001, s11_1Ext>; 1745 def L2_loadbzw2_io: T_load_io<"memubh", IntRegs, 0b0011, s11_1Ext>; 1746 } 1747 1748 let accessSize = WordAccess, opExtentAlign = 2 in { 1749 def L2_loadbzw4_io: T_load_io<"memubh", DoubleRegs, 0b0101, s11_2Ext>; 1750 def L2_loadbsw4_io: T_load_io<"membh", DoubleRegs, 0b0111, s11_2Ext>; 1751 } 1752 1753 let addrMode = BaseImmOffset, isExtendable = 1, hasSideEffects = 0, 1754 opExtendable = 3, isExtentSigned = 1 in 1755 class T_loadalign_io <string str, bits<4> MajOp, Operand ImmOp> 1756 : LDInst<(outs DoubleRegs:$dst), 1757 (ins DoubleRegs:$src1, IntRegs:$src2, ImmOp:$offset), 1758 "$dst = "#str#"($src2 + #$offset)", [], 1759 "$src1 = $dst">, AddrModeRel { 1760 bits<4> name; 1761 bits<5> dst; 1762 bits<5> src2; 1763 bits<12> offset; 1764 bits<11> offsetBits; 1765 1766 let offsetBits = !if (!eq(!cast<string>(ImmOp), "s11_1Ext"), offset{11-1}, 1767 /* s11_0Ext */ offset{10-0}); 1768 let IClass = 0b1001; 1769 1770 let Inst{27} = 0b0; 1771 let Inst{26-25} = offsetBits{10-9}; 1772 let Inst{24-21} = MajOp; 1773 let Inst{20-16} = src2; 1774 let Inst{13-5} = offsetBits{8-0}; 1775 let Inst{4-0} = dst; 1776 } 1777 1778 let accessSize = HalfWordAccess, opExtentBits = 12, opExtentAlign = 1 in 1779 def L2_loadalignh_io: T_loadalign_io <"memh_fifo", 0b0010, s11_1Ext>; 1780 1781 let accessSize = ByteAccess, opExtentBits = 11 in 1782 def L2_loadalignb_io: T_loadalign_io <"memb_fifo", 0b0100, s11_0Ext>; 1783 1784 // Patterns to select load-indexed (i.e. load from base+offset). 1785 multiclass Loadx_pat<PatFrag Load, ValueType VT, PatLeaf ImmPred, 1786 InstHexagon MI> { 1787 def: Pat<(VT (Load AddrFI:$fi)), (VT (MI AddrFI:$fi, 0))>; 1788 def: Pat<(VT (Load (add (i32 AddrFI:$fi), ImmPred:$Off))), 1789 (VT (MI AddrFI:$fi, imm:$Off))>; 1790 def: Pat<(VT (Load (add (i32 IntRegs:$Rs), ImmPred:$Off))), 1791 (VT (MI IntRegs:$Rs, imm:$Off))>; 1792 def: Pat<(VT (Load (i32 IntRegs:$Rs))), (VT (MI IntRegs:$Rs, 0))>; 1793 } 1794 1795 let AddedComplexity = 20 in { 1796 defm: Loadx_pat<load, i32, s30_2ImmPred, L2_loadri_io>; 1797 defm: Loadx_pat<load, i64, s29_3ImmPred, L2_loadrd_io>; 1798 defm: Loadx_pat<atomic_load_8 , i32, s32_0ImmPred, L2_loadrub_io>; 1799 defm: Loadx_pat<atomic_load_16, i32, s31_1ImmPred, L2_loadruh_io>; 1800 defm: Loadx_pat<atomic_load_32, i32, s30_2ImmPred, L2_loadri_io>; 1801 defm: Loadx_pat<atomic_load_64, i64, s29_3ImmPred, L2_loadrd_io>; 1802 1803 defm: Loadx_pat<extloadi1, i32, s32_0ImmPred, L2_loadrub_io>; 1804 defm: Loadx_pat<extloadi8, i32, s32_0ImmPred, L2_loadrub_io>; 1805 defm: Loadx_pat<extloadi16, i32, s31_1ImmPred, L2_loadruh_io>; 1806 defm: Loadx_pat<sextloadi8, i32, s32_0ImmPred, L2_loadrb_io>; 1807 defm: Loadx_pat<sextloadi16, i32, s31_1ImmPred, L2_loadrh_io>; 1808 defm: Loadx_pat<zextloadi1, i32, s32_0ImmPred, L2_loadrub_io>; 1809 defm: Loadx_pat<zextloadi8, i32, s32_0ImmPred, L2_loadrub_io>; 1810 defm: Loadx_pat<zextloadi16, i32, s31_1ImmPred, L2_loadruh_io>; 1811 // No sextloadi1. 1812 } 1813 1814 // Sign-extending loads of i1 need to replicate the lowest bit throughout 1815 // the 32-bit value. Since the loaded value can only be 0 or 1, 0-v should 1816 // do the trick. 1817 let AddedComplexity = 20 in 1818 def: Pat<(i32 (sextloadi1 (i32 IntRegs:$Rs))), 1819 (A2_subri 0, (L2_loadrub_io IntRegs:$Rs, 0))>; 1820 1821 //===----------------------------------------------------------------------===// 1822 // Post increment load 1823 //===----------------------------------------------------------------------===// 1824 //===----------------------------------------------------------------------===// 1825 // Template class for non-predicated post increment loads with immediate offset. 1826 //===----------------------------------------------------------------------===// 1827 let hasSideEffects = 0, addrMode = PostInc in 1828 class T_load_pi <string mnemonic, RegisterClass RC, Operand ImmOp, 1829 bits<4> MajOp > 1830 : LDInstPI <(outs RC:$dst, IntRegs:$dst2), 1831 (ins IntRegs:$src1, ImmOp:$offset), 1832 "$dst = "#mnemonic#"($src1++#$offset)" , 1833 [], 1834 "$src1 = $dst2" > , 1835 PredNewRel { 1836 bits<5> dst; 1837 bits<5> src1; 1838 bits<7> offset; 1839 bits<4> offsetBits; 1840 1841 string ImmOpStr = !cast<string>(ImmOp); 1842 let offsetBits = !if (!eq(ImmOpStr, "s4_3Imm"), offset{6-3}, 1843 !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2}, 1844 !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1}, 1845 /* s4_0Imm */ offset{3-0}))); 1846 let hasNewValue = !if (!eq(ImmOpStr, "s4_3Imm"), 0, 1); 1847 1848 let IClass = 0b1001; 1849 1850 let Inst{27-25} = 0b101; 1851 let Inst{24-21} = MajOp; 1852 let Inst{20-16} = src1; 1853 let Inst{13-12} = 0b00; 1854 let Inst{8-5} = offsetBits; 1855 let Inst{4-0} = dst; 1856 } 1857 1858 //===----------------------------------------------------------------------===// 1859 // Template class for predicated post increment loads with immediate offset. 1860 //===----------------------------------------------------------------------===// 1861 let isPredicated = 1, hasSideEffects = 0, addrMode = PostInc in 1862 class T_pload_pi <string mnemonic, RegisterClass RC, Operand ImmOp, 1863 bits<4> MajOp, bit isPredNot, bit isPredNew > 1864 : LDInst <(outs RC:$dst, IntRegs:$dst2), 1865 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset), 1866 !if(isPredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ", 1867 ") ")#"$dst = "#mnemonic#"($src2++#$offset)", 1868 [] , 1869 "$src2 = $dst2" > , 1870 PredNewRel { 1871 bits<5> dst; 1872 bits<2> src1; 1873 bits<5> src2; 1874 bits<7> offset; 1875 bits<4> offsetBits; 1876 1877 let isPredicatedNew = isPredNew; 1878 let isPredicatedFalse = isPredNot; 1879 1880 string ImmOpStr = !cast<string>(ImmOp); 1881 let offsetBits = !if (!eq(ImmOpStr, "s4_3Imm"), offset{6-3}, 1882 !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2}, 1883 !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1}, 1884 /* s4_0Imm */ offset{3-0}))); 1885 let hasNewValue = !if (!eq(ImmOpStr, "s4_3Imm"), 0, 1); 1886 1887 let IClass = 0b1001; 1888 1889 let Inst{27-25} = 0b101; 1890 let Inst{24-21} = MajOp; 1891 let Inst{20-16} = src2; 1892 let Inst{13} = 0b1; 1893 let Inst{12} = isPredNew; 1894 let Inst{11} = isPredNot; 1895 let Inst{10-9} = src1; 1896 let Inst{8-5} = offsetBits; 1897 let Inst{4-0} = dst; 1898 } 1899 1900 //===----------------------------------------------------------------------===// 1901 // Multiclass for post increment loads with immediate offset. 1902 //===----------------------------------------------------------------------===// 1903 1904 multiclass LD_PostInc <string mnemonic, string BaseOp, RegisterClass RC, 1905 Operand ImmOp, bits<4> MajOp> { 1906 let BaseOpcode = "POST_"#BaseOp in { 1907 let isPredicable = 1 in 1908 def L2_#NAME#_pi : T_load_pi < mnemonic, RC, ImmOp, MajOp>; 1909 1910 // Predicated 1911 def L2_p#NAME#t_pi : T_pload_pi < mnemonic, RC, ImmOp, MajOp, 0, 0>; 1912 def L2_p#NAME#f_pi : T_pload_pi < mnemonic, RC, ImmOp, MajOp, 1, 0>; 1913 1914 // Predicated new 1915 def L2_p#NAME#tnew_pi : T_pload_pi < mnemonic, RC, ImmOp, MajOp, 0, 1>; 1916 def L2_p#NAME#fnew_pi : T_pload_pi < mnemonic, RC, ImmOp, MajOp, 1, 1>; 1917 } 1918 } 1919 1920 // post increment byte loads with immediate offset 1921 let accessSize = ByteAccess in { 1922 defm loadrb : LD_PostInc <"memb", "LDrib", IntRegs, s4_0Imm, 0b1000>; 1923 defm loadrub : LD_PostInc <"memub", "LDriub", IntRegs, s4_0Imm, 0b1001>; 1924 } 1925 1926 // post increment halfword loads with immediate offset 1927 let accessSize = HalfWordAccess, opExtentAlign = 1 in { 1928 defm loadrh : LD_PostInc <"memh", "LDrih", IntRegs, s4_1Imm, 0b1010>; 1929 defm loadruh : LD_PostInc <"memuh", "LDriuh", IntRegs, s4_1Imm, 0b1011>; 1930 } 1931 1932 // post increment word loads with immediate offset 1933 let accessSize = WordAccess, opExtentAlign = 2 in 1934 defm loadri : LD_PostInc <"memw", "LDriw", IntRegs, s4_2Imm, 0b1100>; 1935 1936 // post increment doubleword loads with immediate offset 1937 let accessSize = DoubleWordAccess, opExtentAlign = 3 in 1938 defm loadrd : LD_PostInc <"memd", "LDrid", DoubleRegs, s4_3Imm, 0b1110>; 1939 1940 // Rd=memb[u]h(Rx++#s4:1) 1941 // Rdd=memb[u]h(Rx++#s4:2) 1942 let accessSize = HalfWordAccess, opExtentAlign = 1 in { 1943 def L2_loadbsw2_pi : T_load_pi <"membh", IntRegs, s4_1Imm, 0b0001>; 1944 def L2_loadbzw2_pi : T_load_pi <"memubh", IntRegs, s4_1Imm, 0b0011>; 1945 } 1946 let accessSize = WordAccess, opExtentAlign = 2, hasNewValue = 0 in { 1947 def L2_loadbsw4_pi : T_load_pi <"membh", DoubleRegs, s4_2Imm, 0b0111>; 1948 def L2_loadbzw4_pi : T_load_pi <"memubh", DoubleRegs, s4_2Imm, 0b0101>; 1949 } 1950 1951 //===----------------------------------------------------------------------===// 1952 // Template class for post increment fifo loads with immediate offset. 1953 //===----------------------------------------------------------------------===// 1954 let hasSideEffects = 0, addrMode = PostInc in 1955 class T_loadalign_pi <string mnemonic, Operand ImmOp, bits<4> MajOp > 1956 : LDInstPI <(outs DoubleRegs:$dst, IntRegs:$dst2), 1957 (ins DoubleRegs:$src1, IntRegs:$src2, ImmOp:$offset), 1958 "$dst = "#mnemonic#"($src2++#$offset)" , 1959 [], "$src2 = $dst2, $src1 = $dst" > , 1960 PredNewRel { 1961 bits<5> dst; 1962 bits<5> src2; 1963 bits<5> offset; 1964 bits<4> offsetBits; 1965 1966 let offsetBits = !if (!eq(!cast<string>(ImmOp), "s4_1Imm"), offset{4-1}, 1967 /* s4_0Imm */ offset{3-0}); 1968 let IClass = 0b1001; 1969 1970 let Inst{27-25} = 0b101; 1971 let Inst{24-21} = MajOp; 1972 let Inst{20-16} = src2; 1973 let Inst{13-12} = 0b00; 1974 let Inst{8-5} = offsetBits; 1975 let Inst{4-0} = dst; 1976 } 1977 1978 // Ryy=memh_fifo(Rx++#s4:1) 1979 // Ryy=memb_fifo(Rx++#s4:0) 1980 let accessSize = ByteAccess in 1981 def L2_loadalignb_pi : T_loadalign_pi <"memb_fifo", s4_0Imm, 0b0100>; 1982 1983 let accessSize = HalfWordAccess, opExtentAlign = 1 in 1984 def L2_loadalignh_pi : T_loadalign_pi <"memh_fifo", s4_1Imm, 0b0010>; 1985 1986 //===----------------------------------------------------------------------===// 1987 // Template class for post increment loads with register offset. 1988 //===----------------------------------------------------------------------===// 1989 let hasSideEffects = 0, addrMode = PostInc in 1990 class T_load_pr <string mnemonic, RegisterClass RC, bits<4> MajOp, 1991 MemAccessSize AccessSz> 1992 : LDInstPI <(outs RC:$dst, IntRegs:$_dst_), 1993 (ins IntRegs:$src1, ModRegs:$src2), 1994 "$dst = "#mnemonic#"($src1++$src2)" , 1995 [], "$src1 = $_dst_" > { 1996 bits<5> dst; 1997 bits<5> src1; 1998 bits<1> src2; 1999 2000 let accessSize = AccessSz; 2001 let IClass = 0b1001; 2002 2003 let Inst{27-25} = 0b110; 2004 let Inst{24-21} = MajOp; 2005 let Inst{20-16} = src1; 2006 let Inst{13} = src2; 2007 let Inst{12} = 0b0; 2008 let Inst{7} = 0b0; 2009 let Inst{4-0} = dst; 2010 } 2011 2012 let hasNewValue = 1 in { 2013 def L2_loadrb_pr : T_load_pr <"memb", IntRegs, 0b1000, ByteAccess>; 2014 def L2_loadrub_pr : T_load_pr <"memub", IntRegs, 0b1001, ByteAccess>; 2015 def L2_loadrh_pr : T_load_pr <"memh", IntRegs, 0b1010, HalfWordAccess>; 2016 def L2_loadruh_pr : T_load_pr <"memuh", IntRegs, 0b1011, HalfWordAccess>; 2017 def L2_loadri_pr : T_load_pr <"memw", IntRegs, 0b1100, WordAccess>; 2018 2019 def L2_loadbzw2_pr : T_load_pr <"memubh", IntRegs, 0b0011, HalfWordAccess>; 2020 } 2021 2022 def L2_loadrd_pr : T_load_pr <"memd", DoubleRegs, 0b1110, DoubleWordAccess>; 2023 def L2_loadbzw4_pr : T_load_pr <"memubh", DoubleRegs, 0b0101, WordAccess>; 2024 2025 // Load predicate. 2026 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 13, 2027 isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in 2028 def LDriw_pred : LDInst<(outs PredRegs:$dst), 2029 (ins IntRegs:$addr, s11_2Ext:$off), 2030 ".error \"should not emit\"", []>; 2031 // Load modifier. 2032 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 13, 2033 isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in 2034 def LDriw_mod : LDInst<(outs ModRegs:$dst), 2035 (ins IntRegs:$addr, s11_2Ext:$off), 2036 ".error \"should not emit\"", []>; 2037 2038 let Defs = [R29, R30, R31], Uses = [R30], hasSideEffects = 0 in 2039 def L2_deallocframe : LDInst<(outs), (ins), 2040 "deallocframe", 2041 []> { 2042 let IClass = 0b1001; 2043 2044 let Inst{27-16} = 0b000000011110; 2045 let Inst{13} = 0b0; 2046 let Inst{4-0} = 0b11110; 2047 } 2048 2049 // Load / Post increment circular addressing mode. 2050 let Uses = [CS], hasSideEffects = 0 in 2051 class T_load_pcr<string mnemonic, RegisterClass RC, bits<4> MajOp> 2052 : LDInst <(outs RC:$dst, IntRegs:$_dst_), 2053 (ins IntRegs:$Rz, ModRegs:$Mu), 2054 "$dst = "#mnemonic#"($Rz ++ I:circ($Mu))", [], 2055 "$Rz = $_dst_" > { 2056 bits<5> dst; 2057 bits<5> Rz; 2058 bit Mu; 2059 2060 let hasNewValue = !if (!eq(!cast<string>(RC), "DoubleRegs"), 0, 1); 2061 let IClass = 0b1001; 2062 2063 let Inst{27-25} = 0b100; 2064 let Inst{24-21} = MajOp; 2065 let Inst{20-16} = Rz; 2066 let Inst{13} = Mu; 2067 let Inst{12} = 0b0; 2068 let Inst{9} = 0b1; 2069 let Inst{7} = 0b0; 2070 let Inst{4-0} = dst; 2071 } 2072 2073 let accessSize = ByteAccess in { 2074 def L2_loadrb_pcr : T_load_pcr <"memb", IntRegs, 0b1000>; 2075 def L2_loadrub_pcr : T_load_pcr <"memub", IntRegs, 0b1001>; 2076 } 2077 2078 let accessSize = HalfWordAccess in { 2079 def L2_loadrh_pcr : T_load_pcr <"memh", IntRegs, 0b1010>; 2080 def L2_loadruh_pcr : T_load_pcr <"memuh", IntRegs, 0b1011>; 2081 def L2_loadbsw2_pcr : T_load_pcr <"membh", IntRegs, 0b0001>; 2082 def L2_loadbzw2_pcr : T_load_pcr <"memubh", IntRegs, 0b0011>; 2083 } 2084 2085 let accessSize = WordAccess in { 2086 def L2_loadri_pcr : T_load_pcr <"memw", IntRegs, 0b1100>; 2087 let hasNewValue = 0 in { 2088 def L2_loadbzw4_pcr : T_load_pcr <"memubh", DoubleRegs, 0b0101>; 2089 def L2_loadbsw4_pcr : T_load_pcr <"membh", DoubleRegs, 0b0111>; 2090 } 2091 } 2092 2093 let accessSize = DoubleWordAccess in 2094 def L2_loadrd_pcr : T_load_pcr <"memd", DoubleRegs, 0b1110>; 2095 2096 // Load / Post increment circular addressing mode. 2097 let Uses = [CS], hasSideEffects = 0 in 2098 class T_loadalign_pcr<string mnemonic, bits<4> MajOp, MemAccessSize AccessSz > 2099 : LDInst <(outs DoubleRegs:$dst, IntRegs:$_dst_), 2100 (ins DoubleRegs:$_src_, IntRegs:$Rz, ModRegs:$Mu), 2101 "$dst = "#mnemonic#"($Rz ++ I:circ($Mu))", [], 2102 "$Rz = $_dst_, $dst = $_src_" > { 2103 bits<5> dst; 2104 bits<5> Rz; 2105 bit Mu; 2106 2107 let accessSize = AccessSz; 2108 let IClass = 0b1001; 2109 2110 let Inst{27-25} = 0b100; 2111 let Inst{24-21} = MajOp; 2112 let Inst{20-16} = Rz; 2113 let Inst{13} = Mu; 2114 let Inst{12} = 0b0; 2115 let Inst{9} = 0b1; 2116 let Inst{7} = 0b0; 2117 let Inst{4-0} = dst; 2118 } 2119 2120 def L2_loadalignb_pcr : T_loadalign_pcr <"memb_fifo", 0b0100, ByteAccess>; 2121 def L2_loadalignh_pcr : T_loadalign_pcr <"memh_fifo", 0b0010, HalfWordAccess>; 2122 2123 //===----------------------------------------------------------------------===// 2124 // Circular loads with immediate offset. 2125 //===----------------------------------------------------------------------===// 2126 let Uses = [CS], mayLoad = 1, hasSideEffects = 0 in 2127 class T_load_pci <string mnemonic, RegisterClass RC, 2128 Operand ImmOp, bits<4> MajOp> 2129 : LDInstPI<(outs RC:$dst, IntRegs:$_dst_), 2130 (ins IntRegs:$Rz, ImmOp:$offset, ModRegs:$Mu), 2131 "$dst = "#mnemonic#"($Rz ++ #$offset:circ($Mu))", [], 2132 "$Rz = $_dst_"> { 2133 bits<5> dst; 2134 bits<5> Rz; 2135 bits<1> Mu; 2136 bits<7> offset; 2137 bits<4> offsetBits; 2138 2139 string ImmOpStr = !cast<string>(ImmOp); 2140 let hasNewValue = !if (!eq(!cast<string>(RC), "DoubleRegs"), 0, 1); 2141 let offsetBits = !if (!eq(ImmOpStr, "s4_3Imm"), offset{6-3}, 2142 !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2}, 2143 !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1}, 2144 /* s4_0Imm */ offset{3-0}))); 2145 let IClass = 0b1001; 2146 let Inst{27-25} = 0b100; 2147 let Inst{24-21} = MajOp; 2148 let Inst{20-16} = Rz; 2149 let Inst{13} = Mu; 2150 let Inst{12} = 0b0; 2151 let Inst{9} = 0b0; 2152 let Inst{8-5} = offsetBits; 2153 let Inst{4-0} = dst; 2154 } 2155 2156 // Byte variants of circ load 2157 let accessSize = ByteAccess in { 2158 def L2_loadrb_pci : T_load_pci <"memb", IntRegs, s4_0Imm, 0b1000>; 2159 def L2_loadrub_pci : T_load_pci <"memub", IntRegs, s4_0Imm, 0b1001>; 2160 } 2161 2162 // Half word variants of circ load 2163 let accessSize = HalfWordAccess in { 2164 def L2_loadrh_pci : T_load_pci <"memh", IntRegs, s4_1Imm, 0b1010>; 2165 def L2_loadruh_pci : T_load_pci <"memuh", IntRegs, s4_1Imm, 0b1011>; 2166 def L2_loadbzw2_pci : T_load_pci <"memubh", IntRegs, s4_1Imm, 0b0011>; 2167 def L2_loadbsw2_pci : T_load_pci <"membh", IntRegs, s4_1Imm, 0b0001>; 2168 } 2169 2170 // Word variants of circ load 2171 let accessSize = WordAccess in 2172 def L2_loadri_pci : T_load_pci <"memw", IntRegs, s4_2Imm, 0b1100>; 2173 2174 let accessSize = WordAccess, hasNewValue = 0 in { 2175 def L2_loadbzw4_pci : T_load_pci <"memubh", DoubleRegs, s4_2Imm, 0b0101>; 2176 def L2_loadbsw4_pci : T_load_pci <"membh", DoubleRegs, s4_2Imm, 0b0111>; 2177 } 2178 2179 let accessSize = DoubleWordAccess, hasNewValue = 0 in 2180 def L2_loadrd_pci : T_load_pci <"memd", DoubleRegs, s4_3Imm, 0b1110>; 2181 2182 2183 // TODO: memb_fifo and memh_fifo must take destination register as input. 2184 // One-off circ loads - not enough in common to break into a class. 2185 let accessSize = ByteAccess in 2186 def L2_loadalignb_pci : T_load_pci <"memb_fifo", DoubleRegs, s4_0Imm, 0b0100>; 2187 2188 let accessSize = HalfWordAccess, opExtentAlign = 1 in 2189 def L2_loadalignh_pci : T_load_pci <"memh_fifo", DoubleRegs, s4_1Imm, 0b0010>; 2190 2191 // L[24]_load[wd]_locked: Load word/double with lock. 2192 let isSoloAX = 1 in 2193 class T_load_locked <string mnemonic, RegisterClass RC> 2194 : LD0Inst <(outs RC:$dst), 2195 (ins IntRegs:$src), 2196 "$dst = "#mnemonic#"($src)"> { 2197 bits<5> dst; 2198 bits<5> src; 2199 let IClass = 0b1001; 2200 let Inst{27-21} = 0b0010000; 2201 let Inst{20-16} = src; 2202 let Inst{13-12} = !if (!eq(mnemonic, "memd_locked"), 0b01, 0b00); 2203 let Inst{5} = 0; 2204 let Inst{4-0} = dst; 2205 } 2206 let hasNewValue = 1, accessSize = WordAccess, opNewValue = 0 in 2207 def L2_loadw_locked : T_load_locked <"memw_locked", IntRegs>; 2208 let accessSize = DoubleWordAccess in 2209 def L4_loadd_locked : T_load_locked <"memd_locked", DoubleRegs>; 2210 2211 // S[24]_store[wd]_locked: Store word/double conditionally. 2212 let isSoloAX = 1, isPredicateLate = 1 in 2213 class T_store_locked <string mnemonic, RegisterClass RC> 2214 : ST0Inst <(outs PredRegs:$Pd), (ins IntRegs:$Rs, RC:$Rt), 2215 mnemonic#"($Rs, $Pd) = $Rt"> { 2216 bits<2> Pd; 2217 bits<5> Rs; 2218 bits<5> Rt; 2219 2220 let IClass = 0b1010; 2221 let Inst{27-23} = 0b00001; 2222 let Inst{22} = !if (!eq(mnemonic, "memw_locked"), 0b0, 0b1); 2223 let Inst{21} = 0b1; 2224 let Inst{20-16} = Rs; 2225 let Inst{12-8} = Rt; 2226 let Inst{1-0} = Pd; 2227 } 2228 2229 let accessSize = WordAccess in 2230 def S2_storew_locked : T_store_locked <"memw_locked", IntRegs>; 2231 2232 let accessSize = DoubleWordAccess in 2233 def S4_stored_locked : T_store_locked <"memd_locked", DoubleRegs>; 2234 2235 //===----------------------------------------------------------------------===// 2236 // Bit-reversed loads with auto-increment register 2237 //===----------------------------------------------------------------------===// 2238 let hasSideEffects = 0 in 2239 class T_load_pbr<string mnemonic, RegisterClass RC, 2240 MemAccessSize addrSize, bits<4> majOp> 2241 : LDInst 2242 <(outs RC:$dst, IntRegs:$_dst_), 2243 (ins IntRegs:$Rz, ModRegs:$Mu), 2244 "$dst = "#mnemonic#"($Rz ++ $Mu:brev)" , 2245 [] , "$Rz = $_dst_" > { 2246 2247 let accessSize = addrSize; 2248 2249 bits<5> dst; 2250 bits<5> Rz; 2251 bits<1> Mu; 2252 2253 let IClass = 0b1001; 2254 2255 let Inst{27-25} = 0b111; 2256 let Inst{24-21} = majOp; 2257 let Inst{20-16} = Rz; 2258 let Inst{13} = Mu; 2259 let Inst{12} = 0b0; 2260 let Inst{7} = 0b0; 2261 let Inst{4-0} = dst; 2262 } 2263 2264 let hasNewValue =1, opNewValue = 0 in { 2265 def L2_loadrb_pbr : T_load_pbr <"memb", IntRegs, ByteAccess, 0b1000>; 2266 def L2_loadrub_pbr : T_load_pbr <"memub", IntRegs, ByteAccess, 0b1001>; 2267 def L2_loadrh_pbr : T_load_pbr <"memh", IntRegs, HalfWordAccess, 0b1010>; 2268 def L2_loadruh_pbr : T_load_pbr <"memuh", IntRegs, HalfWordAccess, 0b1011>; 2269 def L2_loadbsw2_pbr : T_load_pbr <"membh", IntRegs, HalfWordAccess, 0b0001>; 2270 def L2_loadbzw2_pbr : T_load_pbr <"memubh", IntRegs, HalfWordAccess, 0b0011>; 2271 def L2_loadri_pbr : T_load_pbr <"memw", IntRegs, WordAccess, 0b1100>; 2272 } 2273 2274 def L2_loadbzw4_pbr : T_load_pbr <"memubh", DoubleRegs, WordAccess, 0b0101>; 2275 def L2_loadbsw4_pbr : T_load_pbr <"membh", DoubleRegs, WordAccess, 0b0111>; 2276 def L2_loadrd_pbr : T_load_pbr <"memd", DoubleRegs, DoubleWordAccess, 0b1110>; 2277 2278 def L2_loadalignb_pbr :T_load_pbr <"memb_fifo", DoubleRegs, ByteAccess, 0b0100>; 2279 def L2_loadalignh_pbr :T_load_pbr <"memh_fifo", DoubleRegs, 2280 HalfWordAccess, 0b0010>; 2281 2282 //===----------------------------------------------------------------------===// 2283 // LD - 2284 //===----------------------------------------------------------------------===// 2285 2286 //===----------------------------------------------------------------------===// 2287 // MTYPE/ALU + 2288 //===----------------------------------------------------------------------===// 2289 //===----------------------------------------------------------------------===// 2290 // MTYPE/ALU - 2291 //===----------------------------------------------------------------------===// 2292 2293 //===----------------------------------------------------------------------===// 2294 // MTYPE/COMPLEX + 2295 //===----------------------------------------------------------------------===// 2296 //===----------------------------------------------------------------------===// 2297 // MTYPE/COMPLEX - 2298 //===----------------------------------------------------------------------===// 2299 2300 //===----------------------------------------------------------------------===// 2301 // MTYPE/MPYH + 2302 //===----------------------------------------------------------------------===// 2303 2304 //===----------------------------------------------------------------------===// 2305 // Template Class 2306 // MPYS / Multipy signed/unsigned halfwords 2307 //Rd=mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:rnd][:sat] 2308 //===----------------------------------------------------------------------===// 2309 2310 let hasNewValue = 1, opNewValue = 0 in 2311 class T_M2_mpy < bits<2> LHbits, bit isSat, bit isRnd, 2312 bit hasShift, bit isUnsigned> 2313 : MInst < (outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt), 2314 "$Rd = "#!if(isUnsigned,"mpyu","mpy")#"($Rs."#!if(LHbits{1},"h","l") 2315 #", $Rt."#!if(LHbits{0},"h)","l)") 2316 #!if(hasShift,":<<1","") 2317 #!if(isRnd,":rnd","") 2318 #!if(isSat,":sat",""), 2319 [], "", M_tc_3x_SLOT23 > { 2320 bits<5> Rd; 2321 bits<5> Rs; 2322 bits<5> Rt; 2323 2324 let IClass = 0b1110; 2325 2326 let Inst{27-24} = 0b1100; 2327 let Inst{23} = hasShift; 2328 let Inst{22} = isUnsigned; 2329 let Inst{21} = isRnd; 2330 let Inst{7} = isSat; 2331 let Inst{6-5} = LHbits; 2332 let Inst{4-0} = Rd; 2333 let Inst{20-16} = Rs; 2334 let Inst{12-8} = Rt; 2335 } 2336 2337 //Rd=mpy(Rs.[H|L],Rt.[H|L])[:<<1] 2338 def M2_mpy_ll_s1: T_M2_mpy<0b00, 0, 0, 1, 0>; 2339 def M2_mpy_ll_s0: T_M2_mpy<0b00, 0, 0, 0, 0>; 2340 def M2_mpy_lh_s1: T_M2_mpy<0b01, 0, 0, 1, 0>; 2341 def M2_mpy_lh_s0: T_M2_mpy<0b01, 0, 0, 0, 0>; 2342 def M2_mpy_hl_s1: T_M2_mpy<0b10, 0, 0, 1, 0>; 2343 def M2_mpy_hl_s0: T_M2_mpy<0b10, 0, 0, 0, 0>; 2344 def M2_mpy_hh_s1: T_M2_mpy<0b11, 0, 0, 1, 0>; 2345 def M2_mpy_hh_s0: T_M2_mpy<0b11, 0, 0, 0, 0>; 2346 2347 //Rd=mpyu(Rs.[H|L],Rt.[H|L])[:<<1] 2348 def M2_mpyu_ll_s1: T_M2_mpy<0b00, 0, 0, 1, 1>; 2349 def M2_mpyu_ll_s0: T_M2_mpy<0b00, 0, 0, 0, 1>; 2350 def M2_mpyu_lh_s1: T_M2_mpy<0b01, 0, 0, 1, 1>; 2351 def M2_mpyu_lh_s0: T_M2_mpy<0b01, 0, 0, 0, 1>; 2352 def M2_mpyu_hl_s1: T_M2_mpy<0b10, 0, 0, 1, 1>; 2353 def M2_mpyu_hl_s0: T_M2_mpy<0b10, 0, 0, 0, 1>; 2354 def M2_mpyu_hh_s1: T_M2_mpy<0b11, 0, 0, 1, 1>; 2355 def M2_mpyu_hh_s0: T_M2_mpy<0b11, 0, 0, 0, 1>; 2356 2357 //Rd=mpy(Rs.[H|L],Rt.[H|L])[:<<1]:rnd 2358 def M2_mpy_rnd_ll_s1: T_M2_mpy <0b00, 0, 1, 1, 0>; 2359 def M2_mpy_rnd_ll_s0: T_M2_mpy <0b00, 0, 1, 0, 0>; 2360 def M2_mpy_rnd_lh_s1: T_M2_mpy <0b01, 0, 1, 1, 0>; 2361 def M2_mpy_rnd_lh_s0: T_M2_mpy <0b01, 0, 1, 0, 0>; 2362 def M2_mpy_rnd_hl_s1: T_M2_mpy <0b10, 0, 1, 1, 0>; 2363 def M2_mpy_rnd_hl_s0: T_M2_mpy <0b10, 0, 1, 0, 0>; 2364 def M2_mpy_rnd_hh_s1: T_M2_mpy <0b11, 0, 1, 1, 0>; 2365 def M2_mpy_rnd_hh_s0: T_M2_mpy <0b11, 0, 1, 0, 0>; 2366 2367 //Rd=mpy(Rs.[H|L],Rt.[H|L])[:<<1][:sat] 2368 //Rd=mpy(Rs.[H|L],Rt.[H|L])[:<<1][:rnd][:sat] 2369 let Defs = [USR_OVF] in { 2370 def M2_mpy_sat_ll_s1: T_M2_mpy <0b00, 1, 0, 1, 0>; 2371 def M2_mpy_sat_ll_s0: T_M2_mpy <0b00, 1, 0, 0, 0>; 2372 def M2_mpy_sat_lh_s1: T_M2_mpy <0b01, 1, 0, 1, 0>; 2373 def M2_mpy_sat_lh_s0: T_M2_mpy <0b01, 1, 0, 0, 0>; 2374 def M2_mpy_sat_hl_s1: T_M2_mpy <0b10, 1, 0, 1, 0>; 2375 def M2_mpy_sat_hl_s0: T_M2_mpy <0b10, 1, 0, 0, 0>; 2376 def M2_mpy_sat_hh_s1: T_M2_mpy <0b11, 1, 0, 1, 0>; 2377 def M2_mpy_sat_hh_s0: T_M2_mpy <0b11, 1, 0, 0, 0>; 2378 2379 def M2_mpy_sat_rnd_ll_s1: T_M2_mpy <0b00, 1, 1, 1, 0>; 2380 def M2_mpy_sat_rnd_ll_s0: T_M2_mpy <0b00, 1, 1, 0, 0>; 2381 def M2_mpy_sat_rnd_lh_s1: T_M2_mpy <0b01, 1, 1, 1, 0>; 2382 def M2_mpy_sat_rnd_lh_s0: T_M2_mpy <0b01, 1, 1, 0, 0>; 2383 def M2_mpy_sat_rnd_hl_s1: T_M2_mpy <0b10, 1, 1, 1, 0>; 2384 def M2_mpy_sat_rnd_hl_s0: T_M2_mpy <0b10, 1, 1, 0, 0>; 2385 def M2_mpy_sat_rnd_hh_s1: T_M2_mpy <0b11, 1, 1, 1, 0>; 2386 def M2_mpy_sat_rnd_hh_s0: T_M2_mpy <0b11, 1, 1, 0, 0>; 2387 } 2388 2389 //===----------------------------------------------------------------------===// 2390 // Template Class 2391 // MPYS / Multipy signed/unsigned halfwords and add/subtract the 2392 // result from the accumulator. 2393 //Rx [-+]= mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:sat] 2394 //===----------------------------------------------------------------------===// 2395 2396 let hasNewValue = 1, opNewValue = 0 in 2397 class T_M2_mpy_acc < bits<2> LHbits, bit isSat, bit isNac, 2398 bit hasShift, bit isUnsigned > 2399 : MInst_acc<(outs IntRegs:$Rx), (ins IntRegs:$dst2, IntRegs:$Rs, IntRegs:$Rt), 2400 "$Rx "#!if(isNac,"-= ","+= ")#!if(isUnsigned,"mpyu","mpy") 2401 #"($Rs."#!if(LHbits{1},"h","l") 2402 #", $Rt."#!if(LHbits{0},"h)","l)") 2403 #!if(hasShift,":<<1","") 2404 #!if(isSat,":sat",""), 2405 [], "$dst2 = $Rx", M_tc_3x_SLOT23 > { 2406 bits<5> Rx; 2407 bits<5> Rs; 2408 bits<5> Rt; 2409 2410 let IClass = 0b1110; 2411 let Inst{27-24} = 0b1110; 2412 let Inst{23} = hasShift; 2413 let Inst{22} = isUnsigned; 2414 let Inst{21} = isNac; 2415 let Inst{7} = isSat; 2416 let Inst{6-5} = LHbits; 2417 let Inst{4-0} = Rx; 2418 let Inst{20-16} = Rs; 2419 let Inst{12-8} = Rt; 2420 } 2421 2422 //Rx += mpy(Rs.[H|L],Rt.[H|L])[:<<1] 2423 def M2_mpy_acc_ll_s1: T_M2_mpy_acc <0b00, 0, 0, 1, 0>; 2424 def M2_mpy_acc_ll_s0: T_M2_mpy_acc <0b00, 0, 0, 0, 0>; 2425 def M2_mpy_acc_lh_s1: T_M2_mpy_acc <0b01, 0, 0, 1, 0>; 2426 def M2_mpy_acc_lh_s0: T_M2_mpy_acc <0b01, 0, 0, 0, 0>; 2427 def M2_mpy_acc_hl_s1: T_M2_mpy_acc <0b10, 0, 0, 1, 0>; 2428 def M2_mpy_acc_hl_s0: T_M2_mpy_acc <0b10, 0, 0, 0, 0>; 2429 def M2_mpy_acc_hh_s1: T_M2_mpy_acc <0b11, 0, 0, 1, 0>; 2430 def M2_mpy_acc_hh_s0: T_M2_mpy_acc <0b11, 0, 0, 0, 0>; 2431 2432 //Rx += mpyu(Rs.[H|L],Rt.[H|L])[:<<1] 2433 def M2_mpyu_acc_ll_s1: T_M2_mpy_acc <0b00, 0, 0, 1, 1>; 2434 def M2_mpyu_acc_ll_s0: T_M2_mpy_acc <0b00, 0, 0, 0, 1>; 2435 def M2_mpyu_acc_lh_s1: T_M2_mpy_acc <0b01, 0, 0, 1, 1>; 2436 def M2_mpyu_acc_lh_s0: T_M2_mpy_acc <0b01, 0, 0, 0, 1>; 2437 def M2_mpyu_acc_hl_s1: T_M2_mpy_acc <0b10, 0, 0, 1, 1>; 2438 def M2_mpyu_acc_hl_s0: T_M2_mpy_acc <0b10, 0, 0, 0, 1>; 2439 def M2_mpyu_acc_hh_s1: T_M2_mpy_acc <0b11, 0, 0, 1, 1>; 2440 def M2_mpyu_acc_hh_s0: T_M2_mpy_acc <0b11, 0, 0, 0, 1>; 2441 2442 //Rx -= mpy(Rs.[H|L],Rt.[H|L])[:<<1] 2443 def M2_mpy_nac_ll_s1: T_M2_mpy_acc <0b00, 0, 1, 1, 0>; 2444 def M2_mpy_nac_ll_s0: T_M2_mpy_acc <0b00, 0, 1, 0, 0>; 2445 def M2_mpy_nac_lh_s1: T_M2_mpy_acc <0b01, 0, 1, 1, 0>; 2446 def M2_mpy_nac_lh_s0: T_M2_mpy_acc <0b01, 0, 1, 0, 0>; 2447 def M2_mpy_nac_hl_s1: T_M2_mpy_acc <0b10, 0, 1, 1, 0>; 2448 def M2_mpy_nac_hl_s0: T_M2_mpy_acc <0b10, 0, 1, 0, 0>; 2449 def M2_mpy_nac_hh_s1: T_M2_mpy_acc <0b11, 0, 1, 1, 0>; 2450 def M2_mpy_nac_hh_s0: T_M2_mpy_acc <0b11, 0, 1, 0, 0>; 2451 2452 //Rx -= mpyu(Rs.[H|L],Rt.[H|L])[:<<1] 2453 def M2_mpyu_nac_ll_s1: T_M2_mpy_acc <0b00, 0, 1, 1, 1>; 2454 def M2_mpyu_nac_ll_s0: T_M2_mpy_acc <0b00, 0, 1, 0, 1>; 2455 def M2_mpyu_nac_lh_s1: T_M2_mpy_acc <0b01, 0, 1, 1, 1>; 2456 def M2_mpyu_nac_lh_s0: T_M2_mpy_acc <0b01, 0, 1, 0, 1>; 2457 def M2_mpyu_nac_hl_s1: T_M2_mpy_acc <0b10, 0, 1, 1, 1>; 2458 def M2_mpyu_nac_hl_s0: T_M2_mpy_acc <0b10, 0, 1, 0, 1>; 2459 def M2_mpyu_nac_hh_s1: T_M2_mpy_acc <0b11, 0, 1, 1, 1>; 2460 def M2_mpyu_nac_hh_s0: T_M2_mpy_acc <0b11, 0, 1, 0, 1>; 2461 2462 //Rx += mpy(Rs.[H|L],Rt.[H|L])[:<<1]:sat 2463 def M2_mpy_acc_sat_ll_s1: T_M2_mpy_acc <0b00, 1, 0, 1, 0>; 2464 def M2_mpy_acc_sat_ll_s0: T_M2_mpy_acc <0b00, 1, 0, 0, 0>; 2465 def M2_mpy_acc_sat_lh_s1: T_M2_mpy_acc <0b01, 1, 0, 1, 0>; 2466 def M2_mpy_acc_sat_lh_s0: T_M2_mpy_acc <0b01, 1, 0, 0, 0>; 2467 def M2_mpy_acc_sat_hl_s1: T_M2_mpy_acc <0b10, 1, 0, 1, 0>; 2468 def M2_mpy_acc_sat_hl_s0: T_M2_mpy_acc <0b10, 1, 0, 0, 0>; 2469 def M2_mpy_acc_sat_hh_s1: T_M2_mpy_acc <0b11, 1, 0, 1, 0>; 2470 def M2_mpy_acc_sat_hh_s0: T_M2_mpy_acc <0b11, 1, 0, 0, 0>; 2471 2472 //Rx -= mpy(Rs.[H|L],Rt.[H|L])[:<<1]:sat 2473 def M2_mpy_nac_sat_ll_s1: T_M2_mpy_acc <0b00, 1, 1, 1, 0>; 2474 def M2_mpy_nac_sat_ll_s0: T_M2_mpy_acc <0b00, 1, 1, 0, 0>; 2475 def M2_mpy_nac_sat_lh_s1: T_M2_mpy_acc <0b01, 1, 1, 1, 0>; 2476 def M2_mpy_nac_sat_lh_s0: T_M2_mpy_acc <0b01, 1, 1, 0, 0>; 2477 def M2_mpy_nac_sat_hl_s1: T_M2_mpy_acc <0b10, 1, 1, 1, 0>; 2478 def M2_mpy_nac_sat_hl_s0: T_M2_mpy_acc <0b10, 1, 1, 0, 0>; 2479 def M2_mpy_nac_sat_hh_s1: T_M2_mpy_acc <0b11, 1, 1, 1, 0>; 2480 def M2_mpy_nac_sat_hh_s0: T_M2_mpy_acc <0b11, 1, 1, 0, 0>; 2481 2482 //===----------------------------------------------------------------------===// 2483 // Template Class 2484 // MPYS / Multipy signed/unsigned halfwords and add/subtract the 2485 // result from the 64-bit destination register. 2486 //Rxx [-+]= mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:sat] 2487 //===----------------------------------------------------------------------===// 2488 2489 class T_M2_mpyd_acc < bits<2> LHbits, bit isNac, bit hasShift, bit isUnsigned> 2490 : MInst_acc<(outs DoubleRegs:$Rxx), 2491 (ins DoubleRegs:$dst2, IntRegs:$Rs, IntRegs:$Rt), 2492 "$Rxx "#!if(isNac,"-= ","+= ")#!if(isUnsigned,"mpyu","mpy") 2493 #"($Rs."#!if(LHbits{1},"h","l") 2494 #", $Rt."#!if(LHbits{0},"h)","l)") 2495 #!if(hasShift,":<<1",""), 2496 [], "$dst2 = $Rxx", M_tc_3x_SLOT23 > { 2497 bits<5> Rxx; 2498 bits<5> Rs; 2499 bits<5> Rt; 2500 2501 let IClass = 0b1110; 2502 2503 let Inst{27-24} = 0b0110; 2504 let Inst{23} = hasShift; 2505 let Inst{22} = isUnsigned; 2506 let Inst{21} = isNac; 2507 let Inst{7} = 0; 2508 let Inst{6-5} = LHbits; 2509 let Inst{4-0} = Rxx; 2510 let Inst{20-16} = Rs; 2511 let Inst{12-8} = Rt; 2512 } 2513 2514 def M2_mpyd_acc_hh_s0: T_M2_mpyd_acc <0b11, 0, 0, 0>; 2515 def M2_mpyd_acc_hl_s0: T_M2_mpyd_acc <0b10, 0, 0, 0>; 2516 def M2_mpyd_acc_lh_s0: T_M2_mpyd_acc <0b01, 0, 0, 0>; 2517 def M2_mpyd_acc_ll_s0: T_M2_mpyd_acc <0b00, 0, 0, 0>; 2518 2519 def M2_mpyd_acc_hh_s1: T_M2_mpyd_acc <0b11, 0, 1, 0>; 2520 def M2_mpyd_acc_hl_s1: T_M2_mpyd_acc <0b10, 0, 1, 0>; 2521 def M2_mpyd_acc_lh_s1: T_M2_mpyd_acc <0b01, 0, 1, 0>; 2522 def M2_mpyd_acc_ll_s1: T_M2_mpyd_acc <0b00, 0, 1, 0>; 2523 2524 def M2_mpyd_nac_hh_s0: T_M2_mpyd_acc <0b11, 1, 0, 0>; 2525 def M2_mpyd_nac_hl_s0: T_M2_mpyd_acc <0b10, 1, 0, 0>; 2526 def M2_mpyd_nac_lh_s0: T_M2_mpyd_acc <0b01, 1, 0, 0>; 2527 def M2_mpyd_nac_ll_s0: T_M2_mpyd_acc <0b00, 1, 0, 0>; 2528 2529 def M2_mpyd_nac_hh_s1: T_M2_mpyd_acc <0b11, 1, 1, 0>; 2530 def M2_mpyd_nac_hl_s1: T_M2_mpyd_acc <0b10, 1, 1, 0>; 2531 def M2_mpyd_nac_lh_s1: T_M2_mpyd_acc <0b01, 1, 1, 0>; 2532 def M2_mpyd_nac_ll_s1: T_M2_mpyd_acc <0b00, 1, 1, 0>; 2533 2534 def M2_mpyud_acc_hh_s0: T_M2_mpyd_acc <0b11, 0, 0, 1>; 2535 def M2_mpyud_acc_hl_s0: T_M2_mpyd_acc <0b10, 0, 0, 1>; 2536 def M2_mpyud_acc_lh_s0: T_M2_mpyd_acc <0b01, 0, 0, 1>; 2537 def M2_mpyud_acc_ll_s0: T_M2_mpyd_acc <0b00, 0, 0, 1>; 2538 2539 def M2_mpyud_acc_hh_s1: T_M2_mpyd_acc <0b11, 0, 1, 1>; 2540 def M2_mpyud_acc_hl_s1: T_M2_mpyd_acc <0b10, 0, 1, 1>; 2541 def M2_mpyud_acc_lh_s1: T_M2_mpyd_acc <0b01, 0, 1, 1>; 2542 def M2_mpyud_acc_ll_s1: T_M2_mpyd_acc <0b00, 0, 1, 1>; 2543 2544 def M2_mpyud_nac_hh_s0: T_M2_mpyd_acc <0b11, 1, 0, 1>; 2545 def M2_mpyud_nac_hl_s0: T_M2_mpyd_acc <0b10, 1, 0, 1>; 2546 def M2_mpyud_nac_lh_s0: T_M2_mpyd_acc <0b01, 1, 0, 1>; 2547 def M2_mpyud_nac_ll_s0: T_M2_mpyd_acc <0b00, 1, 0, 1>; 2548 2549 def M2_mpyud_nac_hh_s1: T_M2_mpyd_acc <0b11, 1, 1, 1>; 2550 def M2_mpyud_nac_hl_s1: T_M2_mpyd_acc <0b10, 1, 1, 1>; 2551 def M2_mpyud_nac_lh_s1: T_M2_mpyd_acc <0b01, 1, 1, 1>; 2552 def M2_mpyud_nac_ll_s1: T_M2_mpyd_acc <0b00, 1, 1, 1>; 2553 2554 //===----------------------------------------------------------------------===// 2555 // Template Class -- Vector Multipy 2556 // Used for complex multiply real or imaginary, dual multiply and even halfwords 2557 //===----------------------------------------------------------------------===// 2558 class T_M2_vmpy < string opc, bits<3> MajOp, bits<3> MinOp, bit hasShift, 2559 bit isRnd, bit isSat > 2560 : MInst <(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss, DoubleRegs:$Rtt), 2561 "$Rdd = "#opc#"($Rss, $Rtt)"#!if(hasShift,":<<1","") 2562 #!if(isRnd,":rnd","") 2563 #!if(isSat,":sat",""), 2564 [] > { 2565 bits<5> Rdd; 2566 bits<5> Rss; 2567 bits<5> Rtt; 2568 2569 let IClass = 0b1110; 2570 2571 let Inst{27-24} = 0b1000; 2572 let Inst{23-21} = MajOp; 2573 let Inst{7-5} = MinOp; 2574 let Inst{4-0} = Rdd; 2575 let Inst{20-16} = Rss; 2576 let Inst{12-8} = Rtt; 2577 } 2578 2579 // Vector complex multiply imaginary: Rdd=vcmpyi(Rss,Rtt)[:<<1]:sat 2580 let Defs = [USR_OVF] in { 2581 def M2_vcmpy_s1_sat_i: T_M2_vmpy <"vcmpyi", 0b110, 0b110, 1, 0, 1>; 2582 def M2_vcmpy_s0_sat_i: T_M2_vmpy <"vcmpyi", 0b010, 0b110, 0, 0, 1>; 2583 2584 // Vector complex multiply real: Rdd=vcmpyr(Rss,Rtt)[:<<1]:sat 2585 def M2_vcmpy_s1_sat_r: T_M2_vmpy <"vcmpyr", 0b101, 0b110, 1, 0, 1>; 2586 def M2_vcmpy_s0_sat_r: T_M2_vmpy <"vcmpyr", 0b001, 0b110, 0, 0, 1>; 2587 2588 // Vector dual multiply: Rdd=vdmpy(Rss,Rtt)[:<<1]:sat 2589 def M2_vdmpys_s1: T_M2_vmpy <"vdmpy", 0b100, 0b100, 1, 0, 1>; 2590 def M2_vdmpys_s0: T_M2_vmpy <"vdmpy", 0b000, 0b100, 0, 0, 1>; 2591 2592 // Vector multiply even halfwords: Rdd=vmpyeh(Rss,Rtt)[:<<1]:sat 2593 def M2_vmpy2es_s1: T_M2_vmpy <"vmpyeh", 0b100, 0b110, 1, 0, 1>; 2594 def M2_vmpy2es_s0: T_M2_vmpy <"vmpyeh", 0b000, 0b110, 0, 0, 1>; 2595 2596 //Rdd=vmpywoh(Rss,Rtt)[:<<1][:rnd]:sat 2597 def M2_mmpyh_s0: T_M2_vmpy <"vmpywoh", 0b000, 0b111, 0, 0, 1>; 2598 def M2_mmpyh_s1: T_M2_vmpy <"vmpywoh", 0b100, 0b111, 1, 0, 1>; 2599 def M2_mmpyh_rs0: T_M2_vmpy <"vmpywoh", 0b001, 0b111, 0, 1, 1>; 2600 def M2_mmpyh_rs1: T_M2_vmpy <"vmpywoh", 0b101, 0b111, 1, 1, 1>; 2601 2602 //Rdd=vmpyweh(Rss,Rtt)[:<<1][:rnd]:sat 2603 def M2_mmpyl_s0: T_M2_vmpy <"vmpyweh", 0b000, 0b101, 0, 0, 1>; 2604 def M2_mmpyl_s1: T_M2_vmpy <"vmpyweh", 0b100, 0b101, 1, 0, 1>; 2605 def M2_mmpyl_rs0: T_M2_vmpy <"vmpyweh", 0b001, 0b101, 0, 1, 1>; 2606 def M2_mmpyl_rs1: T_M2_vmpy <"vmpyweh", 0b101, 0b101, 1, 1, 1>; 2607 2608 //Rdd=vmpywouh(Rss,Rtt)[:<<1][:rnd]:sat 2609 def M2_mmpyuh_s0: T_M2_vmpy <"vmpywouh", 0b010, 0b111, 0, 0, 1>; 2610 def M2_mmpyuh_s1: T_M2_vmpy <"vmpywouh", 0b110, 0b111, 1, 0, 1>; 2611 def M2_mmpyuh_rs0: T_M2_vmpy <"vmpywouh", 0b011, 0b111, 0, 1, 1>; 2612 def M2_mmpyuh_rs1: T_M2_vmpy <"vmpywouh", 0b111, 0b111, 1, 1, 1>; 2613 2614 //Rdd=vmpyweuh(Rss,Rtt)[:<<1][:rnd]:sat 2615 def M2_mmpyul_s0: T_M2_vmpy <"vmpyweuh", 0b010, 0b101, 0, 0, 1>; 2616 def M2_mmpyul_s1: T_M2_vmpy <"vmpyweuh", 0b110, 0b101, 1, 0, 1>; 2617 def M2_mmpyul_rs0: T_M2_vmpy <"vmpyweuh", 0b011, 0b101, 0, 1, 1>; 2618 def M2_mmpyul_rs1: T_M2_vmpy <"vmpyweuh", 0b111, 0b101, 1, 1, 1>; 2619 } 2620 2621 let hasNewValue = 1, opNewValue = 0 in 2622 class T_MType_mpy <string mnemonic, bits<4> RegTyBits, RegisterClass RC, 2623 bits<3> MajOp, bits<3> MinOp, bit isSat = 0, bit isRnd = 0, 2624 string op2Suffix = "", bit isRaw = 0, bit isHi = 0 > 2625 : MInst <(outs IntRegs:$dst), (ins RC:$src1, RC:$src2), 2626 "$dst = "#mnemonic 2627 #"($src1, $src2"#op2Suffix#")" 2628 #!if(MajOp{2}, ":<<1", "") 2629 #!if(isRnd, ":rnd", "") 2630 #!if(isSat, ":sat", "") 2631 #!if(isRaw, !if(isHi, ":raw:hi", ":raw:lo"), ""), [] > { 2632 bits<5> dst; 2633 bits<5> src1; 2634 bits<5> src2; 2635 2636 let IClass = 0b1110; 2637 2638 let Inst{27-24} = RegTyBits; 2639 let Inst{23-21} = MajOp; 2640 let Inst{20-16} = src1; 2641 let Inst{13} = 0b0; 2642 let Inst{12-8} = src2; 2643 let Inst{7-5} = MinOp; 2644 let Inst{4-0} = dst; 2645 } 2646 2647 class T_MType_vrcmpy <string mnemonic, bits<3> MajOp, bits<3> MinOp, bit isHi> 2648 : T_MType_mpy <mnemonic, 0b1001, DoubleRegs, MajOp, MinOp, 1, 1, "", 1, isHi>; 2649 2650 class T_MType_dd <string mnemonic, bits<3> MajOp, bits<3> MinOp, 2651 bit isSat = 0, bit isRnd = 0 > 2652 : T_MType_mpy <mnemonic, 0b1001, DoubleRegs, MajOp, MinOp, isSat, isRnd>; 2653 2654 class T_MType_rr1 <string mnemonic, bits<3> MajOp, bits<3> MinOp, 2655 bit isSat = 0, bit isRnd = 0 > 2656 : T_MType_mpy<mnemonic, 0b1101, IntRegs, MajOp, MinOp, isSat, isRnd>; 2657 2658 class T_MType_rr2 <string mnemonic, bits<3> MajOp, bits<3> MinOp, 2659 bit isSat = 0, bit isRnd = 0, string op2str = "" > 2660 : T_MType_mpy<mnemonic, 0b1101, IntRegs, MajOp, MinOp, isSat, isRnd, op2str>; 2661 2662 def M2_vradduh : T_MType_dd <"vradduh", 0b000, 0b001, 0, 0>; 2663 def M2_vdmpyrs_s0 : T_MType_dd <"vdmpy", 0b000, 0b000, 1, 1>; 2664 def M2_vdmpyrs_s1 : T_MType_dd <"vdmpy", 0b100, 0b000, 1, 1>; 2665 2666 let CextOpcode = "mpyi", InputType = "reg" in 2667 def M2_mpyi : T_MType_rr1 <"mpyi", 0b000, 0b000>, ImmRegRel; 2668 2669 def M2_mpy_up : T_MType_rr1 <"mpy", 0b000, 0b001>; 2670 def M2_mpyu_up : T_MType_rr1 <"mpyu", 0b010, 0b001>; 2671 2672 def M2_dpmpyss_rnd_s0 : T_MType_rr1 <"mpy", 0b001, 0b001, 0, 1>; 2673 2674 def M2_vmpy2s_s0pack : T_MType_rr1 <"vmpyh", 0b001, 0b111, 1, 1>; 2675 def M2_vmpy2s_s1pack : T_MType_rr1 <"vmpyh", 0b101, 0b111, 1, 1>; 2676 2677 def M2_hmmpyh_rs1 : T_MType_rr2 <"mpy", 0b101, 0b100, 1, 1, ".h">; 2678 def M2_hmmpyl_rs1 : T_MType_rr2 <"mpy", 0b111, 0b100, 1, 1, ".l">; 2679 2680 def M2_cmpyrs_s0 : T_MType_rr2 <"cmpy", 0b001, 0b110, 1, 1>; 2681 def M2_cmpyrs_s1 : T_MType_rr2 <"cmpy", 0b101, 0b110, 1, 1>; 2682 def M2_cmpyrsc_s0 : T_MType_rr2 <"cmpy", 0b011, 0b110, 1, 1, "*">; 2683 def M2_cmpyrsc_s1 : T_MType_rr2 <"cmpy", 0b111, 0b110, 1, 1, "*">; 2684 2685 // V4 Instructions 2686 def M2_vraddh : T_MType_dd <"vraddh", 0b001, 0b111, 0>; 2687 def M2_mpysu_up : T_MType_rr1 <"mpysu", 0b011, 0b001, 0>; 2688 def M2_mpy_up_s1 : T_MType_rr1 <"mpy", 0b101, 0b010, 0>; 2689 def M2_mpy_up_s1_sat : T_MType_rr1 <"mpy", 0b111, 0b000, 1>; 2690 2691 def M2_hmmpyh_s1 : T_MType_rr2 <"mpy", 0b101, 0b000, 1, 0, ".h">; 2692 def M2_hmmpyl_s1 : T_MType_rr2 <"mpy", 0b101, 0b001, 1, 0, ".l">; 2693 2694 def: Pat<(i32 (mul I32:$src1, I32:$src2)), (M2_mpyi I32:$src1, I32:$src2)>; 2695 def: Pat<(i32 (mulhs I32:$src1, I32:$src2)), (M2_mpy_up I32:$src1, I32:$src2)>; 2696 def: Pat<(i32 (mulhu I32:$src1, I32:$src2)), (M2_mpyu_up I32:$src1, I32:$src2)>; 2697 2698 let hasNewValue = 1, opNewValue = 0 in 2699 class T_MType_mpy_ri <bit isNeg, Operand ImmOp, list<dag> pattern> 2700 : MInst < (outs IntRegs:$Rd), (ins IntRegs:$Rs, ImmOp:$u8), 2701 "$Rd ="#!if(isNeg, "- ", "+ ")#"mpyi($Rs, #$u8)" , 2702 pattern, "", M_tc_3x_SLOT23> { 2703 bits<5> Rd; 2704 bits<5> Rs; 2705 bits<8> u8; 2706 2707 let IClass = 0b1110; 2708 2709 let Inst{27-24} = 0b0000; 2710 let Inst{23} = isNeg; 2711 let Inst{13} = 0b0; 2712 let Inst{4-0} = Rd; 2713 let Inst{20-16} = Rs; 2714 let Inst{12-5} = u8; 2715 } 2716 2717 let isExtendable = 1, opExtentBits = 8, opExtendable = 2 in 2718 def M2_mpysip : T_MType_mpy_ri <0, u8Ext, 2719 [(set (i32 IntRegs:$Rd), (mul IntRegs:$Rs, u32ImmPred:$u8))]>; 2720 2721 def M2_mpysin : T_MType_mpy_ri <1, u8Imm, 2722 [(set (i32 IntRegs:$Rd), (ineg (mul IntRegs:$Rs, 2723 u8ImmPred:$u8)))]>; 2724 2725 // Assember mapped to M2_mpyi 2726 let isAsmParserOnly = 1 in 2727 def M2_mpyui : MInst<(outs IntRegs:$dst), 2728 (ins IntRegs:$src1, IntRegs:$src2), 2729 "$dst = mpyui($src1, $src2)">; 2730 2731 // Rd=mpyi(Rs,#m9) 2732 // s9 is NOT the same as m9 - but it works.. so far. 2733 // Assembler maps to either Rd=+mpyi(Rs,#u8) or Rd=-mpyi(Rs,#u8) 2734 // depending on the value of m9. See Arch Spec. 2735 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 9, 2736 CextOpcode = "mpyi", InputType = "imm", hasNewValue = 1, 2737 isAsmParserOnly = 1 in 2738 def M2_mpysmi : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, s9Ext:$src2), 2739 "$dst = mpyi($src1, #$src2)", 2740 [(set (i32 IntRegs:$dst), (mul (i32 IntRegs:$src1), 2741 s32ImmPred:$src2))]>, ImmRegRel; 2742 2743 let hasNewValue = 1, isExtendable = 1, opExtentBits = 8, opExtendable = 3, 2744 InputType = "imm" in 2745 class T_MType_acc_ri <string mnemonic, bits<3> MajOp, Operand ImmOp, 2746 list<dag> pattern = []> 2747 : MInst < (outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2, ImmOp:$src3), 2748 "$dst "#mnemonic#"($src2, #$src3)", 2749 pattern, "$src1 = $dst", M_tc_2_SLOT23> { 2750 bits<5> dst; 2751 bits<5> src2; 2752 bits<8> src3; 2753 2754 let IClass = 0b1110; 2755 2756 let Inst{27-26} = 0b00; 2757 let Inst{25-23} = MajOp; 2758 let Inst{20-16} = src2; 2759 let Inst{13} = 0b0; 2760 let Inst{12-5} = src3; 2761 let Inst{4-0} = dst; 2762 } 2763 2764 let InputType = "reg", hasNewValue = 1 in 2765 class T_MType_acc_rr <string mnemonic, bits<3> MajOp, bits<3> MinOp, 2766 bit isSwap = 0, list<dag> pattern = [], bit hasNot = 0, 2767 bit isSat = 0, bit isShift = 0> 2768 : MInst < (outs IntRegs:$dst), 2769 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), 2770 "$dst "#mnemonic#"($src2, "#!if(hasNot, "~$src3)","$src3)") 2771 #!if(isShift, ":<<1", "") 2772 #!if(isSat, ":sat", ""), 2773 pattern, "$src1 = $dst", M_tc_2_SLOT23 > { 2774 bits<5> dst; 2775 bits<5> src2; 2776 bits<5> src3; 2777 2778 let IClass = 0b1110; 2779 2780 let Inst{27-24} = 0b1111; 2781 let Inst{23-21} = MajOp; 2782 let Inst{20-16} = !if(isSwap, src3, src2); 2783 let Inst{13} = 0b0; 2784 let Inst{12-8} = !if(isSwap, src2, src3); 2785 let Inst{7-5} = MinOp; 2786 let Inst{4-0} = dst; 2787 } 2788 2789 let CextOpcode = "MPYI_acc", Itinerary = M_tc_3x_SLOT23 in { 2790 def M2_macsip : T_MType_acc_ri <"+= mpyi", 0b010, u8Ext, 2791 [(set (i32 IntRegs:$dst), 2792 (add (mul IntRegs:$src2, u32ImmPred:$src3), 2793 IntRegs:$src1))]>, ImmRegRel; 2794 2795 def M2_maci : T_MType_acc_rr <"+= mpyi", 0b000, 0b000, 0, 2796 [(set (i32 IntRegs:$dst), 2797 (add (mul IntRegs:$src2, IntRegs:$src3), 2798 IntRegs:$src1))]>, ImmRegRel; 2799 } 2800 2801 let CextOpcode = "ADD_acc" in { 2802 let isExtentSigned = 1 in 2803 def M2_accii : T_MType_acc_ri <"+= add", 0b100, s8Ext, 2804 [(set (i32 IntRegs:$dst), 2805 (add (add (i32 IntRegs:$src2), s32ImmPred:$src3), 2806 (i32 IntRegs:$src1)))]>, ImmRegRel; 2807 2808 def M2_acci : T_MType_acc_rr <"+= add", 0b000, 0b001, 0, 2809 [(set (i32 IntRegs:$dst), 2810 (add (add (i32 IntRegs:$src2), (i32 IntRegs:$src3)), 2811 (i32 IntRegs:$src1)))]>, ImmRegRel; 2812 } 2813 2814 let CextOpcode = "SUB_acc" in { 2815 let isExtentSigned = 1 in 2816 def M2_naccii : T_MType_acc_ri <"-= add", 0b101, s8Ext>, ImmRegRel; 2817 2818 def M2_nacci : T_MType_acc_rr <"-= add", 0b100, 0b001, 0>, ImmRegRel; 2819 } 2820 2821 let Itinerary = M_tc_3x_SLOT23 in 2822 def M2_macsin : T_MType_acc_ri <"-= mpyi", 0b011, u8Ext>; 2823 2824 def M2_xor_xacc : T_MType_acc_rr < "^= xor", 0b100, 0b011, 0>; 2825 def M2_subacc : T_MType_acc_rr <"+= sub", 0b000, 0b011, 1>; 2826 2827 class T_MType_acc_pat1 <InstHexagon MI, SDNode firstOp, SDNode secOp, 2828 PatLeaf ImmPred> 2829 : Pat <(secOp IntRegs:$src1, (firstOp IntRegs:$src2, ImmPred:$src3)), 2830 (MI IntRegs:$src1, IntRegs:$src2, ImmPred:$src3)>; 2831 2832 class T_MType_acc_pat2 <InstHexagon MI, SDNode firstOp, SDNode secOp> 2833 : Pat <(i32 (secOp IntRegs:$src1, (firstOp IntRegs:$src2, IntRegs:$src3))), 2834 (MI IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>; 2835 2836 def : T_MType_acc_pat2 <M2_xor_xacc, xor, xor>; 2837 def : T_MType_acc_pat1 <M2_macsin, mul, sub, u32ImmPred>; 2838 2839 def : T_MType_acc_pat1 <M2_naccii, add, sub, s32ImmPred>; 2840 def : T_MType_acc_pat2 <M2_nacci, add, sub>; 2841 2842 //===----------------------------------------------------------------------===// 2843 // Template Class -- XType Vector Instructions 2844 //===----------------------------------------------------------------------===// 2845 class T_XTYPE_Vect < string opc, bits<3> MajOp, bits<3> MinOp, bit isConj > 2846 : MInst <(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss, DoubleRegs:$Rtt), 2847 "$Rdd = "#opc#"($Rss, $Rtt"#!if(isConj,"*)",")"), 2848 [] > { 2849 bits<5> Rdd; 2850 bits<5> Rss; 2851 bits<5> Rtt; 2852 2853 let IClass = 0b1110; 2854 2855 let Inst{27-24} = 0b1000; 2856 let Inst{23-21} = MajOp; 2857 let Inst{7-5} = MinOp; 2858 let Inst{4-0} = Rdd; 2859 let Inst{20-16} = Rss; 2860 let Inst{12-8} = Rtt; 2861 } 2862 2863 class T_XTYPE_Vect_acc < string opc, bits<3> MajOp, bits<3> MinOp, bit isConj > 2864 : MInst <(outs DoubleRegs:$Rdd), 2865 (ins DoubleRegs:$dst2, DoubleRegs:$Rss, DoubleRegs:$Rtt), 2866 "$Rdd += "#opc#"($Rss, $Rtt"#!if(isConj,"*)",")"), 2867 [], "$dst2 = $Rdd",M_tc_3x_SLOT23 > { 2868 bits<5> Rdd; 2869 bits<5> Rss; 2870 bits<5> Rtt; 2871 2872 let IClass = 0b1110; 2873 2874 let Inst{27-24} = 0b1010; 2875 let Inst{23-21} = MajOp; 2876 let Inst{7-5} = MinOp; 2877 let Inst{4-0} = Rdd; 2878 let Inst{20-16} = Rss; 2879 let Inst{12-8} = Rtt; 2880 } 2881 2882 class T_XTYPE_Vect_diff < bits<3> MajOp, string opc > 2883 : MInst <(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rtt, DoubleRegs:$Rss), 2884 "$Rdd = "#opc#"($Rtt, $Rss)", 2885 [], "",M_tc_2_SLOT23 > { 2886 bits<5> Rdd; 2887 bits<5> Rss; 2888 bits<5> Rtt; 2889 2890 let IClass = 0b1110; 2891 2892 let Inst{27-24} = 0b1000; 2893 let Inst{23-21} = MajOp; 2894 let Inst{7-5} = 0b000; 2895 let Inst{4-0} = Rdd; 2896 let Inst{20-16} = Rss; 2897 let Inst{12-8} = Rtt; 2898 } 2899 2900 // Vector reduce add unsigned bytes: Rdd32=vrmpybu(Rss32,Rtt32) 2901 def A2_vraddub: T_XTYPE_Vect <"vraddub", 0b010, 0b001, 0>; 2902 def A2_vraddub_acc: T_XTYPE_Vect_acc <"vraddub", 0b010, 0b001, 0>; 2903 2904 // Vector sum of absolute differences unsigned bytes: Rdd=vrsadub(Rss,Rtt) 2905 def A2_vrsadub: T_XTYPE_Vect <"vrsadub", 0b010, 0b010, 0>; 2906 def A2_vrsadub_acc: T_XTYPE_Vect_acc <"vrsadub", 0b010, 0b010, 0>; 2907 2908 // Vector absolute difference: Rdd=vabsdiffh(Rtt,Rss) 2909 def M2_vabsdiffh: T_XTYPE_Vect_diff<0b011, "vabsdiffh">; 2910 2911 // Vector absolute difference words: Rdd=vabsdiffw(Rtt,Rss) 2912 def M2_vabsdiffw: T_XTYPE_Vect_diff<0b001, "vabsdiffw">; 2913 2914 // Vector reduce complex multiply real or imaginary: 2915 // Rdd[+]=vrcmpy[ir](Rss,Rtt[*]) 2916 def M2_vrcmpyi_s0: T_XTYPE_Vect <"vrcmpyi", 0b000, 0b000, 0>; 2917 def M2_vrcmpyi_s0c: T_XTYPE_Vect <"vrcmpyi", 0b010, 0b000, 1>; 2918 def M2_vrcmaci_s0: T_XTYPE_Vect_acc <"vrcmpyi", 0b000, 0b000, 0>; 2919 def M2_vrcmaci_s0c: T_XTYPE_Vect_acc <"vrcmpyi", 0b010, 0b000, 1>; 2920 2921 def M2_vrcmpyr_s0: T_XTYPE_Vect <"vrcmpyr", 0b000, 0b001, 0>; 2922 def M2_vrcmpyr_s0c: T_XTYPE_Vect <"vrcmpyr", 0b011, 0b001, 1>; 2923 def M2_vrcmacr_s0: T_XTYPE_Vect_acc <"vrcmpyr", 0b000, 0b001, 0>; 2924 def M2_vrcmacr_s0c: T_XTYPE_Vect_acc <"vrcmpyr", 0b011, 0b001, 1>; 2925 2926 // Vector reduce halfwords: 2927 // Rdd[+]=vrmpyh(Rss,Rtt) 2928 def M2_vrmpy_s0: T_XTYPE_Vect <"vrmpyh", 0b000, 0b010, 0>; 2929 def M2_vrmac_s0: T_XTYPE_Vect_acc <"vrmpyh", 0b000, 0b010, 0>; 2930 2931 //===----------------------------------------------------------------------===// 2932 // Template Class -- Vector Multipy with accumulation. 2933 // Used for complex multiply real or imaginary, dual multiply and even halfwords 2934 //===----------------------------------------------------------------------===// 2935 let Defs = [USR_OVF] in 2936 class T_M2_vmpy_acc_sat < string opc, bits<3> MajOp, bits<3> MinOp, 2937 bit hasShift, bit isRnd > 2938 : MInst <(outs DoubleRegs:$Rxx), 2939 (ins DoubleRegs:$dst2, DoubleRegs:$Rss, DoubleRegs:$Rtt), 2940 "$Rxx += "#opc#"($Rss, $Rtt)"#!if(hasShift,":<<1","") 2941 #!if(isRnd,":rnd","")#":sat", 2942 [], "$dst2 = $Rxx",M_tc_3x_SLOT23 > { 2943 bits<5> Rxx; 2944 bits<5> Rss; 2945 bits<5> Rtt; 2946 2947 let IClass = 0b1110; 2948 2949 let Inst{27-24} = 0b1010; 2950 let Inst{23-21} = MajOp; 2951 let Inst{7-5} = MinOp; 2952 let Inst{4-0} = Rxx; 2953 let Inst{20-16} = Rss; 2954 let Inst{12-8} = Rtt; 2955 } 2956 2957 class T_M2_vmpy_acc < string opc, bits<3> MajOp, bits<3> MinOp, 2958 bit hasShift, bit isRnd > 2959 : MInst <(outs DoubleRegs:$Rxx), 2960 (ins DoubleRegs:$dst2, DoubleRegs:$Rss, DoubleRegs:$Rtt), 2961 "$Rxx += "#opc#"($Rss, $Rtt)"#!if(hasShift,":<<1","") 2962 #!if(isRnd,":rnd",""), 2963 [], "$dst2 = $Rxx",M_tc_3x_SLOT23 > { 2964 bits<5> Rxx; 2965 bits<5> Rss; 2966 bits<5> Rtt; 2967 2968 let IClass = 0b1110; 2969 2970 let Inst{27-24} = 0b1010; 2971 let Inst{23-21} = MajOp; 2972 let Inst{7-5} = MinOp; 2973 let Inst{4-0} = Rxx; 2974 let Inst{20-16} = Rss; 2975 let Inst{12-8} = Rtt; 2976 } 2977 2978 // Vector multiply word by signed half with accumulation 2979 // Rxx+=vmpyw[eo]h(Rss,Rtt)[:<<1][:rnd]:sat 2980 def M2_mmacls_s1: T_M2_vmpy_acc_sat <"vmpyweh", 0b100, 0b101, 1, 0>; 2981 def M2_mmacls_s0: T_M2_vmpy_acc_sat <"vmpyweh", 0b000, 0b101, 0, 0>; 2982 def M2_mmacls_rs1: T_M2_vmpy_acc_sat <"vmpyweh", 0b101, 0b101, 1, 1>; 2983 def M2_mmacls_rs0: T_M2_vmpy_acc_sat <"vmpyweh", 0b001, 0b101, 0, 1>; 2984 2985 def M2_mmachs_s1: T_M2_vmpy_acc_sat <"vmpywoh", 0b100, 0b111, 1, 0>; 2986 def M2_mmachs_s0: T_M2_vmpy_acc_sat <"vmpywoh", 0b000, 0b111, 0, 0>; 2987 def M2_mmachs_rs1: T_M2_vmpy_acc_sat <"vmpywoh", 0b101, 0b111, 1, 1>; 2988 def M2_mmachs_rs0: T_M2_vmpy_acc_sat <"vmpywoh", 0b001, 0b111, 0, 1>; 2989 2990 // Vector multiply word by unsigned half with accumulation 2991 // Rxx+=vmpyw[eo]uh(Rss,Rtt)[:<<1][:rnd]:sat 2992 def M2_mmaculs_s1: T_M2_vmpy_acc_sat <"vmpyweuh", 0b110, 0b101, 1, 0>; 2993 def M2_mmaculs_s0: T_M2_vmpy_acc_sat <"vmpyweuh", 0b010, 0b101, 0, 0>; 2994 def M2_mmaculs_rs1: T_M2_vmpy_acc_sat <"vmpyweuh", 0b111, 0b101, 1, 1>; 2995 def M2_mmaculs_rs0: T_M2_vmpy_acc_sat <"vmpyweuh", 0b011, 0b101, 0, 1>; 2996 2997 def M2_mmacuhs_s1: T_M2_vmpy_acc_sat <"vmpywouh", 0b110, 0b111, 1, 0>; 2998 def M2_mmacuhs_s0: T_M2_vmpy_acc_sat <"vmpywouh", 0b010, 0b111, 0, 0>; 2999 def M2_mmacuhs_rs1: T_M2_vmpy_acc_sat <"vmpywouh", 0b111, 0b111, 1, 1>; 3000 def M2_mmacuhs_rs0: T_M2_vmpy_acc_sat <"vmpywouh", 0b011, 0b111, 0, 1>; 3001 3002 // Vector multiply even halfwords with accumulation 3003 // Rxx+=vmpyeh(Rss,Rtt)[:<<1][:sat] 3004 def M2_vmac2es: T_M2_vmpy_acc <"vmpyeh", 0b001, 0b010, 0, 0>; 3005 def M2_vmac2es_s1: T_M2_vmpy_acc_sat <"vmpyeh", 0b100, 0b110, 1, 0>; 3006 def M2_vmac2es_s0: T_M2_vmpy_acc_sat <"vmpyeh", 0b000, 0b110, 0, 0>; 3007 3008 // Vector dual multiply with accumulation 3009 // Rxx+=vdmpy(Rss,Rtt)[:sat] 3010 def M2_vdmacs_s1: T_M2_vmpy_acc_sat <"vdmpy", 0b100, 0b100, 1, 0>; 3011 def M2_vdmacs_s0: T_M2_vmpy_acc_sat <"vdmpy", 0b000, 0b100, 0, 0>; 3012 3013 // Vector complex multiply real or imaginary with accumulation 3014 // Rxx+=vcmpy[ir](Rss,Rtt):sat 3015 def M2_vcmac_s0_sat_r: T_M2_vmpy_acc_sat <"vcmpyr", 0b001, 0b100, 0, 0>; 3016 def M2_vcmac_s0_sat_i: T_M2_vmpy_acc_sat <"vcmpyi", 0b010, 0b100, 0, 0>; 3017 3018 //===----------------------------------------------------------------------===// 3019 // Template Class -- Multiply signed/unsigned halfwords with and without 3020 // saturation and rounding 3021 //===----------------------------------------------------------------------===// 3022 class T_M2_mpyd < bits<2> LHbits, bit isRnd, bit hasShift, bit isUnsigned > 3023 : MInst < (outs DoubleRegs:$Rdd), (ins IntRegs:$Rs, IntRegs:$Rt), 3024 "$Rdd = "#!if(isUnsigned,"mpyu","mpy")#"($Rs."#!if(LHbits{1},"h","l") 3025 #", $Rt."#!if(LHbits{0},"h)","l)") 3026 #!if(hasShift,":<<1","") 3027 #!if(isRnd,":rnd",""), 3028 [] > { 3029 bits<5> Rdd; 3030 bits<5> Rs; 3031 bits<5> Rt; 3032 3033 let IClass = 0b1110; 3034 3035 let Inst{27-24} = 0b0100; 3036 let Inst{23} = hasShift; 3037 let Inst{22} = isUnsigned; 3038 let Inst{21} = isRnd; 3039 let Inst{6-5} = LHbits; 3040 let Inst{4-0} = Rdd; 3041 let Inst{20-16} = Rs; 3042 let Inst{12-8} = Rt; 3043 } 3044 3045 def M2_mpyd_hh_s0: T_M2_mpyd<0b11, 0, 0, 0>; 3046 def M2_mpyd_hl_s0: T_M2_mpyd<0b10, 0, 0, 0>; 3047 def M2_mpyd_lh_s0: T_M2_mpyd<0b01, 0, 0, 0>; 3048 def M2_mpyd_ll_s0: T_M2_mpyd<0b00, 0, 0, 0>; 3049 3050 def M2_mpyd_hh_s1: T_M2_mpyd<0b11, 0, 1, 0>; 3051 def M2_mpyd_hl_s1: T_M2_mpyd<0b10, 0, 1, 0>; 3052 def M2_mpyd_lh_s1: T_M2_mpyd<0b01, 0, 1, 0>; 3053 def M2_mpyd_ll_s1: T_M2_mpyd<0b00, 0, 1, 0>; 3054 3055 def M2_mpyd_rnd_hh_s0: T_M2_mpyd<0b11, 1, 0, 0>; 3056 def M2_mpyd_rnd_hl_s0: T_M2_mpyd<0b10, 1, 0, 0>; 3057 def M2_mpyd_rnd_lh_s0: T_M2_mpyd<0b01, 1, 0, 0>; 3058 def M2_mpyd_rnd_ll_s0: T_M2_mpyd<0b00, 1, 0, 0>; 3059 3060 def M2_mpyd_rnd_hh_s1: T_M2_mpyd<0b11, 1, 1, 0>; 3061 def M2_mpyd_rnd_hl_s1: T_M2_mpyd<0b10, 1, 1, 0>; 3062 def M2_mpyd_rnd_lh_s1: T_M2_mpyd<0b01, 1, 1, 0>; 3063 def M2_mpyd_rnd_ll_s1: T_M2_mpyd<0b00, 1, 1, 0>; 3064 3065 //Rdd=mpyu(Rs.[HL],Rt.[HL])[:<<1] 3066 def M2_mpyud_hh_s0: T_M2_mpyd<0b11, 0, 0, 1>; 3067 def M2_mpyud_hl_s0: T_M2_mpyd<0b10, 0, 0, 1>; 3068 def M2_mpyud_lh_s0: T_M2_mpyd<0b01, 0, 0, 1>; 3069 def M2_mpyud_ll_s0: T_M2_mpyd<0b00, 0, 0, 1>; 3070 3071 def M2_mpyud_hh_s1: T_M2_mpyd<0b11, 0, 1, 1>; 3072 def M2_mpyud_hl_s1: T_M2_mpyd<0b10, 0, 1, 1>; 3073 def M2_mpyud_lh_s1: T_M2_mpyd<0b01, 0, 1, 1>; 3074 def M2_mpyud_ll_s1: T_M2_mpyd<0b00, 0, 1, 1>; 3075 3076 //===----------------------------------------------------------------------===// 3077 // Template Class for xtype mpy: 3078 // Vector multiply 3079 // Complex multiply 3080 // multiply 32X32 and use full result 3081 //===----------------------------------------------------------------------===// 3082 let hasSideEffects = 0 in 3083 class T_XTYPE_mpy64 <string mnemonic, bits<3> MajOp, bits<3> MinOp, 3084 bit isSat, bit hasShift, bit isConj> 3085 : MInst <(outs DoubleRegs:$Rdd), 3086 (ins IntRegs:$Rs, IntRegs:$Rt), 3087 "$Rdd = "#mnemonic#"($Rs, $Rt"#!if(isConj,"*)",")") 3088 #!if(hasShift,":<<1","") 3089 #!if(isSat,":sat",""), 3090 [] > { 3091 bits<5> Rdd; 3092 bits<5> Rs; 3093 bits<5> Rt; 3094 3095 let IClass = 0b1110; 3096 3097 let Inst{27-24} = 0b0101; 3098 let Inst{23-21} = MajOp; 3099 let Inst{20-16} = Rs; 3100 let Inst{12-8} = Rt; 3101 let Inst{7-5} = MinOp; 3102 let Inst{4-0} = Rdd; 3103 } 3104 3105 //===----------------------------------------------------------------------===// 3106 // Template Class for xtype mpy with accumulation into 64-bit: 3107 // Vector multiply 3108 // Complex multiply 3109 // multiply 32X32 and use full result 3110 //===----------------------------------------------------------------------===// 3111 class T_XTYPE_mpy64_acc <string op1, string op2, bits<3> MajOp, bits<3> MinOp, 3112 bit isSat, bit hasShift, bit isConj> 3113 : MInst <(outs DoubleRegs:$Rxx), 3114 (ins DoubleRegs:$dst2, IntRegs:$Rs, IntRegs:$Rt), 3115 "$Rxx "#op2#"= "#op1#"($Rs, $Rt"#!if(isConj,"*)",")") 3116 #!if(hasShift,":<<1","") 3117 #!if(isSat,":sat",""), 3118 3119 [] , "$dst2 = $Rxx" > { 3120 bits<5> Rxx; 3121 bits<5> Rs; 3122 bits<5> Rt; 3123 3124 let IClass = 0b1110; 3125 3126 let Inst{27-24} = 0b0111; 3127 let Inst{23-21} = MajOp; 3128 let Inst{20-16} = Rs; 3129 let Inst{12-8} = Rt; 3130 let Inst{7-5} = MinOp; 3131 let Inst{4-0} = Rxx; 3132 } 3133 3134 // MPY - Multiply and use full result 3135 // Rdd = mpy[u](Rs,Rt) 3136 def M2_dpmpyss_s0 : T_XTYPE_mpy64 < "mpy", 0b000, 0b000, 0, 0, 0>; 3137 def M2_dpmpyuu_s0 : T_XTYPE_mpy64 < "mpyu", 0b010, 0b000, 0, 0, 0>; 3138 3139 // Rxx[+-]= mpy[u](Rs,Rt) 3140 def M2_dpmpyss_acc_s0 : T_XTYPE_mpy64_acc < "mpy", "+", 0b000, 0b000, 0, 0, 0>; 3141 def M2_dpmpyss_nac_s0 : T_XTYPE_mpy64_acc < "mpy", "-", 0b001, 0b000, 0, 0, 0>; 3142 def M2_dpmpyuu_acc_s0 : T_XTYPE_mpy64_acc < "mpyu", "+", 0b010, 0b000, 0, 0, 0>; 3143 def M2_dpmpyuu_nac_s0 : T_XTYPE_mpy64_acc < "mpyu", "-", 0b011, 0b000, 0, 0, 0>; 3144 3145 // Complex multiply real or imaginary 3146 // Rxx=cmpy[ir](Rs,Rt) 3147 def M2_cmpyi_s0 : T_XTYPE_mpy64 < "cmpyi", 0b000, 0b001, 0, 0, 0>; 3148 def M2_cmpyr_s0 : T_XTYPE_mpy64 < "cmpyr", 0b000, 0b010, 0, 0, 0>; 3149 3150 // Rxx+=cmpy[ir](Rs,Rt) 3151 def M2_cmaci_s0 : T_XTYPE_mpy64_acc < "cmpyi", "+", 0b000, 0b001, 0, 0, 0>; 3152 def M2_cmacr_s0 : T_XTYPE_mpy64_acc < "cmpyr", "+", 0b000, 0b010, 0, 0, 0>; 3153 3154 // Complex multiply 3155 // Rdd=cmpy(Rs,Rt)[:<<]:sat 3156 def M2_cmpys_s0 : T_XTYPE_mpy64 < "cmpy", 0b000, 0b110, 1, 0, 0>; 3157 def M2_cmpys_s1 : T_XTYPE_mpy64 < "cmpy", 0b100, 0b110, 1, 1, 0>; 3158 3159 // Rdd=cmpy(Rs,Rt*)[:<<]:sat 3160 def M2_cmpysc_s0 : T_XTYPE_mpy64 < "cmpy", 0b010, 0b110, 1, 0, 1>; 3161 def M2_cmpysc_s1 : T_XTYPE_mpy64 < "cmpy", 0b110, 0b110, 1, 1, 1>; 3162 3163 // Rxx[-+]=cmpy(Rs,Rt)[:<<1]:sat 3164 def M2_cmacs_s0 : T_XTYPE_mpy64_acc < "cmpy", "+", 0b000, 0b110, 1, 0, 0>; 3165 def M2_cnacs_s0 : T_XTYPE_mpy64_acc < "cmpy", "-", 0b000, 0b111, 1, 0, 0>; 3166 def M2_cmacs_s1 : T_XTYPE_mpy64_acc < "cmpy", "+", 0b100, 0b110, 1, 1, 0>; 3167 def M2_cnacs_s1 : T_XTYPE_mpy64_acc < "cmpy", "-", 0b100, 0b111, 1, 1, 0>; 3168 3169 // Rxx[-+]=cmpy(Rs,Rt*)[:<<1]:sat 3170 def M2_cmacsc_s0 : T_XTYPE_mpy64_acc < "cmpy", "+", 0b010, 0b110, 1, 0, 1>; 3171 def M2_cnacsc_s0 : T_XTYPE_mpy64_acc < "cmpy", "-", 0b010, 0b111, 1, 0, 1>; 3172 def M2_cmacsc_s1 : T_XTYPE_mpy64_acc < "cmpy", "+", 0b110, 0b110, 1, 1, 1>; 3173 def M2_cnacsc_s1 : T_XTYPE_mpy64_acc < "cmpy", "-", 0b110, 0b111, 1, 1, 1>; 3174 3175 // Vector multiply halfwords 3176 // Rdd=vmpyh(Rs,Rt)[:<<]:sat 3177 //let Defs = [USR_OVF] in { 3178 def M2_vmpy2s_s1 : T_XTYPE_mpy64 < "vmpyh", 0b100, 0b101, 1, 1, 0>; 3179 def M2_vmpy2s_s0 : T_XTYPE_mpy64 < "vmpyh", 0b000, 0b101, 1, 0, 0>; 3180 //} 3181 3182 // Rxx+=vmpyh(Rs,Rt)[:<<1][:sat] 3183 def M2_vmac2 : T_XTYPE_mpy64_acc < "vmpyh", "+", 0b001, 0b001, 0, 0, 0>; 3184 def M2_vmac2s_s1 : T_XTYPE_mpy64_acc < "vmpyh", "+", 0b100, 0b101, 1, 1, 0>; 3185 def M2_vmac2s_s0 : T_XTYPE_mpy64_acc < "vmpyh", "+", 0b000, 0b101, 1, 0, 0>; 3186 3187 def: Pat<(i64 (mul (i64 (anyext (i32 IntRegs:$src1))), 3188 (i64 (anyext (i32 IntRegs:$src2))))), 3189 (M2_dpmpyuu_s0 IntRegs:$src1, IntRegs:$src2)>; 3190 3191 def: Pat<(i64 (mul (i64 (sext (i32 IntRegs:$src1))), 3192 (i64 (sext (i32 IntRegs:$src2))))), 3193 (M2_dpmpyss_s0 IntRegs:$src1, IntRegs:$src2)>; 3194 3195 def: Pat<(i64 (mul (is_sext_i32:$src1), 3196 (is_sext_i32:$src2))), 3197 (M2_dpmpyss_s0 (LoReg DoubleRegs:$src1), (LoReg DoubleRegs:$src2))>; 3198 3199 // Multiply and accumulate, use full result. 3200 // Rxx[+-]=mpy(Rs,Rt) 3201 3202 def: Pat<(i64 (add (i64 DoubleRegs:$src1), 3203 (mul (i64 (sext (i32 IntRegs:$src2))), 3204 (i64 (sext (i32 IntRegs:$src3)))))), 3205 (M2_dpmpyss_acc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>; 3206 3207 def: Pat<(i64 (sub (i64 DoubleRegs:$src1), 3208 (mul (i64 (sext (i32 IntRegs:$src2))), 3209 (i64 (sext (i32 IntRegs:$src3)))))), 3210 (M2_dpmpyss_nac_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>; 3211 3212 def: Pat<(i64 (add (i64 DoubleRegs:$src1), 3213 (mul (i64 (anyext (i32 IntRegs:$src2))), 3214 (i64 (anyext (i32 IntRegs:$src3)))))), 3215 (M2_dpmpyuu_acc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>; 3216 3217 def: Pat<(i64 (add (i64 DoubleRegs:$src1), 3218 (mul (i64 (zext (i32 IntRegs:$src2))), 3219 (i64 (zext (i32 IntRegs:$src3)))))), 3220 (M2_dpmpyuu_acc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>; 3221 3222 def: Pat<(i64 (sub (i64 DoubleRegs:$src1), 3223 (mul (i64 (anyext (i32 IntRegs:$src2))), 3224 (i64 (anyext (i32 IntRegs:$src3)))))), 3225 (M2_dpmpyuu_nac_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>; 3226 3227 def: Pat<(i64 (sub (i64 DoubleRegs:$src1), 3228 (mul (i64 (zext (i32 IntRegs:$src2))), 3229 (i64 (zext (i32 IntRegs:$src3)))))), 3230 (M2_dpmpyuu_nac_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>; 3231 3232 //===----------------------------------------------------------------------===// 3233 // MTYPE/MPYH - 3234 //===----------------------------------------------------------------------===// 3235 3236 //===----------------------------------------------------------------------===// 3237 // MTYPE/MPYS + 3238 //===----------------------------------------------------------------------===// 3239 //===----------------------------------------------------------------------===// 3240 // MTYPE/MPYS - 3241 //===----------------------------------------------------------------------===// 3242 3243 //===----------------------------------------------------------------------===// 3244 // MTYPE/VB + 3245 //===----------------------------------------------------------------------===// 3246 //===----------------------------------------------------------------------===// 3247 // MTYPE/VB - 3248 //===----------------------------------------------------------------------===// 3249 3250 //===----------------------------------------------------------------------===// 3251 // MTYPE/VH + 3252 //===----------------------------------------------------------------------===// 3253 //===----------------------------------------------------------------------===// 3254 // MTYPE/VH - 3255 //===----------------------------------------------------------------------===// 3256 3257 //===----------------------------------------------------------------------===// 3258 // ST + 3259 //===----------------------------------------------------------------------===// 3260 /// 3261 // Store doubleword. 3262 //===----------------------------------------------------------------------===// 3263 // Template class for non-predicated post increment stores with immediate offset 3264 //===----------------------------------------------------------------------===// 3265 let isPredicable = 1, hasSideEffects = 0, addrMode = PostInc in 3266 class T_store_pi <string mnemonic, RegisterClass RC, Operand ImmOp, 3267 bits<4> MajOp, bit isHalf > 3268 : STInst <(outs IntRegs:$_dst_), 3269 (ins IntRegs:$src1, ImmOp:$offset, RC:$src2), 3270 mnemonic#"($src1++#$offset) = $src2"#!if(isHalf, ".h", ""), 3271 [], "$src1 = $_dst_" >, 3272 AddrModeRel { 3273 bits<5> src1; 3274 bits<5> src2; 3275 bits<7> offset; 3276 bits<4> offsetBits; 3277 3278 string ImmOpStr = !cast<string>(ImmOp); 3279 let offsetBits = !if (!eq(ImmOpStr, "s4_3Imm"), offset{6-3}, 3280 !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2}, 3281 !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1}, 3282 /* s4_0Imm */ offset{3-0}))); 3283 // Store upper-half and store doubleword cannot be NV. 3284 let isNVStorable = !if (!eq(ImmOpStr, "s4_3Imm"), 0, !if(isHalf,0,1)); 3285 3286 let IClass = 0b1010; 3287 3288 let Inst{27-25} = 0b101; 3289 let Inst{24-21} = MajOp; 3290 let Inst{20-16} = src1; 3291 let Inst{13} = 0b0; 3292 let Inst{12-8} = src2; 3293 let Inst{7} = 0b0; 3294 let Inst{6-3} = offsetBits; 3295 let Inst{1} = 0b0; 3296 } 3297 3298 //===----------------------------------------------------------------------===// 3299 // Template class for predicated post increment stores with immediate offset 3300 //===----------------------------------------------------------------------===// 3301 let isPredicated = 1, hasSideEffects = 0, addrMode = PostInc in 3302 class T_pstore_pi <string mnemonic, RegisterClass RC, Operand ImmOp, 3303 bits<4> MajOp, bit isHalf, bit isPredNot, bit isPredNew> 3304 : STInst <(outs IntRegs:$_dst_), 3305 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset, RC:$src3), 3306 !if(isPredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ", 3307 ") ")#mnemonic#"($src2++#$offset) = $src3"#!if(isHalf, ".h", ""), 3308 [], "$src2 = $_dst_" >, 3309 AddrModeRel { 3310 bits<2> src1; 3311 bits<5> src2; 3312 bits<7> offset; 3313 bits<5> src3; 3314 bits<4> offsetBits; 3315 3316 string ImmOpStr = !cast<string>(ImmOp); 3317 let offsetBits = !if (!eq(ImmOpStr, "s4_3Imm"), offset{6-3}, 3318 !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2}, 3319 !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1}, 3320 /* s4_0Imm */ offset{3-0}))); 3321 3322 // Store upper-half and store doubleword cannot be NV. 3323 let isNVStorable = !if (!eq(ImmOpStr, "s4_3Imm"), 0, !if(isHalf,0,1)); 3324 let isPredicatedNew = isPredNew; 3325 let isPredicatedFalse = isPredNot; 3326 3327 let IClass = 0b1010; 3328 3329 let Inst{27-25} = 0b101; 3330 let Inst{24-21} = MajOp; 3331 let Inst{20-16} = src2; 3332 let Inst{13} = 0b1; 3333 let Inst{12-8} = src3; 3334 let Inst{7} = isPredNew; 3335 let Inst{6-3} = offsetBits; 3336 let Inst{2} = isPredNot; 3337 let Inst{1-0} = src1; 3338 } 3339 3340 multiclass ST_PostInc<string mnemonic, string BaseOp, RegisterClass RC, 3341 Operand ImmOp, bits<4> MajOp, bit isHalf = 0 > { 3342 3343 let BaseOpcode = "POST_"#BaseOp in { 3344 def S2_#NAME#_pi : T_store_pi <mnemonic, RC, ImmOp, MajOp, isHalf>; 3345 3346 // Predicated 3347 def S2_p#NAME#t_pi : T_pstore_pi <mnemonic, RC, ImmOp, MajOp, isHalf, 0, 0>; 3348 def S2_p#NAME#f_pi : T_pstore_pi <mnemonic, RC, ImmOp, MajOp, isHalf, 1, 0>; 3349 3350 // Predicated new 3351 def S2_p#NAME#tnew_pi : T_pstore_pi <mnemonic, RC, ImmOp, MajOp, 3352 isHalf, 0, 1>; 3353 def S2_p#NAME#fnew_pi : T_pstore_pi <mnemonic, RC, ImmOp, MajOp, 3354 isHalf, 1, 1>; 3355 } 3356 } 3357 3358 let accessSize = ByteAccess in 3359 defm storerb: ST_PostInc <"memb", "STrib", IntRegs, s4_0Imm, 0b1000>; 3360 3361 let accessSize = HalfWordAccess in 3362 defm storerh: ST_PostInc <"memh", "STrih", IntRegs, s4_1Imm, 0b1010>; 3363 3364 let accessSize = WordAccess in 3365 defm storeri: ST_PostInc <"memw", "STriw", IntRegs, s4_2Imm, 0b1100>; 3366 3367 let accessSize = DoubleWordAccess in 3368 defm storerd: ST_PostInc <"memd", "STrid", DoubleRegs, s4_3Imm, 0b1110>; 3369 3370 let accessSize = HalfWordAccess, isNVStorable = 0 in 3371 defm storerf: ST_PostInc <"memh", "STrih_H", IntRegs, s4_1Imm, 0b1011, 1>; 3372 3373 class Storepi_pat<PatFrag Store, PatFrag Value, PatFrag Offset, 3374 InstHexagon MI> 3375 : Pat<(Store Value:$src1, I32:$src2, Offset:$offset), 3376 (MI I32:$src2, imm:$offset, Value:$src1)>; 3377 3378 def: Storepi_pat<post_truncsti8, I32, s4_0ImmPred, S2_storerb_pi>; 3379 def: Storepi_pat<post_truncsti16, I32, s4_1ImmPred, S2_storerh_pi>; 3380 def: Storepi_pat<post_store, I32, s4_2ImmPred, S2_storeri_pi>; 3381 def: Storepi_pat<post_store, I64, s4_3ImmPred, S2_storerd_pi>; 3382 3383 //===----------------------------------------------------------------------===// 3384 // Template class for post increment stores with register offset. 3385 //===----------------------------------------------------------------------===// 3386 class T_store_pr <string mnemonic, RegisterClass RC, bits<3> MajOp, 3387 MemAccessSize AccessSz, bit isHalf = 0> 3388 : STInst <(outs IntRegs:$_dst_), 3389 (ins IntRegs:$src1, ModRegs:$src2, RC:$src3), 3390 mnemonic#"($src1++$src2) = $src3"#!if(isHalf, ".h", ""), 3391 [], "$src1 = $_dst_" > { 3392 bits<5> src1; 3393 bits<1> src2; 3394 bits<5> src3; 3395 let accessSize = AccessSz; 3396 3397 // Store upper-half and store doubleword cannot be NV. 3398 let isNVStorable = !if(!eq(mnemonic,"memd"), 0, !if(isHalf,0,1)); 3399 3400 let IClass = 0b1010; 3401 3402 let Inst{27-24} = 0b1101; 3403 let Inst{23-21} = MajOp; 3404 let Inst{20-16} = src1; 3405 let Inst{13} = src2; 3406 let Inst{12-8} = src3; 3407 let Inst{7} = 0b0; 3408 } 3409 3410 def S2_storerb_pr : T_store_pr<"memb", IntRegs, 0b000, ByteAccess>; 3411 def S2_storerh_pr : T_store_pr<"memh", IntRegs, 0b010, HalfWordAccess>; 3412 def S2_storeri_pr : T_store_pr<"memw", IntRegs, 0b100, WordAccess>; 3413 def S2_storerd_pr : T_store_pr<"memd", DoubleRegs, 0b110, DoubleWordAccess>; 3414 def S2_storerf_pr : T_store_pr<"memh", IntRegs, 0b011, HalfWordAccess, 1>; 3415 3416 let opExtendable = 1, isExtentSigned = 1, isPredicable = 1 in 3417 class T_store_io <string mnemonic, RegisterClass RC, Operand ImmOp, 3418 bits<3> MajOp, bit isH = 0> 3419 : STInst <(outs), 3420 (ins IntRegs:$src1, ImmOp:$src2, RC:$src3), 3421 mnemonic#"($src1+#$src2) = $src3"#!if(isH,".h","")>, 3422 AddrModeRel, ImmRegRel { 3423 bits<5> src1; 3424 bits<14> src2; // Actual address offset 3425 bits<5> src3; 3426 bits<11> offsetBits; // Represents offset encoding 3427 3428 string ImmOpStr = !cast<string>(ImmOp); 3429 3430 let opExtentBits = !if (!eq(ImmOpStr, "s11_3Ext"), 14, 3431 !if (!eq(ImmOpStr, "s11_2Ext"), 13, 3432 !if (!eq(ImmOpStr, "s11_1Ext"), 12, 3433 /* s11_0Ext */ 11))); 3434 let offsetBits = !if (!eq(ImmOpStr, "s11_3Ext"), src2{13-3}, 3435 !if (!eq(ImmOpStr, "s11_2Ext"), src2{12-2}, 3436 !if (!eq(ImmOpStr, "s11_1Ext"), src2{11-1}, 3437 /* s11_0Ext */ src2{10-0}))); 3438 // Store upper-half and store doubleword cannot be NV. 3439 let isNVStorable = !if (!eq(mnemonic, "memd"), 0, !if(isH,0,1)); 3440 let IClass = 0b1010; 3441 3442 let Inst{27} = 0b0; 3443 let Inst{26-25} = offsetBits{10-9}; 3444 let Inst{24} = 0b1; 3445 let Inst{23-21} = MajOp; 3446 let Inst{20-16} = src1; 3447 let Inst{13} = offsetBits{8}; 3448 let Inst{12-8} = src3; 3449 let Inst{7-0} = offsetBits{7-0}; 3450 } 3451 3452 let opExtendable = 2, isPredicated = 1 in 3453 class T_pstore_io <string mnemonic, RegisterClass RC, Operand ImmOp, 3454 bits<3>MajOp, bit PredNot, bit isPredNew, bit isH = 0> 3455 : STInst <(outs), 3456 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$src3, RC:$src4), 3457 !if(PredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ", 3458 ") ")#mnemonic#"($src2+#$src3) = $src4"#!if(isH,".h",""), 3459 [],"",V2LDST_tc_st_SLOT01 >, 3460 AddrModeRel, ImmRegRel { 3461 bits<2> src1; 3462 bits<5> src2; 3463 bits<9> src3; // Actual address offset 3464 bits<5> src4; 3465 bits<6> offsetBits; // Represents offset encoding 3466 3467 let isPredicatedNew = isPredNew; 3468 let isPredicatedFalse = PredNot; 3469 3470 string ImmOpStr = !cast<string>(ImmOp); 3471 let opExtentBits = !if (!eq(ImmOpStr, "u6_3Ext"), 9, 3472 !if (!eq(ImmOpStr, "u6_2Ext"), 8, 3473 !if (!eq(ImmOpStr, "u6_1Ext"), 7, 3474 /* u6_0Ext */ 6))); 3475 let offsetBits = !if (!eq(ImmOpStr, "u6_3Ext"), src3{8-3}, 3476 !if (!eq(ImmOpStr, "u6_2Ext"), src3{7-2}, 3477 !if (!eq(ImmOpStr, "u6_1Ext"), src3{6-1}, 3478 /* u6_0Ext */ src3{5-0}))); 3479 // Store upper-half and store doubleword cannot be NV. 3480 let isNVStorable = !if (!eq(mnemonic, "memd"), 0, !if(isH,0,1)); 3481 3482 let IClass = 0b0100; 3483 3484 let Inst{27} = 0b0; 3485 let Inst{26} = PredNot; 3486 let Inst{25} = isPredNew; 3487 let Inst{24} = 0b0; 3488 let Inst{23-21} = MajOp; 3489 let Inst{20-16} = src2; 3490 let Inst{13} = offsetBits{5}; 3491 let Inst{12-8} = src4; 3492 let Inst{7-3} = offsetBits{4-0}; 3493 let Inst{1-0} = src1; 3494 } 3495 3496 let isExtendable = 1, hasSideEffects = 0 in 3497 multiclass ST_Idxd<string mnemonic, string CextOp, RegisterClass RC, 3498 Operand ImmOp, Operand predImmOp, bits<3> MajOp, bit isH = 0> { 3499 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in { 3500 def S2_#NAME#_io : T_store_io <mnemonic, RC, ImmOp, MajOp, isH>; 3501 3502 // Predicated 3503 def S2_p#NAME#t_io : T_pstore_io<mnemonic, RC, predImmOp, MajOp, 0, 0, isH>; 3504 def S2_p#NAME#f_io : T_pstore_io<mnemonic, RC, predImmOp, MajOp, 1, 0, isH>; 3505 3506 // Predicated new 3507 def S4_p#NAME#tnew_io : T_pstore_io <mnemonic, RC, predImmOp, 3508 MajOp, 0, 1, isH>; 3509 def S4_p#NAME#fnew_io : T_pstore_io <mnemonic, RC, predImmOp, 3510 MajOp, 1, 1, isH>; 3511 } 3512 } 3513 3514 let addrMode = BaseImmOffset, InputType = "imm" in { 3515 let accessSize = ByteAccess in 3516 defm storerb: ST_Idxd < "memb", "STrib", IntRegs, s11_0Ext, u6_0Ext, 0b000>; 3517 3518 let accessSize = HalfWordAccess, opExtentAlign = 1 in 3519 defm storerh: ST_Idxd < "memh", "STrih", IntRegs, s11_1Ext, u6_1Ext, 0b010>; 3520 3521 let accessSize = WordAccess, opExtentAlign = 2 in 3522 defm storeri: ST_Idxd < "memw", "STriw", IntRegs, s11_2Ext, u6_2Ext, 0b100>; 3523 3524 let accessSize = DoubleWordAccess, isNVStorable = 0, opExtentAlign = 3 in 3525 defm storerd: ST_Idxd < "memd", "STrid", DoubleRegs, s11_3Ext, 3526 u6_3Ext, 0b110>; 3527 3528 let accessSize = HalfWordAccess, opExtentAlign = 1 in 3529 defm storerf: ST_Idxd < "memh", "STrif", IntRegs, s11_1Ext, 3530 u6_1Ext, 0b011, 1>; 3531 } 3532 3533 // Patterns for generating stores, where the address takes different forms: 3534 // - frameindex, 3535 // - frameindex + offset, 3536 // - base + offset, 3537 // - simple (base address without offset). 3538 // These would usually be used together (via Storex_pat defined below), but 3539 // in some cases one may want to apply different properties (such as 3540 // AddedComplexity) to the individual patterns. 3541 class Storex_fi_pat<PatFrag Store, PatFrag Value, InstHexagon MI> 3542 : Pat<(Store Value:$Rs, AddrFI:$fi), (MI AddrFI:$fi, 0, Value:$Rs)>; 3543 class Storex_fi_add_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred, 3544 InstHexagon MI> 3545 : Pat<(Store Value:$Rs, (add (i32 AddrFI:$fi), ImmPred:$Off)), 3546 (MI AddrFI:$fi, imm:$Off, Value:$Rs)>; 3547 class Storex_add_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred, 3548 InstHexagon MI> 3549 : Pat<(Store Value:$Rt, (add (i32 IntRegs:$Rs), ImmPred:$Off)), 3550 (MI IntRegs:$Rs, imm:$Off, Value:$Rt)>; 3551 class Storex_simple_pat<PatFrag Store, PatFrag Value, InstHexagon MI> 3552 : Pat<(Store Value:$Rt, (i32 IntRegs:$Rs)), 3553 (MI IntRegs:$Rs, 0, Value:$Rt)>; 3554 3555 // Patterns for generating stores, where the address takes different forms, 3556 // and where the value being stored is transformed through the value modifier 3557 // ValueMod. The address forms are same as above. 3558 class Storexm_fi_pat<PatFrag Store, PatFrag Value, PatFrag ValueMod, 3559 InstHexagon MI> 3560 : Pat<(Store Value:$Rs, AddrFI:$fi), 3561 (MI AddrFI:$fi, 0, (ValueMod Value:$Rs))>; 3562 class Storexm_fi_add_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred, 3563 PatFrag ValueMod, InstHexagon MI> 3564 : Pat<(Store Value:$Rs, (add (i32 AddrFI:$fi), ImmPred:$Off)), 3565 (MI AddrFI:$fi, imm:$Off, (ValueMod Value:$Rs))>; 3566 class Storexm_add_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred, 3567 PatFrag ValueMod, InstHexagon MI> 3568 : Pat<(Store Value:$Rt, (add (i32 IntRegs:$Rs), ImmPred:$Off)), 3569 (MI IntRegs:$Rs, imm:$Off, (ValueMod Value:$Rt))>; 3570 class Storexm_simple_pat<PatFrag Store, PatFrag Value, PatFrag ValueMod, 3571 InstHexagon MI> 3572 : Pat<(Store Value:$Rt, (i32 IntRegs:$Rs)), 3573 (MI IntRegs:$Rs, 0, (ValueMod Value:$Rt))>; 3574 3575 multiclass Storex_pat<PatFrag Store, PatFrag Value, PatLeaf ImmPred, 3576 InstHexagon MI> { 3577 def: Storex_fi_pat <Store, Value, MI>; 3578 def: Storex_fi_add_pat <Store, Value, ImmPred, MI>; 3579 def: Storex_add_pat <Store, Value, ImmPred, MI>; 3580 } 3581 3582 multiclass Storexm_pat<PatFrag Store, PatFrag Value, PatLeaf ImmPred, 3583 PatFrag ValueMod, InstHexagon MI> { 3584 def: Storexm_fi_pat <Store, Value, ValueMod, MI>; 3585 def: Storexm_fi_add_pat <Store, Value, ImmPred, ValueMod, MI>; 3586 def: Storexm_add_pat <Store, Value, ImmPred, ValueMod, MI>; 3587 } 3588 3589 // Regular stores in the DAG have two operands: value and address. 3590 // Atomic stores also have two, but they are reversed: address, value. 3591 // To use atomic stores with the patterns, they need to have their operands 3592 // swapped. This relies on the knowledge that the F.Fragment uses names 3593 // "ptr" and "val". 3594 class SwapSt<PatFrag F> 3595 : PatFrag<(ops node:$val, node:$ptr), F.Fragment>; 3596 3597 let AddedComplexity = 20 in { 3598 defm: Storex_pat<truncstorei8, I32, s32_0ImmPred, S2_storerb_io>; 3599 defm: Storex_pat<truncstorei16, I32, s31_1ImmPred, S2_storerh_io>; 3600 defm: Storex_pat<store, I32, s30_2ImmPred, S2_storeri_io>; 3601 defm: Storex_pat<store, I64, s29_3ImmPred, S2_storerd_io>; 3602 3603 defm: Storex_pat<SwapSt<atomic_store_8>, I32, s32_0ImmPred, S2_storerb_io>; 3604 defm: Storex_pat<SwapSt<atomic_store_16>, I32, s31_1ImmPred, S2_storerh_io>; 3605 defm: Storex_pat<SwapSt<atomic_store_32>, I32, s30_2ImmPred, S2_storeri_io>; 3606 defm: Storex_pat<SwapSt<atomic_store_64>, I64, s29_3ImmPred, S2_storerd_io>; 3607 } 3608 3609 // Simple patterns should be tried with the least priority. 3610 def: Storex_simple_pat<truncstorei8, I32, S2_storerb_io>; 3611 def: Storex_simple_pat<truncstorei16, I32, S2_storerh_io>; 3612 def: Storex_simple_pat<store, I32, S2_storeri_io>; 3613 def: Storex_simple_pat<store, I64, S2_storerd_io>; 3614 3615 def: Storex_simple_pat<SwapSt<atomic_store_8>, I32, S2_storerb_io>; 3616 def: Storex_simple_pat<SwapSt<atomic_store_16>, I32, S2_storerh_io>; 3617 def: Storex_simple_pat<SwapSt<atomic_store_32>, I32, S2_storeri_io>; 3618 def: Storex_simple_pat<SwapSt<atomic_store_64>, I64, S2_storerd_io>; 3619 3620 let AddedComplexity = 20 in { 3621 defm: Storexm_pat<truncstorei8, I64, s32_0ImmPred, LoReg, S2_storerb_io>; 3622 defm: Storexm_pat<truncstorei16, I64, s31_1ImmPred, LoReg, S2_storerh_io>; 3623 defm: Storexm_pat<truncstorei32, I64, s30_2ImmPred, LoReg, S2_storeri_io>; 3624 } 3625 3626 def: Storexm_simple_pat<truncstorei8, I64, LoReg, S2_storerb_io>; 3627 def: Storexm_simple_pat<truncstorei16, I64, LoReg, S2_storerh_io>; 3628 def: Storexm_simple_pat<truncstorei32, I64, LoReg, S2_storeri_io>; 3629 3630 // Store predicate. 3631 let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 13, 3632 isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in 3633 def STriw_pred : STInst<(outs), 3634 (ins IntRegs:$addr, s11_2Ext:$off, PredRegs:$src1), 3635 ".error \"should not emit\"", []>; 3636 // Store modifier. 3637 let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 13, 3638 isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in 3639 def STriw_mod : STInst<(outs), 3640 (ins IntRegs:$addr, s11_2Ext:$off, ModRegs:$src1), 3641 ".error \"should not emit\"", []>; 3642 3643 // S2_allocframe: Allocate stack frame. 3644 let Defs = [R29, R30], Uses = [R29, R31, R30], 3645 hasSideEffects = 0, accessSize = DoubleWordAccess in 3646 def S2_allocframe: ST0Inst < 3647 (outs), (ins u11_3Imm:$u11_3), 3648 "allocframe(#$u11_3)" > { 3649 bits<14> u11_3; 3650 3651 let IClass = 0b1010; 3652 let Inst{27-16} = 0b000010011101; 3653 let Inst{13-11} = 0b000; 3654 let Inst{10-0} = u11_3{13-3}; 3655 } 3656 3657 // S2_storer[bhwdf]_pci: Store byte/half/word/double. 3658 // S2_storer[bhwdf]_pci -> S2_storerbnew_pci 3659 let Uses = [CS] in 3660 class T_store_pci <string mnemonic, RegisterClass RC, 3661 Operand Imm, bits<4>MajOp, 3662 MemAccessSize AlignSize, string RegSrc = "Rt"> 3663 : STInst <(outs IntRegs:$_dst_), 3664 (ins IntRegs:$Rz, Imm:$offset, ModRegs:$Mu, RC:$Rt), 3665 #mnemonic#"($Rz ++ #$offset:circ($Mu)) = $"#RegSrc#"", 3666 [] , 3667 "$Rz = $_dst_" > { 3668 bits<5> Rz; 3669 bits<7> offset; 3670 bits<1> Mu; 3671 bits<5> Rt; 3672 let accessSize = AlignSize; 3673 let isNVStorable = !if(!eq(mnemonic,"memd"), 0, 3674 !if(!eq(RegSrc,"Rt.h"), 0, 1)); 3675 3676 let IClass = 0b1010; 3677 let Inst{27-25} = 0b100; 3678 let Inst{24-21} = MajOp; 3679 let Inst{20-16} = Rz; 3680 let Inst{13} = Mu; 3681 let Inst{12-8} = Rt; 3682 let Inst{7} = 0b0; 3683 let Inst{6-3} = 3684 !if (!eq(!cast<string>(AlignSize), "DoubleWordAccess"), offset{6-3}, 3685 !if (!eq(!cast<string>(AlignSize), "WordAccess"), offset{5-2}, 3686 !if (!eq(!cast<string>(AlignSize), "HalfWordAccess"), offset{4-1}, 3687 /* ByteAccess */ offset{3-0}))); 3688 let Inst{1} = 0b0; 3689 } 3690 3691 def S2_storerb_pci : T_store_pci<"memb", IntRegs, s4_0Imm, 0b1000, 3692 ByteAccess>; 3693 def S2_storerh_pci : T_store_pci<"memh", IntRegs, s4_1Imm, 0b1010, 3694 HalfWordAccess>; 3695 def S2_storerf_pci : T_store_pci<"memh", IntRegs, s4_1Imm, 0b1011, 3696 HalfWordAccess, "Rt.h">; 3697 def S2_storeri_pci : T_store_pci<"memw", IntRegs, s4_2Imm, 0b1100, 3698 WordAccess>; 3699 def S2_storerd_pci : T_store_pci<"memd", DoubleRegs, s4_3Imm, 0b1110, 3700 DoubleWordAccess>; 3701 3702 let Uses = [CS], isNewValue = 1, mayStore = 1, isNVStore = 1, opNewValue = 4 in 3703 class T_storenew_pci <string mnemonic, Operand Imm, 3704 bits<2>MajOp, MemAccessSize AlignSize> 3705 : NVInst < (outs IntRegs:$_dst_), 3706 (ins IntRegs:$Rz, Imm:$offset, ModRegs:$Mu, IntRegs:$Nt), 3707 #mnemonic#"($Rz ++ #$offset:circ($Mu)) = $Nt.new", 3708 [], 3709 "$Rz = $_dst_"> { 3710 bits<5> Rz; 3711 bits<6> offset; 3712 bits<1> Mu; 3713 bits<3> Nt; 3714 3715 let accessSize = AlignSize; 3716 3717 let IClass = 0b1010; 3718 let Inst{27-21} = 0b1001101; 3719 let Inst{20-16} = Rz; 3720 let Inst{13} = Mu; 3721 let Inst{12-11} = MajOp; 3722 let Inst{10-8} = Nt; 3723 let Inst{7} = 0b0; 3724 let Inst{6-3} = 3725 !if (!eq(!cast<string>(AlignSize), "WordAccess"), offset{5-2}, 3726 !if (!eq(!cast<string>(AlignSize), "HalfWordAccess"), offset{4-1}, 3727 /* ByteAccess */ offset{3-0})); 3728 let Inst{1} = 0b0; 3729 } 3730 3731 def S2_storerbnew_pci : T_storenew_pci <"memb", s4_0Imm, 0b00, ByteAccess>; 3732 def S2_storerhnew_pci : T_storenew_pci <"memh", s4_1Imm, 0b01, HalfWordAccess>; 3733 def S2_storerinew_pci : T_storenew_pci <"memw", s4_2Imm, 0b10, WordAccess>; 3734 3735 //===----------------------------------------------------------------------===// 3736 // Circular stores with auto-increment register 3737 //===----------------------------------------------------------------------===// 3738 let Uses = [CS] in 3739 class T_store_pcr <string mnemonic, RegisterClass RC, bits<4>MajOp, 3740 MemAccessSize AlignSize, string RegSrc = "Rt"> 3741 : STInst <(outs IntRegs:$_dst_), 3742 (ins IntRegs:$Rz, ModRegs:$Mu, RC:$Rt), 3743 #mnemonic#"($Rz ++ I:circ($Mu)) = $"#RegSrc#"", 3744 [], 3745 "$Rz = $_dst_" > { 3746 bits<5> Rz; 3747 bits<1> Mu; 3748 bits<5> Rt; 3749 3750 let accessSize = AlignSize; 3751 let isNVStorable = !if(!eq(mnemonic,"memd"), 0, 3752 !if(!eq(RegSrc,"Rt.h"), 0, 1)); 3753 3754 let IClass = 0b1010; 3755 let Inst{27-25} = 0b100; 3756 let Inst{24-21} = MajOp; 3757 let Inst{20-16} = Rz; 3758 let Inst{13} = Mu; 3759 let Inst{12-8} = Rt; 3760 let Inst{7} = 0b0; 3761 let Inst{1} = 0b1; 3762 } 3763 3764 def S2_storerb_pcr : T_store_pcr<"memb", IntRegs, 0b1000, ByteAccess>; 3765 def S2_storerh_pcr : T_store_pcr<"memh", IntRegs, 0b1010, HalfWordAccess>; 3766 def S2_storeri_pcr : T_store_pcr<"memw", IntRegs, 0b1100, WordAccess>; 3767 def S2_storerd_pcr : T_store_pcr<"memd", DoubleRegs, 0b1110, DoubleWordAccess>; 3768 def S2_storerf_pcr : T_store_pcr<"memh", IntRegs, 0b1011, 3769 HalfWordAccess, "Rt.h">; 3770 3771 //===----------------------------------------------------------------------===// 3772 // Circular .new stores with auto-increment register 3773 //===----------------------------------------------------------------------===// 3774 let Uses = [CS], isNewValue = 1, mayStore = 1, isNVStore = 1, opNewValue = 3 in 3775 class T_storenew_pcr <string mnemonic, bits<2>MajOp, 3776 MemAccessSize AlignSize> 3777 : NVInst <(outs IntRegs:$_dst_), 3778 (ins IntRegs:$Rz, ModRegs:$Mu, IntRegs:$Nt), 3779 #mnemonic#"($Rz ++ I:circ($Mu)) = $Nt.new" , 3780 [] , 3781 "$Rz = $_dst_"> { 3782 bits<5> Rz; 3783 bits<1> Mu; 3784 bits<3> Nt; 3785 3786 let accessSize = AlignSize; 3787 3788 let IClass = 0b1010; 3789 let Inst{27-21} = 0b1001101; 3790 let Inst{20-16} = Rz; 3791 let Inst{13} = Mu; 3792 let Inst{12-11} = MajOp; 3793 let Inst{10-8} = Nt; 3794 let Inst{7} = 0b0; 3795 let Inst{1} = 0b1; 3796 } 3797 3798 def S2_storerbnew_pcr : T_storenew_pcr <"memb", 0b00, ByteAccess>; 3799 def S2_storerhnew_pcr : T_storenew_pcr <"memh", 0b01, HalfWordAccess>; 3800 def S2_storerinew_pcr : T_storenew_pcr <"memw", 0b10, WordAccess>; 3801 3802 //===----------------------------------------------------------------------===// 3803 // Bit-reversed stores with auto-increment register 3804 //===----------------------------------------------------------------------===// 3805 let hasSideEffects = 0 in 3806 class T_store_pbr<string mnemonic, RegisterClass RC, 3807 MemAccessSize addrSize, bits<3> majOp, 3808 bit isHalf = 0> 3809 : STInst 3810 <(outs IntRegs:$_dst_), 3811 (ins IntRegs:$Rz, ModRegs:$Mu, RC:$src), 3812 #mnemonic#"($Rz ++ $Mu:brev) = $src"#!if (!eq(isHalf, 1), ".h", ""), 3813 [], "$Rz = $_dst_" > { 3814 3815 let accessSize = addrSize; 3816 3817 bits<5> Rz; 3818 bits<1> Mu; 3819 bits<5> src; 3820 3821 let IClass = 0b1010; 3822 3823 let Inst{27-24} = 0b1111; 3824 let Inst{23-21} = majOp; 3825 let Inst{7} = 0b0; 3826 let Inst{20-16} = Rz; 3827 let Inst{13} = Mu; 3828 let Inst{12-8} = src; 3829 } 3830 3831 let isNVStorable = 1 in { 3832 let BaseOpcode = "S2_storerb_pbr" in 3833 def S2_storerb_pbr : T_store_pbr<"memb", IntRegs, ByteAccess, 3834 0b000>, NewValueRel; 3835 let BaseOpcode = "S2_storerh_pbr" in 3836 def S2_storerh_pbr : T_store_pbr<"memh", IntRegs, HalfWordAccess, 3837 0b010>, NewValueRel; 3838 let BaseOpcode = "S2_storeri_pbr" in 3839 def S2_storeri_pbr : T_store_pbr<"memw", IntRegs, WordAccess, 3840 0b100>, NewValueRel; 3841 } 3842 3843 def S2_storerf_pbr : T_store_pbr<"memh", IntRegs, HalfWordAccess, 0b011, 1>; 3844 def S2_storerd_pbr : T_store_pbr<"memd", DoubleRegs, DoubleWordAccess, 0b110>; 3845 3846 //===----------------------------------------------------------------------===// 3847 // Bit-reversed .new stores with auto-increment register 3848 //===----------------------------------------------------------------------===// 3849 let isNewValue = 1, mayStore = 1, isNVStore = 1, opNewValue = 3, 3850 hasSideEffects = 0 in 3851 class T_storenew_pbr<string mnemonic, MemAccessSize addrSize, bits<2> majOp> 3852 : NVInst <(outs IntRegs:$_dst_), 3853 (ins IntRegs:$Rz, ModRegs:$Mu, IntRegs:$Nt), 3854 #mnemonic#"($Rz ++ $Mu:brev) = $Nt.new", [], 3855 "$Rz = $_dst_">, NewValueRel { 3856 let accessSize = addrSize; 3857 bits<5> Rz; 3858 bits<1> Mu; 3859 bits<3> Nt; 3860 3861 let IClass = 0b1010; 3862 3863 let Inst{27-21} = 0b1111101; 3864 let Inst{12-11} = majOp; 3865 let Inst{7} = 0b0; 3866 let Inst{20-16} = Rz; 3867 let Inst{13} = Mu; 3868 let Inst{10-8} = Nt; 3869 } 3870 3871 let BaseOpcode = "S2_storerb_pbr" in 3872 def S2_storerbnew_pbr : T_storenew_pbr<"memb", ByteAccess, 0b00>; 3873 3874 let BaseOpcode = "S2_storerh_pbr" in 3875 def S2_storerhnew_pbr : T_storenew_pbr<"memh", HalfWordAccess, 0b01>; 3876 3877 let BaseOpcode = "S2_storeri_pbr" in 3878 def S2_storerinew_pbr : T_storenew_pbr<"memw", WordAccess, 0b10>; 3879 3880 //===----------------------------------------------------------------------===// 3881 // ST - 3882 //===----------------------------------------------------------------------===// 3883 3884 //===----------------------------------------------------------------------===// 3885 // Template class for S_2op instructions. 3886 //===----------------------------------------------------------------------===// 3887 let hasSideEffects = 0 in 3888 class T_S2op_1 <string mnemonic, bits<4> RegTyBits, RegisterClass RCOut, 3889 RegisterClass RCIn, bits<2> MajOp, bits<3> MinOp, bit isSat> 3890 : SInst <(outs RCOut:$dst), (ins RCIn:$src), 3891 "$dst = "#mnemonic#"($src)"#!if(isSat, ":sat", ""), 3892 [], "", S_2op_tc_1_SLOT23 > { 3893 bits<5> dst; 3894 bits<5> src; 3895 3896 let IClass = 0b1000; 3897 3898 let Inst{27-24} = RegTyBits; 3899 let Inst{23-22} = MajOp; 3900 let Inst{21} = 0b0; 3901 let Inst{20-16} = src; 3902 let Inst{7-5} = MinOp; 3903 let Inst{4-0} = dst; 3904 } 3905 3906 class T_S2op_1_di <string mnemonic, bits<2> MajOp, bits<3> MinOp> 3907 : T_S2op_1 <mnemonic, 0b0100, DoubleRegs, IntRegs, MajOp, MinOp, 0>; 3908 3909 let hasNewValue = 1 in 3910 class T_S2op_1_id <string mnemonic, bits<2> MajOp, bits<3> MinOp, bit isSat = 0> 3911 : T_S2op_1 <mnemonic, 0b1000, IntRegs, DoubleRegs, MajOp, MinOp, isSat>; 3912 3913 let hasNewValue = 1 in 3914 class T_S2op_1_ii <string mnemonic, bits<2> MajOp, bits<3> MinOp, bit isSat = 0> 3915 : T_S2op_1 <mnemonic, 0b1100, IntRegs, IntRegs, MajOp, MinOp, isSat>; 3916 3917 // Vector sign/zero extend 3918 let isReMaterializable = 1, isAsCheapAsAMove = 1 in { 3919 def S2_vsxtbh : T_S2op_1_di <"vsxtbh", 0b00, 0b000>; 3920 def S2_vsxthw : T_S2op_1_di <"vsxthw", 0b00, 0b100>; 3921 def S2_vzxtbh : T_S2op_1_di <"vzxtbh", 0b00, 0b010>; 3922 def S2_vzxthw : T_S2op_1_di <"vzxthw", 0b00, 0b110>; 3923 } 3924 3925 // Vector splat bytes/halfwords 3926 let isReMaterializable = 1, isAsCheapAsAMove = 1 in { 3927 def S2_vsplatrb : T_S2op_1_ii <"vsplatb", 0b01, 0b111>; 3928 def S2_vsplatrh : T_S2op_1_di <"vsplath", 0b01, 0b010>; 3929 } 3930 3931 // Sign extend word to doubleword 3932 def A2_sxtw : T_S2op_1_di <"sxtw", 0b01, 0b000>; 3933 3934 def: Pat <(i64 (sext I32:$src)), (A2_sxtw I32:$src)>; 3935 3936 // Vector saturate and pack 3937 let Defs = [USR_OVF] in { 3938 def S2_svsathb : T_S2op_1_ii <"vsathb", 0b10, 0b000>; 3939 def S2_svsathub : T_S2op_1_ii <"vsathub", 0b10, 0b010>; 3940 def S2_vsathb : T_S2op_1_id <"vsathb", 0b00, 0b110>; 3941 def S2_vsathub : T_S2op_1_id <"vsathub", 0b00, 0b000>; 3942 def S2_vsatwh : T_S2op_1_id <"vsatwh", 0b00, 0b010>; 3943 def S2_vsatwuh : T_S2op_1_id <"vsatwuh", 0b00, 0b100>; 3944 } 3945 3946 // Vector truncate 3947 def S2_vtrunohb : T_S2op_1_id <"vtrunohb", 0b10, 0b000>; 3948 def S2_vtrunehb : T_S2op_1_id <"vtrunehb", 0b10, 0b010>; 3949 3950 // Swizzle the bytes of a word 3951 def A2_swiz : T_S2op_1_ii <"swiz", 0b10, 0b111>; 3952 3953 // Saturate 3954 let Defs = [USR_OVF] in { 3955 def A2_sat : T_S2op_1_id <"sat", 0b11, 0b000>; 3956 def A2_satb : T_S2op_1_ii <"satb", 0b11, 0b111>; 3957 def A2_satub : T_S2op_1_ii <"satub", 0b11, 0b110>; 3958 def A2_sath : T_S2op_1_ii <"sath", 0b11, 0b100>; 3959 def A2_satuh : T_S2op_1_ii <"satuh", 0b11, 0b101>; 3960 def A2_roundsat : T_S2op_1_id <"round", 0b11, 0b001, 0b1>; 3961 } 3962 3963 let Itinerary = S_2op_tc_2_SLOT23 in { 3964 // Vector round and pack 3965 def S2_vrndpackwh : T_S2op_1_id <"vrndwh", 0b10, 0b100>; 3966 3967 let Defs = [USR_OVF] in 3968 def S2_vrndpackwhs : T_S2op_1_id <"vrndwh", 0b10, 0b110, 1>; 3969 3970 // Bit reverse 3971 def S2_brev : T_S2op_1_ii <"brev", 0b01, 0b110>; 3972 3973 // Absolute value word 3974 def A2_abs : T_S2op_1_ii <"abs", 0b10, 0b100>; 3975 3976 let Defs = [USR_OVF] in 3977 def A2_abssat : T_S2op_1_ii <"abs", 0b10, 0b101, 1>; 3978 3979 // Negate with saturation 3980 let Defs = [USR_OVF] in 3981 def A2_negsat : T_S2op_1_ii <"neg", 0b10, 0b110, 1>; 3982 } 3983 3984 def: Pat<(i32 (select (i1 (setlt (i32 IntRegs:$src), 0)), 3985 (i32 (sub 0, (i32 IntRegs:$src))), 3986 (i32 IntRegs:$src))), 3987 (A2_abs IntRegs:$src)>; 3988 3989 let AddedComplexity = 50 in 3990 def: Pat<(i32 (xor (add (sra (i32 IntRegs:$src), (i32 31)), 3991 (i32 IntRegs:$src)), 3992 (sra (i32 IntRegs:$src), (i32 31)))), 3993 (A2_abs IntRegs:$src)>; 3994 3995 class T_S2op_2 <string mnemonic, bits<4> RegTyBits, RegisterClass RCOut, 3996 RegisterClass RCIn, bits<3> MajOp, bits<3> MinOp, 3997 bit isSat, bit isRnd, list<dag> pattern = []> 3998 : SInst <(outs RCOut:$dst), 3999 (ins RCIn:$src, u5Imm:$u5), 4000 "$dst = "#mnemonic#"($src, #$u5)"#!if(isSat, ":sat", "") 4001 #!if(isRnd, ":rnd", ""), 4002 pattern, "", S_2op_tc_2_SLOT23> { 4003 bits<5> dst; 4004 bits<5> src; 4005 bits<5> u5; 4006 4007 let IClass = 0b1000; 4008 4009 let Inst{27-24} = RegTyBits; 4010 let Inst{23-21} = MajOp; 4011 let Inst{20-16} = src; 4012 let Inst{13} = 0b0; 4013 let Inst{12-8} = u5; 4014 let Inst{7-5} = MinOp; 4015 let Inst{4-0} = dst; 4016 } 4017 4018 class T_S2op_2_di <string mnemonic, bits<3> MajOp, bits<3> MinOp> 4019 : T_S2op_2 <mnemonic, 0b1000, DoubleRegs, IntRegs, MajOp, MinOp, 0, 0>; 4020 4021 let hasNewValue = 1 in 4022 class T_S2op_2_id <string mnemonic, bits<3> MajOp, bits<3> MinOp> 4023 : T_S2op_2 <mnemonic, 0b1000, IntRegs, DoubleRegs, MajOp, MinOp, 0, 0>; 4024 4025 let hasNewValue = 1 in 4026 class T_S2op_2_ii <string mnemonic, bits<3> MajOp, bits<3> MinOp, 4027 bit isSat = 0, bit isRnd = 0, list<dag> pattern = []> 4028 : T_S2op_2 <mnemonic, 0b1100, IntRegs, IntRegs, MajOp, MinOp, 4029 isSat, isRnd, pattern>; 4030 4031 class T_S2op_shift <string mnemonic, bits<3> MajOp, bits<3> MinOp, SDNode OpNd> 4032 : T_S2op_2_ii <mnemonic, MajOp, MinOp, 0, 0, 4033 [(set (i32 IntRegs:$dst), (OpNd (i32 IntRegs:$src), 4034 (u5ImmPred:$u5)))]>; 4035 4036 // Vector arithmetic shift right by immediate with truncate and pack 4037 def S2_asr_i_svw_trun : T_S2op_2_id <"vasrw", 0b110, 0b010>; 4038 4039 // Arithmetic/logical shift right/left by immediate 4040 let Itinerary = S_2op_tc_1_SLOT23 in { 4041 def S2_asr_i_r : T_S2op_shift <"asr", 0b000, 0b000, sra>; 4042 def S2_lsr_i_r : T_S2op_shift <"lsr", 0b000, 0b001, srl>; 4043 def S2_asl_i_r : T_S2op_shift <"asl", 0b000, 0b010, shl>; 4044 } 4045 4046 // Shift left by immediate with saturation 4047 let Defs = [USR_OVF] in 4048 def S2_asl_i_r_sat : T_S2op_2_ii <"asl", 0b010, 0b010, 1>; 4049 4050 // Shift right with round 4051 def S2_asr_i_r_rnd : T_S2op_2_ii <"asr", 0b010, 0b000, 0, 1>; 4052 4053 let isAsmParserOnly = 1 in 4054 def S2_asr_i_r_rnd_goodsyntax 4055 : SInst <(outs IntRegs:$dst), (ins IntRegs:$src, u5Imm:$u5), 4056 "$dst = asrrnd($src, #$u5)", 4057 [], "", S_2op_tc_1_SLOT23>; 4058 4059 let isAsmParserOnly = 1 in 4060 def A2_not: ALU32_rr<(outs IntRegs:$dst),(ins IntRegs:$src), 4061 "$dst = not($src)">; 4062 4063 def: Pat<(i32 (sra (i32 (add (i32 (sra I32:$src1, u5ImmPred:$src2)), 4064 (i32 1))), 4065 (i32 1))), 4066 (S2_asr_i_r_rnd IntRegs:$src1, u5ImmPred:$src2)>; 4067 4068 class T_S2op_3<string opc, bits<2>MajOp, bits<3>minOp, bits<1> sat = 0> 4069 : SInst<(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss), 4070 "$Rdd = "#opc#"($Rss)"#!if(!eq(sat, 1),":sat","")> { 4071 bits<5> Rss; 4072 bits<5> Rdd; 4073 let IClass = 0b1000; 4074 let Inst{27-24} = 0; 4075 let Inst{23-22} = MajOp; 4076 let Inst{20-16} = Rss; 4077 let Inst{7-5} = minOp; 4078 let Inst{4-0} = Rdd; 4079 } 4080 4081 def A2_absp : T_S2op_3 <"abs", 0b10, 0b110>; 4082 def A2_negp : T_S2op_3 <"neg", 0b10, 0b101>; 4083 def A2_notp : T_S2op_3 <"not", 0b10, 0b100>; 4084 4085 // Innterleave/deinterleave 4086 def S2_interleave : T_S2op_3 <"interleave", 0b11, 0b101>; 4087 def S2_deinterleave : T_S2op_3 <"deinterleave", 0b11, 0b100>; 4088 4089 // Vector Complex conjugate 4090 def A2_vconj : T_S2op_3 <"vconj", 0b10, 0b111, 1>; 4091 4092 // Vector saturate without pack 4093 def S2_vsathb_nopack : T_S2op_3 <"vsathb", 0b00, 0b111>; 4094 def S2_vsathub_nopack : T_S2op_3 <"vsathub", 0b00, 0b100>; 4095 def S2_vsatwh_nopack : T_S2op_3 <"vsatwh", 0b00, 0b110>; 4096 def S2_vsatwuh_nopack : T_S2op_3 <"vsatwuh", 0b00, 0b101>; 4097 4098 // Vector absolute value halfwords with and without saturation 4099 // Rdd64=vabsh(Rss64)[:sat] 4100 def A2_vabsh : T_S2op_3 <"vabsh", 0b01, 0b100>; 4101 def A2_vabshsat : T_S2op_3 <"vabsh", 0b01, 0b101, 1>; 4102 4103 // Vector absolute value words with and without saturation 4104 def A2_vabsw : T_S2op_3 <"vabsw", 0b01, 0b110>; 4105 def A2_vabswsat : T_S2op_3 <"vabsw", 0b01, 0b111, 1>; 4106 4107 def : Pat<(not (i64 DoubleRegs:$src1)), 4108 (A2_notp DoubleRegs:$src1)>; 4109 4110 //===----------------------------------------------------------------------===// 4111 // STYPE/BIT + 4112 //===----------------------------------------------------------------------===// 4113 // Bit count 4114 4115 let hasSideEffects = 0, hasNewValue = 1 in 4116 class T_COUNT_LEADING<string MnOp, bits<3> MajOp, bits<3> MinOp, bit Is32, 4117 dag Out, dag Inp> 4118 : SInst<Out, Inp, "$Rd = "#MnOp#"($Rs)", [], "", S_2op_tc_1_SLOT23> { 4119 bits<5> Rs; 4120 bits<5> Rd; 4121 let IClass = 0b1000; 4122 let Inst{27} = 0b1; 4123 let Inst{26} = Is32; 4124 let Inst{25-24} = 0b00; 4125 let Inst{23-21} = MajOp; 4126 let Inst{20-16} = Rs; 4127 let Inst{7-5} = MinOp; 4128 let Inst{4-0} = Rd; 4129 } 4130 4131 class T_COUNT_LEADING_32<string MnOp, bits<3> MajOp, bits<3> MinOp> 4132 : T_COUNT_LEADING<MnOp, MajOp, MinOp, 0b1, 4133 (outs IntRegs:$Rd), (ins IntRegs:$Rs)>; 4134 4135 class T_COUNT_LEADING_64<string MnOp, bits<3> MajOp, bits<3> MinOp> 4136 : T_COUNT_LEADING<MnOp, MajOp, MinOp, 0b0, 4137 (outs IntRegs:$Rd), (ins DoubleRegs:$Rs)>; 4138 4139 def S2_cl0 : T_COUNT_LEADING_32<"cl0", 0b000, 0b101>; 4140 def S2_cl1 : T_COUNT_LEADING_32<"cl1", 0b000, 0b110>; 4141 def S2_ct0 : T_COUNT_LEADING_32<"ct0", 0b010, 0b100>; 4142 def S2_ct1 : T_COUNT_LEADING_32<"ct1", 0b010, 0b101>; 4143 def S2_cl0p : T_COUNT_LEADING_64<"cl0", 0b010, 0b010>; 4144 def S2_cl1p : T_COUNT_LEADING_64<"cl1", 0b010, 0b100>; 4145 def S2_clb : T_COUNT_LEADING_32<"clb", 0b000, 0b100>; 4146 def S2_clbp : T_COUNT_LEADING_64<"clb", 0b010, 0b000>; 4147 def S2_clbnorm : T_COUNT_LEADING_32<"normamt", 0b000, 0b111>; 4148 4149 // Count leading zeros. 4150 def: Pat<(i32 (ctlz I32:$Rs)), (S2_cl0 I32:$Rs)>; 4151 def: Pat<(i32 (trunc (ctlz I64:$Rss))), (S2_cl0p I64:$Rss)>; 4152 4153 // Count trailing zeros: 32-bit. 4154 def: Pat<(i32 (cttz I32:$Rs)), (S2_ct0 I32:$Rs)>; 4155 4156 // Count leading ones. 4157 def: Pat<(i32 (ctlz (not I32:$Rs))), (S2_cl1 I32:$Rs)>; 4158 def: Pat<(i32 (trunc (ctlz (not I64:$Rss)))), (S2_cl1p I64:$Rss)>; 4159 4160 // Count trailing ones: 32-bit. 4161 def: Pat<(i32 (cttz (not I32:$Rs))), (S2_ct1 I32:$Rs)>; 4162 4163 // The 64-bit counts leading/trailing are defined in HexagonInstrInfoV4.td. 4164 4165 // Bit set/clear/toggle 4166 4167 let hasSideEffects = 0, hasNewValue = 1 in 4168 class T_SCT_BIT_IMM<string MnOp, bits<3> MinOp> 4169 : SInst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, u5Imm:$u5), 4170 "$Rd = "#MnOp#"($Rs, #$u5)", [], "", S_2op_tc_1_SLOT23> { 4171 bits<5> Rd; 4172 bits<5> Rs; 4173 bits<5> u5; 4174 let IClass = 0b1000; 4175 let Inst{27-21} = 0b1100110; 4176 let Inst{20-16} = Rs; 4177 let Inst{13} = 0b0; 4178 let Inst{12-8} = u5; 4179 let Inst{7-5} = MinOp; 4180 let Inst{4-0} = Rd; 4181 } 4182 4183 let hasSideEffects = 0, hasNewValue = 1 in 4184 class T_SCT_BIT_REG<string MnOp, bits<2> MinOp> 4185 : SInst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt), 4186 "$Rd = "#MnOp#"($Rs, $Rt)", [], "", S_3op_tc_1_SLOT23> { 4187 bits<5> Rd; 4188 bits<5> Rs; 4189 bits<5> Rt; 4190 let IClass = 0b1100; 4191 let Inst{27-22} = 0b011010; 4192 let Inst{20-16} = Rs; 4193 let Inst{12-8} = Rt; 4194 let Inst{7-6} = MinOp; 4195 let Inst{4-0} = Rd; 4196 } 4197 4198 def S2_clrbit_i : T_SCT_BIT_IMM<"clrbit", 0b001>; 4199 def S2_setbit_i : T_SCT_BIT_IMM<"setbit", 0b000>; 4200 def S2_togglebit_i : T_SCT_BIT_IMM<"togglebit", 0b010>; 4201 def S2_clrbit_r : T_SCT_BIT_REG<"clrbit", 0b01>; 4202 def S2_setbit_r : T_SCT_BIT_REG<"setbit", 0b00>; 4203 def S2_togglebit_r : T_SCT_BIT_REG<"togglebit", 0b10>; 4204 4205 def: Pat<(i32 (and (i32 IntRegs:$Rs), (not (shl 1, u5ImmPred:$u5)))), 4206 (S2_clrbit_i IntRegs:$Rs, u5ImmPred:$u5)>; 4207 def: Pat<(i32 (or (i32 IntRegs:$Rs), (shl 1, u5ImmPred:$u5))), 4208 (S2_setbit_i IntRegs:$Rs, u5ImmPred:$u5)>; 4209 def: Pat<(i32 (xor (i32 IntRegs:$Rs), (shl 1, u5ImmPred:$u5))), 4210 (S2_togglebit_i IntRegs:$Rs, u5ImmPred:$u5)>; 4211 def: Pat<(i32 (and (i32 IntRegs:$Rs), (not (shl 1, (i32 IntRegs:$Rt))))), 4212 (S2_clrbit_r IntRegs:$Rs, IntRegs:$Rt)>; 4213 def: Pat<(i32 (or (i32 IntRegs:$Rs), (shl 1, (i32 IntRegs:$Rt)))), 4214 (S2_setbit_r IntRegs:$Rs, IntRegs:$Rt)>; 4215 def: Pat<(i32 (xor (i32 IntRegs:$Rs), (shl 1, (i32 IntRegs:$Rt)))), 4216 (S2_togglebit_r IntRegs:$Rs, IntRegs:$Rt)>; 4217 4218 // Bit test 4219 4220 let hasSideEffects = 0 in 4221 class T_TEST_BIT_IMM<string MnOp, bits<3> MajOp> 4222 : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, u5Imm:$u5), 4223 "$Pd = "#MnOp#"($Rs, #$u5)", 4224 [], "", S_2op_tc_2early_SLOT23> { 4225 bits<2> Pd; 4226 bits<5> Rs; 4227 bits<5> u5; 4228 let IClass = 0b1000; 4229 let Inst{27-24} = 0b0101; 4230 let Inst{23-21} = MajOp; 4231 let Inst{20-16} = Rs; 4232 let Inst{13} = 0; 4233 let Inst{12-8} = u5; 4234 let Inst{1-0} = Pd; 4235 } 4236 4237 let hasSideEffects = 0 in 4238 class T_TEST_BIT_REG<string MnOp, bit IsNeg> 4239 : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt), 4240 "$Pd = "#MnOp#"($Rs, $Rt)", 4241 [], "", S_3op_tc_2early_SLOT23> { 4242 bits<2> Pd; 4243 bits<5> Rs; 4244 bits<5> Rt; 4245 let IClass = 0b1100; 4246 let Inst{27-22} = 0b011100; 4247 let Inst{21} = IsNeg; 4248 let Inst{20-16} = Rs; 4249 let Inst{12-8} = Rt; 4250 let Inst{1-0} = Pd; 4251 } 4252 4253 def S2_tstbit_i : T_TEST_BIT_IMM<"tstbit", 0b000>; 4254 def S2_tstbit_r : T_TEST_BIT_REG<"tstbit", 0>; 4255 4256 let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm. 4257 def: Pat<(i1 (setne (and (shl 1, u5ImmPred:$u5), (i32 IntRegs:$Rs)), 0)), 4258 (S2_tstbit_i IntRegs:$Rs, u5ImmPred:$u5)>; 4259 def: Pat<(i1 (setne (and (shl 1, (i32 IntRegs:$Rt)), (i32 IntRegs:$Rs)), 0)), 4260 (S2_tstbit_r IntRegs:$Rs, IntRegs:$Rt)>; 4261 def: Pat<(i1 (trunc (i32 IntRegs:$Rs))), 4262 (S2_tstbit_i IntRegs:$Rs, 0)>; 4263 def: Pat<(i1 (trunc (i64 DoubleRegs:$Rs))), 4264 (S2_tstbit_i (LoReg DoubleRegs:$Rs), 0)>; 4265 } 4266 4267 let hasSideEffects = 0 in 4268 class T_TEST_BITS_IMM<string MnOp, bits<2> MajOp, bit IsNeg> 4269 : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, u6Imm:$u6), 4270 "$Pd = "#MnOp#"($Rs, #$u6)", 4271 [], "", S_2op_tc_2early_SLOT23> { 4272 bits<2> Pd; 4273 bits<5> Rs; 4274 bits<6> u6; 4275 let IClass = 0b1000; 4276 let Inst{27-24} = 0b0101; 4277 let Inst{23-22} = MajOp; 4278 let Inst{21} = IsNeg; 4279 let Inst{20-16} = Rs; 4280 let Inst{13-8} = u6; 4281 let Inst{1-0} = Pd; 4282 } 4283 4284 let hasSideEffects = 0 in 4285 class T_TEST_BITS_REG<string MnOp, bits<2> MajOp, bit IsNeg> 4286 : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt), 4287 "$Pd = "#MnOp#"($Rs, $Rt)", 4288 [], "", S_3op_tc_2early_SLOT23> { 4289 bits<2> Pd; 4290 bits<5> Rs; 4291 bits<5> Rt; 4292 let IClass = 0b1100; 4293 let Inst{27-24} = 0b0111; 4294 let Inst{23-22} = MajOp; 4295 let Inst{21} = IsNeg; 4296 let Inst{20-16} = Rs; 4297 let Inst{12-8} = Rt; 4298 let Inst{1-0} = Pd; 4299 } 4300 4301 def C2_bitsclri : T_TEST_BITS_IMM<"bitsclr", 0b10, 0>; 4302 def C2_bitsclr : T_TEST_BITS_REG<"bitsclr", 0b10, 0>; 4303 def C2_bitsset : T_TEST_BITS_REG<"bitsset", 0b01, 0>; 4304 4305 let AddedComplexity = 20 in { // Complexity greater than compare reg-imm. 4306 def: Pat<(i1 (seteq (and (i32 IntRegs:$Rs), u6ImmPred:$u6), 0)), 4307 (C2_bitsclri IntRegs:$Rs, u6ImmPred:$u6)>; 4308 def: Pat<(i1 (seteq (and (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)), 0)), 4309 (C2_bitsclr IntRegs:$Rs, IntRegs:$Rt)>; 4310 } 4311 4312 let AddedComplexity = 10 in // Complexity greater than compare reg-reg. 4313 def: Pat<(i1 (seteq (and (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)), IntRegs:$Rt)), 4314 (C2_bitsset IntRegs:$Rs, IntRegs:$Rt)>; 4315 4316 //===----------------------------------------------------------------------===// 4317 // STYPE/BIT - 4318 //===----------------------------------------------------------------------===// 4319 4320 //===----------------------------------------------------------------------===// 4321 // STYPE/COMPLEX + 4322 //===----------------------------------------------------------------------===// 4323 //===----------------------------------------------------------------------===// 4324 // STYPE/COMPLEX - 4325 //===----------------------------------------------------------------------===// 4326 4327 //===----------------------------------------------------------------------===// 4328 // XTYPE/PERM + 4329 //===----------------------------------------------------------------------===// 4330 4331 def: Pat<(or (or (shl (or (shl (i32 (extloadi8 (add (i32 IntRegs:$b), 3))), 4332 (i32 8)), 4333 (i32 (zextloadi8 (add (i32 IntRegs:$b), 2)))), 4334 (i32 16)), 4335 (shl (i32 (zextloadi8 (add (i32 IntRegs:$b), 1))), (i32 8))), 4336 (zextloadi8 (i32 IntRegs:$b))), 4337 (A2_swiz (L2_loadri_io IntRegs:$b, 0))>; 4338 4339 //===----------------------------------------------------------------------===// 4340 // XTYPE/PERM - 4341 //===----------------------------------------------------------------------===// 4342 4343 //===----------------------------------------------------------------------===// 4344 // STYPE/PRED + 4345 //===----------------------------------------------------------------------===// 4346 4347 // Predicate transfer. 4348 let hasSideEffects = 0, hasNewValue = 1 in 4349 def C2_tfrpr : SInst<(outs IntRegs:$Rd), (ins PredRegs:$Ps), 4350 "$Rd = $Ps", [], "", S_2op_tc_1_SLOT23> { 4351 bits<5> Rd; 4352 bits<2> Ps; 4353 4354 let IClass = 0b1000; 4355 let Inst{27-24} = 0b1001; 4356 let Inst{22} = 0b1; 4357 let Inst{17-16} = Ps; 4358 let Inst{4-0} = Rd; 4359 } 4360 4361 // Transfer general register to predicate. 4362 let hasSideEffects = 0 in 4363 def C2_tfrrp: SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs), 4364 "$Pd = $Rs", [], "", S_2op_tc_2early_SLOT23> { 4365 bits<2> Pd; 4366 bits<5> Rs; 4367 4368 let IClass = 0b1000; 4369 let Inst{27-21} = 0b0101010; 4370 let Inst{20-16} = Rs; 4371 let Inst{1-0} = Pd; 4372 } 4373 4374 let hasSideEffects = 0, isCodeGenOnly = 1 in 4375 def C2_pxfer_map: SInst<(outs PredRegs:$dst), (ins PredRegs:$src), 4376 "$dst = $src">; 4377 4378 4379 // Patterns for loads of i1: 4380 def: Pat<(i1 (load AddrFI:$fi)), 4381 (C2_tfrrp (L2_loadrub_io AddrFI:$fi, 0))>; 4382 def: Pat<(i1 (load (add (i32 IntRegs:$Rs), s32ImmPred:$Off))), 4383 (C2_tfrrp (L2_loadrub_io IntRegs:$Rs, imm:$Off))>; 4384 def: Pat<(i1 (load (i32 IntRegs:$Rs))), 4385 (C2_tfrrp (L2_loadrub_io IntRegs:$Rs, 0))>; 4386 4387 def I1toI32: OutPatFrag<(ops node:$Rs), 4388 (C2_muxii (i1 $Rs), 1, 0)>; 4389 4390 def I32toI1: OutPatFrag<(ops node:$Rs), 4391 (i1 (C2_tfrrp (i32 $Rs)))>; 4392 4393 defm: Storexm_pat<store, I1, s32ImmPred, I1toI32, S2_storerb_io>; 4394 def: Storexm_simple_pat<store, I1, I1toI32, S2_storerb_io>; 4395 4396 //===----------------------------------------------------------------------===// 4397 // STYPE/PRED - 4398 //===----------------------------------------------------------------------===// 4399 4400 //===----------------------------------------------------------------------===// 4401 // STYPE/SHIFT + 4402 //===----------------------------------------------------------------------===// 4403 class S_2OpInstImm<string Mnemonic, bits<3>MajOp, bits<3>MinOp, 4404 Operand Imm, list<dag> pattern = [], bit isRnd = 0> 4405 : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, Imm:$src2), 4406 "$dst = "#Mnemonic#"($src1, #$src2)"#!if(isRnd, ":rnd", ""), 4407 pattern> { 4408 bits<5> src1; 4409 bits<5> dst; 4410 let IClass = 0b1000; 4411 let Inst{27-24} = 0; 4412 let Inst{23-21} = MajOp; 4413 let Inst{20-16} = src1; 4414 let Inst{7-5} = MinOp; 4415 let Inst{4-0} = dst; 4416 } 4417 4418 class S_2OpInstImmI6<string Mnemonic, SDNode OpNode, bits<3>MinOp> 4419 : S_2OpInstImm<Mnemonic, 0b000, MinOp, u6Imm, 4420 [(set (i64 DoubleRegs:$dst), (OpNode (i64 DoubleRegs:$src1), 4421 u6ImmPred:$src2))]> { 4422 bits<6> src2; 4423 let Inst{13-8} = src2; 4424 } 4425 4426 // Shift by immediate. 4427 def S2_asr_i_p : S_2OpInstImmI6<"asr", sra, 0b000>; 4428 def S2_asl_i_p : S_2OpInstImmI6<"asl", shl, 0b010>; 4429 def S2_lsr_i_p : S_2OpInstImmI6<"lsr", srl, 0b001>; 4430 4431 // Shift left by small amount and add. 4432 let AddedComplexity = 100, hasNewValue = 1, hasSideEffects = 0 in 4433 def S2_addasl_rrri: SInst <(outs IntRegs:$Rd), 4434 (ins IntRegs:$Rt, IntRegs:$Rs, u3Imm:$u3), 4435 "$Rd = addasl($Rt, $Rs, #$u3)" , 4436 [(set (i32 IntRegs:$Rd), (add (i32 IntRegs:$Rt), 4437 (shl (i32 IntRegs:$Rs), u3ImmPred:$u3)))], 4438 "", S_3op_tc_2_SLOT23> { 4439 bits<5> Rd; 4440 bits<5> Rt; 4441 bits<5> Rs; 4442 bits<3> u3; 4443 4444 let IClass = 0b1100; 4445 4446 let Inst{27-21} = 0b0100000; 4447 let Inst{20-16} = Rs; 4448 let Inst{13} = 0b0; 4449 let Inst{12-8} = Rt; 4450 let Inst{7-5} = u3; 4451 let Inst{4-0} = Rd; 4452 } 4453 4454 //===----------------------------------------------------------------------===// 4455 // STYPE/SHIFT - 4456 //===----------------------------------------------------------------------===// 4457 4458 //===----------------------------------------------------------------------===// 4459 // STYPE/VH + 4460 //===----------------------------------------------------------------------===// 4461 //===----------------------------------------------------------------------===// 4462 // STYPE/VH - 4463 //===----------------------------------------------------------------------===// 4464 4465 //===----------------------------------------------------------------------===// 4466 // STYPE/VW + 4467 //===----------------------------------------------------------------------===// 4468 //===----------------------------------------------------------------------===// 4469 // STYPE/VW - 4470 //===----------------------------------------------------------------------===// 4471 4472 //===----------------------------------------------------------------------===// 4473 // SYSTEM/SUPER + 4474 //===----------------------------------------------------------------------===// 4475 4476 //===----------------------------------------------------------------------===// 4477 // SYSTEM/USER + 4478 //===----------------------------------------------------------------------===// 4479 def HexagonBARRIER: SDNode<"HexagonISD::BARRIER", SDTNone, [SDNPHasChain]>; 4480 4481 let hasSideEffects = 1, isSoloAX = 1 in 4482 def Y2_barrier : SYSInst<(outs), (ins), 4483 "barrier", 4484 [(HexagonBARRIER)],"",ST_tc_st_SLOT0> { 4485 let Inst{31-28} = 0b1010; 4486 let Inst{27-21} = 0b1000000; 4487 } 4488 4489 //===----------------------------------------------------------------------===// 4490 // SYSTEM/SUPER - 4491 //===----------------------------------------------------------------------===// 4492 4493 // Generate frameindex addresses. The main reason for the offset operand is 4494 // that every instruction that is allowed to have frame index as an operand 4495 // will then have that operand followed by an immediate operand (the offset). 4496 // This simplifies the frame-index elimination code. 4497 // 4498 let isMoveImm = 1, isAsCheapAsAMove = 1, isReMaterializable = 1, 4499 isPseudo = 1, isCodeGenOnly = 1, hasSideEffects = 0 in { 4500 def TFR_FI : ALU32_ri<(outs IntRegs:$Rd), 4501 (ins IntRegs:$fi, s32Imm:$off), "">; 4502 def TFR_FIA : ALU32_ri<(outs IntRegs:$Rd), 4503 (ins IntRegs:$Rs, IntRegs:$fi, s32Imm:$off), "">; 4504 } 4505 4506 //===----------------------------------------------------------------------===// 4507 // CRUSER - Type. 4508 //===----------------------------------------------------------------------===// 4509 // HW loop 4510 let isExtendable = 1, isExtentSigned = 1, opExtentBits = 9, opExtentAlign = 2, 4511 opExtendable = 0, hasSideEffects = 0 in 4512 class LOOP_iBase<string mnemonic, Operand brOp, bit mustExtend = 0> 4513 : CRInst<(outs), (ins brOp:$offset, u10Imm:$src2), 4514 #mnemonic#"($offset, #$src2)", 4515 [], "" , CR_tc_3x_SLOT3> { 4516 bits<9> offset; 4517 bits<10> src2; 4518 4519 let IClass = 0b0110; 4520 4521 let Inst{27-22} = 0b100100; 4522 let Inst{21} = !if (!eq(mnemonic, "loop0"), 0b0, 0b1); 4523 let Inst{20-16} = src2{9-5}; 4524 let Inst{12-8} = offset{8-4}; 4525 let Inst{7-5} = src2{4-2}; 4526 let Inst{4-3} = offset{3-2}; 4527 let Inst{1-0} = src2{1-0}; 4528 } 4529 4530 let isExtendable = 1, isExtentSigned = 1, opExtentBits = 9, opExtentAlign = 2, 4531 opExtendable = 0, hasSideEffects = 0 in 4532 class LOOP_rBase<string mnemonic, Operand brOp, bit mustExtend = 0> 4533 : CRInst<(outs), (ins brOp:$offset, IntRegs:$src2), 4534 #mnemonic#"($offset, $src2)", 4535 [], "" ,CR_tc_3x_SLOT3> { 4536 bits<9> offset; 4537 bits<5> src2; 4538 4539 let IClass = 0b0110; 4540 4541 let Inst{27-22} = 0b000000; 4542 let Inst{21} = !if (!eq(mnemonic, "loop0"), 0b0, 0b1); 4543 let Inst{20-16} = src2; 4544 let Inst{12-8} = offset{8-4}; 4545 let Inst{4-3} = offset{3-2}; 4546 } 4547 4548 multiclass LOOP_ri<string mnemonic> { 4549 def i : LOOP_iBase<mnemonic, brtarget>; 4550 def r : LOOP_rBase<mnemonic, brtarget>; 4551 4552 let isCodeGenOnly = 1, isExtended = 1, opExtendable = 0 in { 4553 def iext: LOOP_iBase<mnemonic, brtargetExt, 1>; 4554 def rext: LOOP_rBase<mnemonic, brtargetExt, 1>; 4555 } 4556 } 4557 4558 4559 let Defs = [SA0, LC0, USR] in 4560 defm J2_loop0 : LOOP_ri<"loop0">; 4561 4562 // Interestingly only loop0's appear to set usr.lpcfg 4563 let Defs = [SA1, LC1] in 4564 defm J2_loop1 : LOOP_ri<"loop1">; 4565 4566 let isBranch = 1, isTerminator = 1, hasSideEffects = 0, 4567 Defs = [PC, LC0], Uses = [SA0, LC0] in { 4568 def ENDLOOP0 : Endloop<(outs), (ins brtarget:$offset), 4569 ":endloop0", 4570 []>; 4571 } 4572 4573 let isBranch = 1, isTerminator = 1, hasSideEffects = 0, 4574 Defs = [PC, LC1], Uses = [SA1, LC1] in { 4575 def ENDLOOP1 : Endloop<(outs), (ins brtarget:$offset), 4576 ":endloop1", 4577 []>; 4578 } 4579 4580 // Pipelined loop instructions, sp[123]loop0 4581 let Defs = [LC0, SA0, P3, USR], hasSideEffects = 0, 4582 isExtentSigned = 1, isExtendable = 1, opExtentBits = 9, opExtentAlign = 2, 4583 opExtendable = 0, isPredicateLate = 1 in 4584 class SPLOOP_iBase<string SP, bits<2> op> 4585 : CRInst <(outs), (ins brtarget:$r7_2, u10Imm:$U10), 4586 "p3 = sp"#SP#"loop0($r7_2, #$U10)" > { 4587 bits<9> r7_2; 4588 bits<10> U10; 4589 4590 let IClass = 0b0110; 4591 4592 let Inst{22-21} = op; 4593 let Inst{27-23} = 0b10011; 4594 let Inst{20-16} = U10{9-5}; 4595 let Inst{12-8} = r7_2{8-4}; 4596 let Inst{7-5} = U10{4-2}; 4597 let Inst{4-3} = r7_2{3-2}; 4598 let Inst{1-0} = U10{1-0}; 4599 } 4600 4601 let Defs = [LC0, SA0, P3, USR], hasSideEffects = 0, 4602 isExtentSigned = 1, isExtendable = 1, opExtentBits = 9, opExtentAlign = 2, 4603 opExtendable = 0, isPredicateLate = 1 in 4604 class SPLOOP_rBase<string SP, bits<2> op> 4605 : CRInst <(outs), (ins brtarget:$r7_2, IntRegs:$Rs), 4606 "p3 = sp"#SP#"loop0($r7_2, $Rs)" > { 4607 bits<9> r7_2; 4608 bits<5> Rs; 4609 4610 let IClass = 0b0110; 4611 4612 let Inst{22-21} = op; 4613 let Inst{27-23} = 0b00001; 4614 let Inst{20-16} = Rs; 4615 let Inst{12-8} = r7_2{8-4}; 4616 let Inst{4-3} = r7_2{3-2}; 4617 } 4618 4619 multiclass SPLOOP_ri<string mnemonic, bits<2> op> { 4620 def i : SPLOOP_iBase<mnemonic, op>; 4621 def r : SPLOOP_rBase<mnemonic, op>; 4622 } 4623 4624 defm J2_ploop1s : SPLOOP_ri<"1", 0b01>; 4625 defm J2_ploop2s : SPLOOP_ri<"2", 0b10>; 4626 defm J2_ploop3s : SPLOOP_ri<"3", 0b11>; 4627 4628 // if (Rs[!>=<]=#0) jump:[t/nt] 4629 let Defs = [PC], isPredicated = 1, isBranch = 1, hasSideEffects = 0, 4630 hasSideEffects = 0 in 4631 class J2_jump_0_Base<string compare, bit isTak, bits<2> op> 4632 : CRInst <(outs), (ins IntRegs:$Rs, brtarget:$r13_2), 4633 "if ($Rs"#compare#"#0) jump"#!if(isTak, ":t", ":nt")#" $r13_2" > { 4634 bits<5> Rs; 4635 bits<15> r13_2; 4636 4637 let IClass = 0b0110; 4638 4639 let Inst{27-24} = 0b0001; 4640 let Inst{23-22} = op; 4641 let Inst{12} = isTak; 4642 let Inst{21} = r13_2{14}; 4643 let Inst{20-16} = Rs; 4644 let Inst{11-1} = r13_2{12-2}; 4645 let Inst{13} = r13_2{13}; 4646 } 4647 4648 multiclass J2_jump_compare_0<string compare, bits<2> op> { 4649 def NAME : J2_jump_0_Base<compare, 0, op>; 4650 def NAME#pt : J2_jump_0_Base<compare, 1, op>; 4651 } 4652 4653 defm J2_jumprz : J2_jump_compare_0<"!=", 0b00>; 4654 defm J2_jumprgtez : J2_jump_compare_0<">=", 0b01>; 4655 defm J2_jumprnz : J2_jump_compare_0<"==", 0b10>; 4656 defm J2_jumprltez : J2_jump_compare_0<"<=", 0b11>; 4657 4658 // Transfer to/from Control/GPR Guest/GPR 4659 let hasSideEffects = 0 in 4660 class TFR_CR_RS_base<RegisterClass CTRC, RegisterClass RC, bit isDouble> 4661 : CRInst <(outs CTRC:$dst), (ins RC:$src), 4662 "$dst = $src", [], "", CR_tc_3x_SLOT3> { 4663 bits<5> dst; 4664 bits<5> src; 4665 4666 let IClass = 0b0110; 4667 4668 let Inst{27-25} = 0b001; 4669 let Inst{24} = isDouble; 4670 let Inst{23-21} = 0b001; 4671 let Inst{20-16} = src; 4672 let Inst{4-0} = dst; 4673 } 4674 4675 def A2_tfrrcr : TFR_CR_RS_base<CtrRegs, IntRegs, 0b0>; 4676 def A4_tfrpcp : TFR_CR_RS_base<CtrRegs64, DoubleRegs, 0b1>; 4677 def : InstAlias<"m0 = $Rs", (A2_tfrrcr C6, IntRegs:$Rs)>; 4678 def : InstAlias<"m1 = $Rs", (A2_tfrrcr C7, IntRegs:$Rs)>; 4679 4680 let hasSideEffects = 0 in 4681 class TFR_RD_CR_base<RegisterClass RC, RegisterClass CTRC, bit isSingle> 4682 : CRInst <(outs RC:$dst), (ins CTRC:$src), 4683 "$dst = $src", [], "", CR_tc_3x_SLOT3> { 4684 bits<5> dst; 4685 bits<5> src; 4686 4687 let IClass = 0b0110; 4688 4689 let Inst{27-26} = 0b10; 4690 let Inst{25} = isSingle; 4691 let Inst{24-21} = 0b0000; 4692 let Inst{20-16} = src; 4693 let Inst{4-0} = dst; 4694 } 4695 4696 let hasNewValue = 1, opNewValue = 0 in 4697 def A2_tfrcrr : TFR_RD_CR_base<IntRegs, CtrRegs, 1>; 4698 def A4_tfrcpp : TFR_RD_CR_base<DoubleRegs, CtrRegs64, 0>; 4699 def : InstAlias<"$Rd = m0", (A2_tfrcrr IntRegs:$Rd, C6)>; 4700 def : InstAlias<"$Rd = m1", (A2_tfrcrr IntRegs:$Rd, C7)>; 4701 4702 // Y4_trace: Send value to etm trace. 4703 let isSoloAX = 1, hasSideEffects = 0 in 4704 def Y4_trace: CRInst <(outs), (ins IntRegs:$Rs), 4705 "trace($Rs)"> { 4706 bits<5> Rs; 4707 4708 let IClass = 0b0110; 4709 let Inst{27-21} = 0b0010010; 4710 let Inst{20-16} = Rs; 4711 } 4712 4713 // Support for generating global address. 4714 // Taken from X86InstrInfo.td. 4715 def SDTHexagonCONST32 : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, 4716 SDTCisVT<1, i32>, 4717 SDTCisPtrTy<0>]>; 4718 def HexagonCONST32 : SDNode<"HexagonISD::CONST32", SDTHexagonCONST32>; 4719 def HexagonCONST32_GP : SDNode<"HexagonISD::CONST32_GP", SDTHexagonCONST32>; 4720 4721 // HI/LO Instructions 4722 let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0, 4723 hasNewValue = 1, opNewValue = 0 in 4724 class REG_IMMED<string RegHalf, string Op, bit Rs, bits<3> MajOp, bit MinOp> 4725 : ALU32_ri<(outs IntRegs:$dst), 4726 (ins i32imm:$imm_value), 4727 "$dst"#RegHalf#" = #"#Op#"($imm_value)", []> { 4728 bits<5> dst; 4729 bits<32> imm_value; 4730 let IClass = 0b0111; 4731 4732 let Inst{27} = Rs; 4733 let Inst{26-24} = MajOp; 4734 let Inst{21} = MinOp; 4735 let Inst{20-16} = dst; 4736 let Inst{23-22} = !if (!eq(Op, "LO"), imm_value{15-14}, imm_value{31-30}); 4737 let Inst{13-0} = !if (!eq(Op, "LO"), imm_value{13-0}, imm_value{29-16}); 4738 } 4739 4740 let isAsmParserOnly = 1 in { 4741 def LO : REG_IMMED<".l", "LO", 0b0, 0b001, 0b1>; 4742 def LO_H : REG_IMMED<".l", "HI", 0b0, 0b001, 0b1>; 4743 def HI : REG_IMMED<".h", "HI", 0b0, 0b010, 0b1>; 4744 def HI_L : REG_IMMED<".h", "LO", 0b0, 0b010, 0b1>; 4745 } 4746 4747 let isMoveImm = 1, isCodeGenOnly = 1 in 4748 def LO_PIC : ALU32_ri<(outs IntRegs:$dst), (ins bblabel:$label), 4749 "$dst.l = #LO($label@GOTREL)", 4750 []>; 4751 4752 let isMoveImm = 1, isCodeGenOnly = 1 in 4753 def HI_PIC : ALU32_ri<(outs IntRegs:$dst), (ins bblabel:$label), 4754 "$dst.h = #HI($label@GOTREL)", 4755 []>; 4756 4757 let isReMaterializable = 1, isMoveImm = 1, 4758 isCodeGenOnly = 1, hasSideEffects = 0 in 4759 def HI_GOT : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global), 4760 "$dst.h = #HI($global@GOT)", 4761 []>; 4762 4763 let isReMaterializable = 1, isMoveImm = 1, 4764 isCodeGenOnly = 1, hasSideEffects = 0 in 4765 def LO_GOT : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global), 4766 "$dst.l = #LO($global@GOT)", 4767 []>; 4768 4769 let isReMaterializable = 1, isMoveImm = 1, 4770 isCodeGenOnly = 1, hasSideEffects = 0 in 4771 def HI_GOTREL : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global), 4772 "$dst.h = #HI($global@GOTREL)", 4773 []>; 4774 4775 let isReMaterializable = 1, isMoveImm = 1, 4776 isCodeGenOnly = 1, hasSideEffects = 0 in 4777 def LO_GOTREL : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global), 4778 "$dst.l = #LO($global@GOTREL)", 4779 []>; 4780 4781 // This pattern is incorrect. When we add small data, we should change 4782 // this pattern to use memw(#foo). 4783 // This is for sdata. 4784 let isMoveImm = 1, isAsmParserOnly = 1 in 4785 def CONST32 : CONSTLDInst<(outs IntRegs:$dst), (ins globaladdress:$global), 4786 "$dst = CONST32(#$global)", 4787 [(set (i32 IntRegs:$dst), 4788 (load (HexagonCONST32 tglobaltlsaddr:$global)))]>; 4789 4790 let isReMaterializable = 1, isMoveImm = 1, isAsmParserOnly = 1 in 4791 def CONST32_Int_Real : CONSTLDInst<(outs IntRegs:$dst), (ins i32imm:$global), 4792 "$dst = CONST32(#$global)", 4793 [(set (i32 IntRegs:$dst), imm:$global) ]>; 4794 4795 // Map TLS addressses to a CONST32 instruction 4796 def: Pat<(HexagonCONST32 tglobaltlsaddr:$addr), (A2_tfrsi s16Ext:$addr)>; 4797 def: Pat<(HexagonCONST32 bbl:$label), (A2_tfrsi s16Ext:$label)>; 4798 4799 let isReMaterializable = 1, isMoveImm = 1, isAsmParserOnly = 1 in 4800 def CONST64_Int_Real : CONSTLDInst<(outs DoubleRegs:$dst), (ins i64imm:$global), 4801 "$dst = CONST64(#$global)", 4802 [(set (i64 DoubleRegs:$dst), imm:$global)]>; 4803 4804 let hasSideEffects = 0, isReMaterializable = 1, isPseudo = 1, 4805 isCodeGenOnly = 1 in 4806 def TFR_PdTrue : SInst<(outs PredRegs:$dst), (ins), "", 4807 [(set (i1 PredRegs:$dst), 1)]>; 4808 4809 let hasSideEffects = 0, isReMaterializable = 1, isPseudo = 1, 4810 isCodeGenOnly = 1 in 4811 def TFR_PdFalse : SInst<(outs PredRegs:$dst), (ins), "$dst = xor($dst, $dst)", 4812 [(set (i1 PredRegs:$dst), 0)]>; 4813 4814 // Pseudo instructions. 4815 def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>; 4816 def SDT_SPCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, 4817 SDTCisVT<1, i32> ]>; 4818 4819 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart, 4820 [SDNPHasChain, SDNPOutGlue]>; 4821 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd, 4822 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 4823 4824 def SDT_SPCall : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 4825 4826 // For tailcalls a HexagonTCRet SDNode has 3 SDNode Properties - a chain, 4827 // Optional Flag and Variable Arguments. 4828 // Its 1 Operand has pointer type. 4829 def HexagonTCRet : SDNode<"HexagonISD::TC_RETURN", SDT_SPCall, 4830 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 4831 4832 let Defs = [R29, R30], Uses = [R31, R30, R29], isPseudo = 1 in 4833 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt), 4834 ".error \"should not emit\" ", 4835 [(callseq_start timm:$amt)]>; 4836 4837 let Defs = [R29, R30, R31], Uses = [R29], isPseudo = 1 in 4838 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), 4839 ".error \"should not emit\" ", 4840 [(callseq_end timm:$amt1, timm:$amt2)]>; 4841 4842 // Call subroutine indirectly. 4843 let Defs = VolatileV3.Regs in 4844 def J2_callr : JUMPR_MISC_CALLR<0, 1>; 4845 4846 // Indirect tail-call. 4847 let isPseudo = 1, isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0, 4848 isTerminator = 1, isCodeGenOnly = 1 in 4849 def TCRETURNr : T_JMPr; 4850 4851 // Direct tail-calls. 4852 let isPseudo = 1, isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0, 4853 isTerminator = 1, isCodeGenOnly = 1 in 4854 def TCRETURNi : JInst<(outs), (ins calltarget:$dst), "", []>; 4855 4856 //Tail calls. 4857 def: Pat<(HexagonTCRet tglobaladdr:$dst), 4858 (TCRETURNi tglobaladdr:$dst)>; 4859 def: Pat<(HexagonTCRet texternalsym:$dst), 4860 (TCRETURNi texternalsym:$dst)>; 4861 def: Pat<(HexagonTCRet (i32 IntRegs:$dst)), 4862 (TCRETURNr IntRegs:$dst)>; 4863 4864 // Map from r0 = and(r1, 65535) to r0 = zxth(r1) 4865 def: Pat<(and (i32 IntRegs:$src1), 65535), 4866 (A2_zxth IntRegs:$src1)>; 4867 4868 // Map from r0 = and(r1, 255) to r0 = zxtb(r1). 4869 def: Pat<(and (i32 IntRegs:$src1), 255), 4870 (A2_zxtb IntRegs:$src1)>; 4871 4872 // Map Add(p1, true) to p1 = not(p1). 4873 // Add(p1, false) should never be produced, 4874 // if it does, it got to be mapped to NOOP. 4875 def: Pat<(add (i1 PredRegs:$src1), -1), 4876 (C2_not PredRegs:$src1)>; 4877 4878 // Map from p0 = pnot(p0); r0 = mux(p0, #i, #j) => r0 = mux(p0, #j, #i). 4879 def: Pat<(select (not (i1 PredRegs:$src1)), s8ImmPred:$src2, s32ImmPred:$src3), 4880 (C2_muxii PredRegs:$src1, s32ImmPred:$src3, s8ImmPred:$src2)>; 4881 4882 // Map from p0 = pnot(p0); r0 = select(p0, #i, r1) 4883 // => r0 = C2_muxir(p0, r1, #i) 4884 def: Pat<(select (not (i1 PredRegs:$src1)), s32ImmPred:$src2, 4885 (i32 IntRegs:$src3)), 4886 (C2_muxir PredRegs:$src1, IntRegs:$src3, s32ImmPred:$src2)>; 4887 4888 // Map from p0 = pnot(p0); r0 = mux(p0, r1, #i) 4889 // => r0 = C2_muxri (p0, #i, r1) 4890 def: Pat<(select (not (i1 PredRegs:$src1)), IntRegs:$src2, s32ImmPred:$src3), 4891 (C2_muxri PredRegs:$src1, s32ImmPred:$src3, IntRegs:$src2)>; 4892 4893 // Map from p0 = pnot(p0); if (p0) jump => if (!p0) jump. 4894 def: Pat<(brcond (not (i1 PredRegs:$src1)), bb:$offset), 4895 (J2_jumpf PredRegs:$src1, bb:$offset)>; 4896 4897 // Map from Rdd = sign_extend_inreg(Rss, i32) -> Rdd = A2_sxtw(Rss.lo). 4898 def: Pat<(i64 (sext_inreg (i64 DoubleRegs:$src1), i32)), 4899 (A2_sxtw (LoReg DoubleRegs:$src1))>; 4900 4901 // Map from Rdd = sign_extend_inreg(Rss, i16) -> Rdd = A2_sxtw(A2_sxth(Rss.lo)). 4902 def: Pat<(i64 (sext_inreg (i64 DoubleRegs:$src1), i16)), 4903 (A2_sxtw (A2_sxth (LoReg DoubleRegs:$src1)))>; 4904 4905 // Map from Rdd = sign_extend_inreg(Rss, i8) -> Rdd = A2_sxtw(A2_sxtb(Rss.lo)). 4906 def: Pat<(i64 (sext_inreg (i64 DoubleRegs:$src1), i8)), 4907 (A2_sxtw (A2_sxtb (LoReg DoubleRegs:$src1)))>; 4908 4909 // We want to prevent emitting pnot's as much as possible. 4910 // Map brcond with an unsupported setcc to a J2_jumpf. 4911 def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), (i32 IntRegs:$src2))), 4912 bb:$offset), 4913 (J2_jumpf (C2_cmpeq (i32 IntRegs:$src1), (i32 IntRegs:$src2)), 4914 bb:$offset)>; 4915 4916 def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), s10ImmPred:$src2)), 4917 bb:$offset), 4918 (J2_jumpf (C2_cmpeqi (i32 IntRegs:$src1), s10ImmPred:$src2), bb:$offset)>; 4919 4920 def: Pat<(brcond (i1 (setne (i1 PredRegs:$src1), (i1 -1))), bb:$offset), 4921 (J2_jumpf PredRegs:$src1, bb:$offset)>; 4922 4923 def: Pat<(brcond (i1 (setne (i1 PredRegs:$src1), (i1 0))), bb:$offset), 4924 (J2_jumpt PredRegs:$src1, bb:$offset)>; 4925 4926 // cmp.lt(Rs, Imm) -> !cmp.ge(Rs, Imm) -> !cmp.gt(Rs, Imm-1) 4927 def: Pat<(brcond (i1 (setlt (i32 IntRegs:$src1), s8ImmPred:$src2)), bb:$offset), 4928 (J2_jumpf (C2_cmpgti IntRegs:$src1, (DEC_CONST_SIGNED s8ImmPred:$src2)), 4929 bb:$offset)>; 4930 4931 // Map from a 64-bit select to an emulated 64-bit mux. 4932 // Hexagon does not support 64-bit MUXes; so emulate with combines. 4933 def: Pat<(select (i1 PredRegs:$src1), (i64 DoubleRegs:$src2), 4934 (i64 DoubleRegs:$src3)), 4935 (A2_combinew (C2_mux PredRegs:$src1, (HiReg DoubleRegs:$src2), 4936 (HiReg DoubleRegs:$src3)), 4937 (C2_mux PredRegs:$src1, (LoReg DoubleRegs:$src2), 4938 (LoReg DoubleRegs:$src3)))>; 4939 4940 // Map from a 1-bit select to logical ops. 4941 // From LegalizeDAG.cpp: (B1 ? B2 : B3) <=> (B1 & B2)|(!B1&B3). 4942 def: Pat<(select (i1 PredRegs:$src1), (i1 PredRegs:$src2), (i1 PredRegs:$src3)), 4943 (C2_or (C2_and PredRegs:$src1, PredRegs:$src2), 4944 (C2_and (C2_not PredRegs:$src1), PredRegs:$src3))>; 4945 4946 // Map for truncating from 64 immediates to 32 bit immediates. 4947 def: Pat<(i32 (trunc (i64 DoubleRegs:$src))), 4948 (LoReg DoubleRegs:$src)>; 4949 4950 // Map for truncating from i64 immediates to i1 bit immediates. 4951 def: Pat<(i1 (trunc (i64 DoubleRegs:$src))), 4952 (C2_tfrrp (LoReg DoubleRegs:$src))>; 4953 4954 // rs <= rt -> !(rs > rt). 4955 let AddedComplexity = 30 in 4956 def: Pat<(i1 (setle (i32 IntRegs:$src1), s32ImmPred:$src2)), 4957 (C2_not (C2_cmpgti IntRegs:$src1, s32ImmPred:$src2))>; 4958 4959 // rs <= rt -> !(rs > rt). 4960 def : Pat<(i1 (setle (i32 IntRegs:$src1), (i32 IntRegs:$src2))), 4961 (i1 (C2_not (C2_cmpgt (i32 IntRegs:$src1), (i32 IntRegs:$src2))))>; 4962 4963 // Rss <= Rtt -> !(Rss > Rtt). 4964 def: Pat<(i1 (setle (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))), 4965 (C2_not (C2_cmpgtp DoubleRegs:$src1, DoubleRegs:$src2))>; 4966 4967 // Map cmpne -> cmpeq. 4968 // Hexagon_TODO: We should improve on this. 4969 // rs != rt -> !(rs == rt). 4970 let AddedComplexity = 30 in 4971 def: Pat<(i1 (setne (i32 IntRegs:$src1), s32ImmPred:$src2)), 4972 (C2_not (C2_cmpeqi IntRegs:$src1, s32ImmPred:$src2))>; 4973 4974 // Convert setne back to xor for hexagon since we compute w/ pred registers. 4975 def: Pat<(i1 (setne (i1 PredRegs:$src1), (i1 PredRegs:$src2))), 4976 (C2_xor PredRegs:$src1, PredRegs:$src2)>; 4977 4978 // Map cmpne(Rss) -> !cmpew(Rss). 4979 // rs != rt -> !(rs == rt). 4980 def: Pat<(i1 (setne (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))), 4981 (C2_not (C2_cmpeqp DoubleRegs:$src1, DoubleRegs:$src2))>; 4982 4983 // Map cmpge(Rs, Rt) -> !(cmpgt(Rs, Rt). 4984 // rs >= rt -> !(rt > rs). 4985 def : Pat <(i1 (setge (i32 IntRegs:$src1), (i32 IntRegs:$src2))), 4986 (i1 (C2_not (i1 (C2_cmpgt (i32 IntRegs:$src2), (i32 IntRegs:$src1)))))>; 4987 4988 // cmpge(Rs, Imm) -> cmpgt(Rs, Imm-1) 4989 let AddedComplexity = 30 in 4990 def: Pat<(i1 (setge (i32 IntRegs:$src1), s32ImmPred:$src2)), 4991 (C2_cmpgti IntRegs:$src1, (DEC_CONST_SIGNED s32ImmPred:$src2))>; 4992 4993 // Map cmpge(Rss, Rtt) -> !cmpgt(Rtt, Rss). 4994 // rss >= rtt -> !(rtt > rss). 4995 def: Pat<(i1 (setge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))), 4996 (C2_not (C2_cmpgtp DoubleRegs:$src2, DoubleRegs:$src1))>; 4997 4998 // Map cmplt(Rs, Imm) -> !cmpge(Rs, Imm). 4999 // !cmpge(Rs, Imm) -> !cmpgt(Rs, Imm-1). 5000 // rs < rt -> !(rs >= rt). 5001 let AddedComplexity = 30 in 5002 def: Pat<(i1 (setlt (i32 IntRegs:$src1), s32ImmPred:$src2)), 5003 (C2_not (C2_cmpgti IntRegs:$src1, 5004 (DEC_CONST_SIGNED s32ImmPred:$src2)))>; 5005 5006 // Generate cmpgeu(Rs, #0) -> cmpeq(Rs, Rs) 5007 def: Pat<(i1 (setuge (i32 IntRegs:$src1), 0)), 5008 (C2_cmpeq IntRegs:$src1, IntRegs:$src1)>; 5009 5010 // Generate cmpgeu(Rs, #u8) -> cmpgtu(Rs, #u8 -1) 5011 def: Pat<(i1 (setuge (i32 IntRegs:$src1), u32ImmPred:$src2)), 5012 (C2_cmpgtui IntRegs:$src1, (DEC_CONST_UNSIGNED u32ImmPred:$src2))>; 5013 5014 // Generate cmpgtu(Rs, #u9) 5015 def: Pat<(i1 (setugt (i32 IntRegs:$src1), u32ImmPred:$src2)), 5016 (C2_cmpgtui IntRegs:$src1, u32ImmPred:$src2)>; 5017 5018 // Map from Rs >= Rt -> !(Rt > Rs). 5019 // rs >= rt -> !(rt > rs). 5020 def: Pat<(i1 (setuge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))), 5021 (C2_not (C2_cmpgtup DoubleRegs:$src2, DoubleRegs:$src1))>; 5022 5023 // Map from cmpleu(Rss, Rtt) -> !cmpgtu(Rss, Rtt-1). 5024 // Map from (Rs <= Rt) -> !(Rs > Rt). 5025 def: Pat<(i1 (setule (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))), 5026 (C2_not (C2_cmpgtup DoubleRegs:$src1, DoubleRegs:$src2))>; 5027 5028 // Sign extends. 5029 // i1 -> i32 5030 def: Pat<(i32 (sext (i1 PredRegs:$src1))), 5031 (C2_muxii PredRegs:$src1, -1, 0)>; 5032 5033 // i1 -> i64 5034 def: Pat<(i64 (sext (i1 PredRegs:$src1))), 5035 (A2_combinew (A2_tfrsi -1), (C2_muxii PredRegs:$src1, -1, 0))>; 5036 5037 // Zero extends. 5038 // i1 -> i32 5039 def: Pat<(i32 (zext (i1 PredRegs:$src1))), 5040 (C2_muxii PredRegs:$src1, 1, 0)>; 5041 5042 // Map from Rs = Pd to Pd = mux(Pd, #1, #0) 5043 def: Pat<(i32 (anyext (i1 PredRegs:$src1))), 5044 (C2_muxii PredRegs:$src1, 1, 0)>; 5045 5046 // Map from Rss = Pd to Rdd = sxtw (mux(Pd, #1, #0)) 5047 def: Pat<(i64 (anyext (i1 PredRegs:$src1))), 5048 (A2_sxtw (C2_muxii PredRegs:$src1, 1, 0))>; 5049 5050 // Multiply 64-bit unsigned and use upper result. 5051 def : Pat <(mulhu (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)), 5052 (A2_addp 5053 (M2_dpmpyuu_acc_s0 5054 (S2_lsr_i_p 5055 (A2_addp 5056 (M2_dpmpyuu_acc_s0 5057 (S2_lsr_i_p (M2_dpmpyuu_s0 (LoReg $src1), (LoReg $src2)), 32), 5058 (HiReg $src1), 5059 (LoReg $src2)), 5060 (A2_combinew (A2_tfrsi 0), 5061 (LoReg (M2_dpmpyuu_s0 (LoReg $src1), (HiReg $src2))))), 5062 32), 5063 (HiReg $src1), 5064 (HiReg $src2)), 5065 (S2_lsr_i_p (M2_dpmpyuu_s0 (LoReg $src1), (HiReg $src2)), 32) 5066 )>; 5067 5068 // Hexagon specific ISD nodes. 5069 def SDTHexagonALLOCA : SDTypeProfile<1, 2, 5070 [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 5071 def HexagonALLOCA : SDNode<"HexagonISD::ALLOCA", SDTHexagonALLOCA, 5072 [SDNPHasChain]>; 5073 5074 // The reason for the custom inserter is to record all ALLOCA instructions 5075 // in MachineFunctionInfo. 5076 let Defs = [R29], isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 1, 5077 usesCustomInserter = 1 in 5078 def ALLOCA: ALU32Inst<(outs IntRegs:$Rd), 5079 (ins IntRegs:$Rs, u32Imm:$A), "", 5080 [(set (i32 IntRegs:$Rd), 5081 (HexagonALLOCA (i32 IntRegs:$Rs), (i32 imm:$A)))]>; 5082 5083 let isCodeGenOnly = 1, isPseudo = 1, Uses = [R30], hasSideEffects = 0 in 5084 def ALIGNA : ALU32Inst<(outs IntRegs:$Rd), (ins u32Imm:$A), "", []>; 5085 5086 def SDTHexagonARGEXTEND : SDTypeProfile<1, 1, [SDTCisVT<0, i32>]>; 5087 def Hexagon_ARGEXTEND : SDNode<"HexagonISD::ARGEXTEND", SDTHexagonARGEXTEND>; 5088 let isCodeGenOnly = 1 in 5089 def ARGEXTEND : ALU32_rr <(outs IntRegs:$dst), (ins IntRegs:$src1), 5090 "$dst = $src1", 5091 [(set (i32 IntRegs:$dst), 5092 (Hexagon_ARGEXTEND (i32 IntRegs:$src1)))]>; 5093 5094 let AddedComplexity = 100 in 5095 def: Pat<(i32 (sext_inreg (Hexagon_ARGEXTEND (i32 IntRegs:$src1)), i16)), 5096 (i32 IntRegs:$src1)>; 5097 5098 def HexagonJT: SDNode<"HexagonISD::JT", SDTIntUnaryOp>; 5099 def HexagonCP: SDNode<"HexagonISD::CP", SDTIntUnaryOp>; 5100 5101 def: Pat<(HexagonJT tjumptable:$dst), (A2_tfrsi s16Ext:$dst)>; 5102 def: Pat<(HexagonCP tconstpool:$dst), (A2_tfrsi s16Ext:$dst)>; 5103 5104 // XTYPE/SHIFT 5105 // 5106 //===----------------------------------------------------------------------===// 5107 // Template Class 5108 // Shift by immediate/register and accumulate/logical 5109 //===----------------------------------------------------------------------===// 5110 5111 // Rx[+-&|]=asr(Rs,#u5) 5112 // Rx[+-&|^]=lsr(Rs,#u5) 5113 // Rx[+-&|^]=asl(Rs,#u5) 5114 5115 let hasNewValue = 1, opNewValue = 0 in 5116 class T_shift_imm_acc_r <string opc1, string opc2, SDNode OpNode1, 5117 SDNode OpNode2, bits<3> majOp, bits<2> minOp> 5118 : SInst_acc<(outs IntRegs:$Rx), 5119 (ins IntRegs:$src1, IntRegs:$Rs, u5Imm:$u5), 5120 "$Rx "#opc2#opc1#"($Rs, #$u5)", 5121 [(set (i32 IntRegs:$Rx), 5122 (OpNode2 (i32 IntRegs:$src1), 5123 (OpNode1 (i32 IntRegs:$Rs), u5ImmPred:$u5)))], 5124 "$src1 = $Rx", S_2op_tc_2_SLOT23> { 5125 bits<5> Rx; 5126 bits<5> Rs; 5127 bits<5> u5; 5128 5129 let IClass = 0b1000; 5130 5131 let Inst{27-24} = 0b1110; 5132 let Inst{23-22} = majOp{2-1}; 5133 let Inst{13} = 0b0; 5134 let Inst{7} = majOp{0}; 5135 let Inst{6-5} = minOp; 5136 let Inst{4-0} = Rx; 5137 let Inst{20-16} = Rs; 5138 let Inst{12-8} = u5; 5139 } 5140 5141 // Rx[+-&|]=asr(Rs,Rt) 5142 // Rx[+-&|^]=lsr(Rs,Rt) 5143 // Rx[+-&|^]=asl(Rs,Rt) 5144 5145 let hasNewValue = 1, opNewValue = 0 in 5146 class T_shift_reg_acc_r <string opc1, string opc2, SDNode OpNode1, 5147 SDNode OpNode2, bits<2> majOp, bits<2> minOp> 5148 : SInst_acc<(outs IntRegs:$Rx), 5149 (ins IntRegs:$src1, IntRegs:$Rs, IntRegs:$Rt), 5150 "$Rx "#opc2#opc1#"($Rs, $Rt)", 5151 [(set (i32 IntRegs:$Rx), 5152 (OpNode2 (i32 IntRegs:$src1), 5153 (OpNode1 (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))], 5154 "$src1 = $Rx", S_3op_tc_2_SLOT23 > { 5155 bits<5> Rx; 5156 bits<5> Rs; 5157 bits<5> Rt; 5158 5159 let IClass = 0b1100; 5160 5161 let Inst{27-24} = 0b1100; 5162 let Inst{23-22} = majOp; 5163 let Inst{7-6} = minOp; 5164 let Inst{4-0} = Rx; 5165 let Inst{20-16} = Rs; 5166 let Inst{12-8} = Rt; 5167 } 5168 5169 // Rxx[+-&|]=asr(Rss,#u6) 5170 // Rxx[+-&|^]=lsr(Rss,#u6) 5171 // Rxx[+-&|^]=asl(Rss,#u6) 5172 5173 class T_shift_imm_acc_p <string opc1, string opc2, SDNode OpNode1, 5174 SDNode OpNode2, bits<3> majOp, bits<2> minOp> 5175 : SInst_acc<(outs DoubleRegs:$Rxx), 5176 (ins DoubleRegs:$src1, DoubleRegs:$Rss, u6Imm:$u6), 5177 "$Rxx "#opc2#opc1#"($Rss, #$u6)", 5178 [(set (i64 DoubleRegs:$Rxx), 5179 (OpNode2 (i64 DoubleRegs:$src1), 5180 (OpNode1 (i64 DoubleRegs:$Rss), u6ImmPred:$u6)))], 5181 "$src1 = $Rxx", S_2op_tc_2_SLOT23> { 5182 bits<5> Rxx; 5183 bits<5> Rss; 5184 bits<6> u6; 5185 5186 let IClass = 0b1000; 5187 5188 let Inst{27-24} = 0b0010; 5189 let Inst{23-22} = majOp{2-1}; 5190 let Inst{7} = majOp{0}; 5191 let Inst{6-5} = minOp; 5192 let Inst{4-0} = Rxx; 5193 let Inst{20-16} = Rss; 5194 let Inst{13-8} = u6; 5195 } 5196 5197 5198 // Rxx[+-&|]=asr(Rss,Rt) 5199 // Rxx[+-&|^]=lsr(Rss,Rt) 5200 // Rxx[+-&|^]=asl(Rss,Rt) 5201 // Rxx[+-&|^]=lsl(Rss,Rt) 5202 5203 class T_shift_reg_acc_p <string opc1, string opc2, SDNode OpNode1, 5204 SDNode OpNode2, bits<3> majOp, bits<2> minOp> 5205 : SInst_acc<(outs DoubleRegs:$Rxx), 5206 (ins DoubleRegs:$src1, DoubleRegs:$Rss, IntRegs:$Rt), 5207 "$Rxx "#opc2#opc1#"($Rss, $Rt)", 5208 [(set (i64 DoubleRegs:$Rxx), 5209 (OpNode2 (i64 DoubleRegs:$src1), 5210 (OpNode1 (i64 DoubleRegs:$Rss), (i32 IntRegs:$Rt))))], 5211 "$src1 = $Rxx", S_3op_tc_2_SLOT23> { 5212 bits<5> Rxx; 5213 bits<5> Rss; 5214 bits<5> Rt; 5215 5216 let IClass = 0b1100; 5217 5218 let Inst{27-24} = 0b1011; 5219 let Inst{23-21} = majOp; 5220 let Inst{20-16} = Rss; 5221 let Inst{12-8} = Rt; 5222 let Inst{7-6} = minOp; 5223 let Inst{4-0} = Rxx; 5224 } 5225 5226 //===----------------------------------------------------------------------===// 5227 // Multi-class for the shift instructions with logical/arithmetic operators. 5228 //===----------------------------------------------------------------------===// 5229 5230 multiclass xtype_imm_base<string OpcStr1, string OpcStr2, SDNode OpNode1, 5231 SDNode OpNode2, bits<3> majOp, bits<2> minOp > { 5232 def _i_r#NAME : T_shift_imm_acc_r< OpcStr1, OpcStr2, OpNode1, 5233 OpNode2, majOp, minOp >; 5234 def _i_p#NAME : T_shift_imm_acc_p< OpcStr1, OpcStr2, OpNode1, 5235 OpNode2, majOp, minOp >; 5236 } 5237 5238 multiclass xtype_imm_acc<string opc1, SDNode OpNode, bits<2>minOp> { 5239 let AddedComplexity = 100 in 5240 defm _acc : xtype_imm_base< opc1, "+= ", OpNode, add, 0b001, minOp>; 5241 5242 defm _nac : xtype_imm_base< opc1, "-= ", OpNode, sub, 0b000, minOp>; 5243 defm _and : xtype_imm_base< opc1, "&= ", OpNode, and, 0b010, minOp>; 5244 defm _or : xtype_imm_base< opc1, "|= ", OpNode, or, 0b011, minOp>; 5245 } 5246 5247 multiclass xtype_xor_imm_acc<string opc1, SDNode OpNode, bits<2>minOp> { 5248 let AddedComplexity = 100 in 5249 defm _xacc : xtype_imm_base< opc1, "^= ", OpNode, xor, 0b100, minOp>; 5250 } 5251 5252 defm S2_asr : xtype_imm_acc<"asr", sra, 0b00>; 5253 5254 defm S2_lsr : xtype_imm_acc<"lsr", srl, 0b01>, 5255 xtype_xor_imm_acc<"lsr", srl, 0b01>; 5256 5257 defm S2_asl : xtype_imm_acc<"asl", shl, 0b10>, 5258 xtype_xor_imm_acc<"asl", shl, 0b10>; 5259 5260 multiclass xtype_reg_acc_r<string opc1, SDNode OpNode, bits<2>minOp> { 5261 let AddedComplexity = 100 in 5262 def _acc : T_shift_reg_acc_r <opc1, "+= ", OpNode, add, 0b11, minOp>; 5263 5264 def _nac : T_shift_reg_acc_r <opc1, "-= ", OpNode, sub, 0b10, minOp>; 5265 def _and : T_shift_reg_acc_r <opc1, "&= ", OpNode, and, 0b01, minOp>; 5266 def _or : T_shift_reg_acc_r <opc1, "|= ", OpNode, or, 0b00, minOp>; 5267 } 5268 5269 multiclass xtype_reg_acc_p<string opc1, SDNode OpNode, bits<2>minOp> { 5270 let AddedComplexity = 100 in 5271 def _acc : T_shift_reg_acc_p <opc1, "+= ", OpNode, add, 0b110, minOp>; 5272 5273 def _nac : T_shift_reg_acc_p <opc1, "-= ", OpNode, sub, 0b100, minOp>; 5274 def _and : T_shift_reg_acc_p <opc1, "&= ", OpNode, and, 0b010, minOp>; 5275 def _or : T_shift_reg_acc_p <opc1, "|= ", OpNode, or, 0b000, minOp>; 5276 def _xor : T_shift_reg_acc_p <opc1, "^= ", OpNode, xor, 0b011, minOp>; 5277 } 5278 5279 multiclass xtype_reg_acc<string OpcStr, SDNode OpNode, bits<2> minOp > { 5280 defm _r_r : xtype_reg_acc_r <OpcStr, OpNode, minOp>; 5281 defm _r_p : xtype_reg_acc_p <OpcStr, OpNode, minOp>; 5282 } 5283 5284 defm S2_asl : xtype_reg_acc<"asl", shl, 0b10>; 5285 defm S2_asr : xtype_reg_acc<"asr", sra, 0b00>; 5286 defm S2_lsr : xtype_reg_acc<"lsr", srl, 0b01>; 5287 defm S2_lsl : xtype_reg_acc<"lsl", shl, 0b11>; 5288 5289 //===----------------------------------------------------------------------===// 5290 let hasSideEffects = 0 in 5291 class T_S3op_1 <string mnemonic, RegisterClass RC, bits<2> MajOp, bits<3> MinOp, 5292 bit SwapOps, bit isSat = 0, bit isRnd = 0, bit hasShift = 0> 5293 : SInst <(outs RC:$dst), 5294 (ins DoubleRegs:$src1, DoubleRegs:$src2), 5295 "$dst = "#mnemonic#"($src1, $src2)"#!if(isRnd, ":rnd", "") 5296 #!if(hasShift,":>>1","") 5297 #!if(isSat, ":sat", ""), 5298 [], "", S_3op_tc_2_SLOT23 > { 5299 bits<5> dst; 5300 bits<5> src1; 5301 bits<5> src2; 5302 5303 let IClass = 0b1100; 5304 5305 let Inst{27-24} = 0b0001; 5306 let Inst{23-22} = MajOp; 5307 let Inst{20-16} = !if (SwapOps, src2, src1); 5308 let Inst{12-8} = !if (SwapOps, src1, src2); 5309 let Inst{7-5} = MinOp; 5310 let Inst{4-0} = dst; 5311 } 5312 5313 class T_S3op_64 <string mnemonic, bits<2> MajOp, bits<3> MinOp, bit SwapOps, 5314 bit isSat = 0, bit isRnd = 0, bit hasShift = 0 > 5315 : T_S3op_1 <mnemonic, DoubleRegs, MajOp, MinOp, SwapOps, 5316 isSat, isRnd, hasShift>; 5317 5318 let Itinerary = S_3op_tc_1_SLOT23 in { 5319 def S2_shuffeb : T_S3op_64 < "shuffeb", 0b00, 0b010, 0>; 5320 def S2_shuffeh : T_S3op_64 < "shuffeh", 0b00, 0b110, 0>; 5321 def S2_shuffob : T_S3op_64 < "shuffob", 0b00, 0b100, 1>; 5322 def S2_shuffoh : T_S3op_64 < "shuffoh", 0b10, 0b000, 1>; 5323 5324 def S2_vtrunewh : T_S3op_64 < "vtrunewh", 0b10, 0b010, 0>; 5325 def S2_vtrunowh : T_S3op_64 < "vtrunowh", 0b10, 0b100, 0>; 5326 } 5327 5328 def S2_lfsp : T_S3op_64 < "lfs", 0b10, 0b110, 0>; 5329 5330 let hasSideEffects = 0 in 5331 class T_S3op_2 <string mnemonic, bits<3> MajOp, bit SwapOps> 5332 : SInst < (outs DoubleRegs:$Rdd), 5333 (ins DoubleRegs:$Rss, DoubleRegs:$Rtt, PredRegs:$Pu), 5334 "$Rdd = "#mnemonic#"($Rss, $Rtt, $Pu)", 5335 [], "", S_3op_tc_1_SLOT23 > { 5336 bits<5> Rdd; 5337 bits<5> Rss; 5338 bits<5> Rtt; 5339 bits<2> Pu; 5340 5341 let IClass = 0b1100; 5342 5343 let Inst{27-24} = 0b0010; 5344 let Inst{23-21} = MajOp; 5345 let Inst{20-16} = !if (SwapOps, Rtt, Rss); 5346 let Inst{12-8} = !if (SwapOps, Rss, Rtt); 5347 let Inst{6-5} = Pu; 5348 let Inst{4-0} = Rdd; 5349 } 5350 5351 def S2_valignrb : T_S3op_2 < "valignb", 0b000, 1>; 5352 def S2_vsplicerb : T_S3op_2 < "vspliceb", 0b100, 0>; 5353 5354 //===----------------------------------------------------------------------===// 5355 // Template class used by vector shift, vector rotate, vector neg, 5356 // 32-bit shift, 64-bit shifts, etc. 5357 //===----------------------------------------------------------------------===// 5358 5359 let hasSideEffects = 0 in 5360 class T_S3op_3 <string mnemonic, RegisterClass RC, bits<2> MajOp, 5361 bits<2> MinOp, bit isSat = 0, list<dag> pattern = [] > 5362 : SInst <(outs RC:$dst), 5363 (ins RC:$src1, IntRegs:$src2), 5364 "$dst = "#mnemonic#"($src1, $src2)"#!if(isSat, ":sat", ""), 5365 pattern, "", S_3op_tc_1_SLOT23> { 5366 bits<5> dst; 5367 bits<5> src1; 5368 bits<5> src2; 5369 5370 let IClass = 0b1100; 5371 5372 let Inst{27-24} = !if(!eq(!cast<string>(RC), "IntRegs"), 0b0110, 0b0011); 5373 let Inst{23-22} = MajOp; 5374 let Inst{20-16} = src1; 5375 let Inst{12-8} = src2; 5376 let Inst{7-6} = MinOp; 5377 let Inst{4-0} = dst; 5378 } 5379 5380 let hasNewValue = 1 in 5381 class T_S3op_shift32 <string mnemonic, SDNode OpNode, bits<2> MinOp> 5382 : T_S3op_3 <mnemonic, IntRegs, 0b01, MinOp, 0, 5383 [(set (i32 IntRegs:$dst), (OpNode (i32 IntRegs:$src1), 5384 (i32 IntRegs:$src2)))]>; 5385 5386 let hasNewValue = 1, Itinerary = S_3op_tc_2_SLOT23 in 5387 class T_S3op_shift32_Sat <string mnemonic, bits<2> MinOp> 5388 : T_S3op_3 <mnemonic, IntRegs, 0b00, MinOp, 1, []>; 5389 5390 5391 class T_S3op_shift64 <string mnemonic, SDNode OpNode, bits<2> MinOp> 5392 : T_S3op_3 <mnemonic, DoubleRegs, 0b10, MinOp, 0, 5393 [(set (i64 DoubleRegs:$dst), (OpNode (i64 DoubleRegs:$src1), 5394 (i32 IntRegs:$src2)))]>; 5395 5396 5397 class T_S3op_shiftVect <string mnemonic, bits<2> MajOp, bits<2> MinOp> 5398 : T_S3op_3 <mnemonic, DoubleRegs, MajOp, MinOp, 0, []>; 5399 5400 5401 // Shift by register 5402 // Rdd=[asr|lsr|asl|lsl](Rss,Rt) 5403 5404 def S2_asr_r_p : T_S3op_shift64 < "asr", sra, 0b00>; 5405 def S2_lsr_r_p : T_S3op_shift64 < "lsr", srl, 0b01>; 5406 def S2_asl_r_p : T_S3op_shift64 < "asl", shl, 0b10>; 5407 def S2_lsl_r_p : T_S3op_shift64 < "lsl", shl, 0b11>; 5408 5409 // Rd=[asr|lsr|asl|lsl](Rs,Rt) 5410 5411 def S2_asr_r_r : T_S3op_shift32<"asr", sra, 0b00>; 5412 def S2_lsr_r_r : T_S3op_shift32<"lsr", srl, 0b01>; 5413 def S2_asl_r_r : T_S3op_shift32<"asl", shl, 0b10>; 5414 def S2_lsl_r_r : T_S3op_shift32<"lsl", shl, 0b11>; 5415 5416 // Shift by register with saturation 5417 // Rd=asr(Rs,Rt):sat 5418 // Rd=asl(Rs,Rt):sat 5419 5420 let Defs = [USR_OVF] in { 5421 def S2_asr_r_r_sat : T_S3op_shift32_Sat<"asr", 0b00>; 5422 def S2_asl_r_r_sat : T_S3op_shift32_Sat<"asl", 0b10>; 5423 } 5424 5425 let hasNewValue = 1, hasSideEffects = 0 in 5426 class T_S3op_8 <string opc, bits<3> MinOp, bit isSat, bit isRnd, bit hasShift, bit hasSplat = 0> 5427 : SInst < (outs IntRegs:$Rd), 5428 (ins DoubleRegs:$Rss, IntRegs:$Rt), 5429 "$Rd = "#opc#"($Rss, $Rt"#!if(hasSplat, "*", "")#")" 5430 #!if(hasShift, ":<<1", "") 5431 #!if(isRnd, ":rnd", "") 5432 #!if(isSat, ":sat", ""), 5433 [], "", S_3op_tc_1_SLOT23 > { 5434 bits<5> Rd; 5435 bits<5> Rss; 5436 bits<5> Rt; 5437 5438 let IClass = 0b1100; 5439 5440 let Inst{27-24} = 0b0101; 5441 let Inst{20-16} = Rss; 5442 let Inst{12-8} = Rt; 5443 let Inst{7-5} = MinOp; 5444 let Inst{4-0} = Rd; 5445 } 5446 5447 def S2_asr_r_svw_trun : T_S3op_8<"vasrw", 0b010, 0, 0, 0>; 5448 5449 let Defs = [USR_OVF], Itinerary = S_3op_tc_2_SLOT23 in 5450 def S2_vcrotate : T_S3op_shiftVect < "vcrotate", 0b11, 0b00>; 5451 5452 let hasSideEffects = 0 in 5453 class T_S3op_7 <string mnemonic, bit MajOp > 5454 : SInst <(outs DoubleRegs:$Rdd), 5455 (ins DoubleRegs:$Rss, DoubleRegs:$Rtt, u3Imm:$u3), 5456 "$Rdd = "#mnemonic#"($Rss, $Rtt, #$u3)" , 5457 [], "", S_3op_tc_1_SLOT23 > { 5458 bits<5> Rdd; 5459 bits<5> Rss; 5460 bits<5> Rtt; 5461 bits<3> u3; 5462 5463 let IClass = 0b1100; 5464 5465 let Inst{27-24} = 0b0000; 5466 let Inst{23} = MajOp; 5467 let Inst{20-16} = !if(MajOp, Rss, Rtt); 5468 let Inst{12-8} = !if(MajOp, Rtt, Rss); 5469 let Inst{7-5} = u3; 5470 let Inst{4-0} = Rdd; 5471 } 5472 5473 def S2_valignib : T_S3op_7 < "valignb", 0>; 5474 def S2_vspliceib : T_S3op_7 < "vspliceb", 1>; 5475 5476 //===----------------------------------------------------------------------===// 5477 // Template class for 'insert bitfield' instructions 5478 //===----------------------------------------------------------------------===// 5479 let hasSideEffects = 0 in 5480 class T_S3op_insert <string mnemonic, RegisterClass RC> 5481 : SInst <(outs RC:$dst), 5482 (ins RC:$src1, RC:$src2, DoubleRegs:$src3), 5483 "$dst = "#mnemonic#"($src2, $src3)" , 5484 [], "$src1 = $dst", S_3op_tc_1_SLOT23 > { 5485 bits<5> dst; 5486 bits<5> src2; 5487 bits<5> src3; 5488 5489 let IClass = 0b1100; 5490 5491 let Inst{27-26} = 0b10; 5492 let Inst{25-24} = !if(!eq(!cast<string>(RC), "IntRegs"), 0b00, 0b10); 5493 let Inst{23} = 0b0; 5494 let Inst{20-16} = src2; 5495 let Inst{12-8} = src3; 5496 let Inst{4-0} = dst; 5497 } 5498 5499 let hasSideEffects = 0 in 5500 class T_S2op_insert <bits<4> RegTyBits, RegisterClass RC, Operand ImmOp> 5501 : SInst <(outs RC:$dst), (ins RC:$dst2, RC:$src1, ImmOp:$src2, ImmOp:$src3), 5502 "$dst = insert($src1, #$src2, #$src3)", 5503 [], "$dst2 = $dst", S_2op_tc_2_SLOT23> { 5504 bits<5> dst; 5505 bits<5> src1; 5506 bits<6> src2; 5507 bits<6> src3; 5508 bit bit23; 5509 bit bit13; 5510 string ImmOpStr = !cast<string>(ImmOp); 5511 5512 let bit23 = !if (!eq(ImmOpStr, "u6Imm"), src3{5}, 0); 5513 let bit13 = !if (!eq(ImmOpStr, "u6Imm"), src2{5}, 0); 5514 5515 let IClass = 0b1000; 5516 5517 let Inst{27-24} = RegTyBits; 5518 let Inst{23} = bit23; 5519 let Inst{22-21} = src3{4-3}; 5520 let Inst{20-16} = src1; 5521 let Inst{13} = bit13; 5522 let Inst{12-8} = src2{4-0}; 5523 let Inst{7-5} = src3{2-0}; 5524 let Inst{4-0} = dst; 5525 } 5526 5527 // Rx=insert(Rs,Rtt) 5528 // Rx=insert(Rs,#u5,#U5) 5529 let hasNewValue = 1 in { 5530 def S2_insert_rp : T_S3op_insert <"insert", IntRegs>; 5531 def S2_insert : T_S2op_insert <0b1111, IntRegs, u5Imm>; 5532 } 5533 5534 // Rxx=insert(Rss,Rtt) 5535 // Rxx=insert(Rss,#u6,#U6) 5536 def S2_insertp_rp : T_S3op_insert<"insert", DoubleRegs>; 5537 def S2_insertp : T_S2op_insert <0b0011, DoubleRegs, u6Imm>; 5538 5539 5540 def SDTHexagonINSERT: 5541 SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, 5542 SDTCisInt<0>, SDTCisVT<3, i32>, SDTCisVT<4, i32>]>; 5543 def SDTHexagonINSERTRP: 5544 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, 5545 SDTCisInt<0>, SDTCisVT<3, i64>]>; 5546 5547 def HexagonINSERT : SDNode<"HexagonISD::INSERT", SDTHexagonINSERT>; 5548 def HexagonINSERTRP : SDNode<"HexagonISD::INSERTRP", SDTHexagonINSERTRP>; 5549 5550 def: Pat<(HexagonINSERT I32:$Rs, I32:$Rt, u5ImmPred:$u1, u5ImmPred:$u2), 5551 (S2_insert I32:$Rs, I32:$Rt, u5ImmPred:$u1, u5ImmPred:$u2)>; 5552 def: Pat<(HexagonINSERT I64:$Rs, I64:$Rt, u6ImmPred:$u1, u6ImmPred:$u2), 5553 (S2_insertp I64:$Rs, I64:$Rt, u6ImmPred:$u1, u6ImmPred:$u2)>; 5554 def: Pat<(HexagonINSERTRP I32:$Rs, I32:$Rt, I64:$Ru), 5555 (S2_insert_rp I32:$Rs, I32:$Rt, I64:$Ru)>; 5556 def: Pat<(HexagonINSERTRP I64:$Rs, I64:$Rt, I64:$Ru), 5557 (S2_insertp_rp I64:$Rs, I64:$Rt, I64:$Ru)>; 5558 5559 let AddedComplexity = 100 in 5560 def: Pat<(or (or (shl (HexagonINSERT (i32 (zextloadi8 (add I32:$b, 2))), 5561 (i32 (extloadi8 (add I32:$b, 3))), 5562 24, 8), 5563 (i32 16)), 5564 (shl (i32 (zextloadi8 (add I32:$b, 1))), (i32 8))), 5565 (zextloadi8 I32:$b)), 5566 (A2_swiz (L2_loadri_io I32:$b, 0))>; 5567 5568 5569 //===----------------------------------------------------------------------===// 5570 // Template class for 'extract bitfield' instructions 5571 //===----------------------------------------------------------------------===// 5572 let hasNewValue = 1, hasSideEffects = 0 in 5573 class T_S3op_extract <string mnemonic, bits<2> MinOp> 5574 : SInst <(outs IntRegs:$Rd), (ins IntRegs:$Rs, DoubleRegs:$Rtt), 5575 "$Rd = "#mnemonic#"($Rs, $Rtt)", 5576 [], "", S_3op_tc_2_SLOT23 > { 5577 bits<5> Rd; 5578 bits<5> Rs; 5579 bits<5> Rtt; 5580 5581 let IClass = 0b1100; 5582 5583 let Inst{27-22} = 0b100100; 5584 let Inst{20-16} = Rs; 5585 let Inst{12-8} = Rtt; 5586 let Inst{7-6} = MinOp; 5587 let Inst{4-0} = Rd; 5588 } 5589 5590 let hasSideEffects = 0 in 5591 class T_S2op_extract <string mnemonic, bits<4> RegTyBits, 5592 RegisterClass RC, Operand ImmOp> 5593 : SInst <(outs RC:$dst), (ins RC:$src1, ImmOp:$src2, ImmOp:$src3), 5594 "$dst = "#mnemonic#"($src1, #$src2, #$src3)", 5595 [], "", S_2op_tc_2_SLOT23> { 5596 bits<5> dst; 5597 bits<5> src1; 5598 bits<6> src2; 5599 bits<6> src3; 5600 bit bit23; 5601 bit bit13; 5602 string ImmOpStr = !cast<string>(ImmOp); 5603 5604 let bit23 = !if (!eq(ImmOpStr, "u6Imm"), src3{5}, 5605 !if (!eq(mnemonic, "extractu"), 0, 1)); 5606 5607 let bit13 = !if (!eq(ImmOpStr, "u6Imm"), src2{5}, 0); 5608 5609 let IClass = 0b1000; 5610 5611 let Inst{27-24} = RegTyBits; 5612 let Inst{23} = bit23; 5613 let Inst{22-21} = src3{4-3}; 5614 let Inst{20-16} = src1; 5615 let Inst{13} = bit13; 5616 let Inst{12-8} = src2{4-0}; 5617 let Inst{7-5} = src3{2-0}; 5618 let Inst{4-0} = dst; 5619 } 5620 5621 // Extract bitfield 5622 5623 // Rdd=extractu(Rss,Rtt) 5624 // Rdd=extractu(Rss,#u6,#U6) 5625 def S2_extractup_rp : T_S3op_64 < "extractu", 0b00, 0b000, 0>; 5626 def S2_extractup : T_S2op_extract <"extractu", 0b0001, DoubleRegs, u6Imm>; 5627 5628 // Rd=extractu(Rs,Rtt) 5629 // Rd=extractu(Rs,#u5,#U5) 5630 let hasNewValue = 1 in { 5631 def S2_extractu_rp : T_S3op_extract<"extractu", 0b00>; 5632 def S2_extractu : T_S2op_extract <"extractu", 0b1101, IntRegs, u5Imm>; 5633 } 5634 5635 def SDTHexagonEXTRACTU: 5636 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<1>, 5637 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>; 5638 def SDTHexagonEXTRACTURP: 5639 SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<1>, 5640 SDTCisVT<2, i64>]>; 5641 5642 def HexagonEXTRACTU : SDNode<"HexagonISD::EXTRACTU", SDTHexagonEXTRACTU>; 5643 def HexagonEXTRACTURP : SDNode<"HexagonISD::EXTRACTURP", SDTHexagonEXTRACTURP>; 5644 5645 def: Pat<(HexagonEXTRACTU I32:$src1, u5ImmPred:$src2, u5ImmPred:$src3), 5646 (S2_extractu I32:$src1, u5ImmPred:$src2, u5ImmPred:$src3)>; 5647 def: Pat<(HexagonEXTRACTU I64:$src1, u6ImmPred:$src2, u6ImmPred:$src3), 5648 (S2_extractup I64:$src1, u6ImmPred:$src2, u6ImmPred:$src3)>; 5649 def: Pat<(HexagonEXTRACTURP I32:$src1, I64:$src2), 5650 (S2_extractu_rp I32:$src1, I64:$src2)>; 5651 def: Pat<(HexagonEXTRACTURP I64:$src1, I64:$src2), 5652 (S2_extractup_rp I64:$src1, I64:$src2)>; 5653 5654 // Change the sign of the immediate for Rd=-mpyi(Rs,#u8) 5655 def: Pat<(mul (i32 IntRegs:$src1), (ineg n8ImmPred:$src2)), 5656 (M2_mpysin IntRegs:$src1, u8ImmPred:$src2)>; 5657 5658 //===----------------------------------------------------------------------===// 5659 // :raw for of tableindx[bdhw] insns 5660 //===----------------------------------------------------------------------===// 5661 5662 let hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in 5663 class tableidxRaw<string OpStr, bits<2>MinOp> 5664 : SInst <(outs IntRegs:$Rx), 5665 (ins IntRegs:$_dst_, IntRegs:$Rs, u4Imm:$u4, s6Imm:$S6), 5666 "$Rx = "#OpStr#"($Rs, #$u4, #$S6):raw", 5667 [], "$Rx = $_dst_" > { 5668 bits<5> Rx; 5669 bits<5> Rs; 5670 bits<4> u4; 5671 bits<6> S6; 5672 5673 let IClass = 0b1000; 5674 5675 let Inst{27-24} = 0b0111; 5676 let Inst{23-22} = MinOp; 5677 let Inst{21} = u4{3}; 5678 let Inst{20-16} = Rs; 5679 let Inst{13-8} = S6; 5680 let Inst{7-5} = u4{2-0}; 5681 let Inst{4-0} = Rx; 5682 } 5683 5684 def S2_tableidxb : tableidxRaw<"tableidxb", 0b00>; 5685 def S2_tableidxh : tableidxRaw<"tableidxh", 0b01>; 5686 def S2_tableidxw : tableidxRaw<"tableidxw", 0b10>; 5687 def S2_tableidxd : tableidxRaw<"tableidxd", 0b11>; 5688 5689 //===----------------------------------------------------------------------===// 5690 // Template class for 'table index' instructions which are assembler mapped 5691 // to their :raw format. 5692 //===----------------------------------------------------------------------===// 5693 let isPseudo = 1 in 5694 class tableidx_goodsyntax <string mnemonic> 5695 : SInst <(outs IntRegs:$Rx), 5696 (ins IntRegs:$_dst_, IntRegs:$Rs, u4Imm:$u4, u5Imm:$u5), 5697 "$Rx = "#mnemonic#"($Rs, #$u4, #$u5)", 5698 [], "$Rx = $_dst_" >; 5699 5700 def S2_tableidxb_goodsyntax : tableidx_goodsyntax<"tableidxb">; 5701 def S2_tableidxh_goodsyntax : tableidx_goodsyntax<"tableidxh">; 5702 def S2_tableidxw_goodsyntax : tableidx_goodsyntax<"tableidxw">; 5703 def S2_tableidxd_goodsyntax : tableidx_goodsyntax<"tableidxd">; 5704 5705 //===----------------------------------------------------------------------===// 5706 // V3 Instructions + 5707 //===----------------------------------------------------------------------===// 5708 5709 include "HexagonInstrInfoV3.td" 5710 5711 //===----------------------------------------------------------------------===// 5712 // V3 Instructions - 5713 //===----------------------------------------------------------------------===// 5714 5715 //===----------------------------------------------------------------------===// 5716 // V4 Instructions + 5717 //===----------------------------------------------------------------------===// 5718 5719 include "HexagonInstrInfoV4.td" 5720 5721 //===----------------------------------------------------------------------===// 5722 // V4 Instructions - 5723 //===----------------------------------------------------------------------===// 5724 5725 //===----------------------------------------------------------------------===// 5726 // V5 Instructions + 5727 //===----------------------------------------------------------------------===// 5728 5729 include "HexagonInstrInfoV5.td" 5730 5731 //===----------------------------------------------------------------------===// 5732 // V5 Instructions - 5733 //===----------------------------------------------------------------------===// 5734 5735 //===----------------------------------------------------------------------===// 5736 // V60 Instructions + 5737 //===----------------------------------------------------------------------===// 5738 5739 include "HexagonInstrInfoV60.td" 5740 5741 //===----------------------------------------------------------------------===// 5742 // V60 Instructions - 5743 //===----------------------------------------------------------------------===// 5744 5745 //===----------------------------------------------------------------------===// 5746 // ALU32/64/Vector + 5747 //===----------------------------------------------------------------------===/// 5748 5749 include "HexagonInstrInfoVector.td" 5750 5751 include "HexagonInstrAlias.td" 5752 include "HexagonSystemInst.td" 5753 5754
