1 //=- MicroMips32r6InstrFormats.td - Mips32r6 Instruction Formats -*- tablegen -*-==// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes microMIPS32r6 instruction formats. 11 // 12 //===----------------------------------------------------------------------===// 13 14 class MMR6Arch<string opstr> { 15 string Arch = "micromipsr6"; 16 string BaseOpcode = opstr; 17 string DecoderNamespace = "MicroMipsR6"; 18 } 19 20 // Class used for microMIPS32r6 and microMIPS64r6 instructions. 21 class MicroMipsR6Inst16 : PredicateControl { 22 string DecoderNamespace = "MicroMipsR6"; 23 let InsnPredicates = [HasMicroMips32r6]; 24 } 25 26 //===----------------------------------------------------------------------===// 27 // 28 // Disambiguators 29 // 30 //===----------------------------------------------------------------------===// 31 // 32 // Some encodings are ambiguous except by comparing field values. 33 34 class MMDecodeDisambiguatedBy<string Name> : DecodeDisambiguates<Name> { 35 string DecoderNamespace = "MicroMipsR6_Ambiguous"; 36 } 37 38 //===----------------------------------------------------------------------===// 39 // 40 // Encoding Formats 41 // 42 //===----------------------------------------------------------------------===// 43 44 class BC16_FM_MM16R6 { 45 bits<10> offset; 46 47 bits<16> Inst; 48 49 let Inst{15-10} = 0x33; 50 let Inst{9-0} = offset; 51 } 52 53 class BEQZC_BNEZC_FM_MM16R6<bits<6> op> : MicroMipsR6Inst16 { 54 bits<3> rs; 55 bits<7> offset; 56 57 bits<16> Inst; 58 59 let Inst{15-10} = op; 60 let Inst{9-7} = rs; 61 let Inst{6-0} = offset; 62 } 63 64 class POOL16C_JALRC_FM_MM16R6<bits<5> op> { 65 bits<5> rs; 66 67 bits<16> Inst; 68 69 let Inst{15-10} = 0x11; 70 let Inst{9-5} = rs; 71 let Inst{4-0} = op; 72 } 73 74 class POP35_BOVC_FM_MMR6<string instr_asm> : MipsR6Inst, MMR6Arch<instr_asm> { 75 bits<5> rt; 76 bits<5> rs; 77 bits<16> offset; 78 79 bits<32> Inst; 80 81 let Inst{31-26} = 0b011101; 82 let Inst{25-21} = rt; 83 let Inst{20-16} = rs; 84 let Inst{15-0} = offset; 85 } 86 87 class POP37_BNVC_FM_MMR6<string instr_asm> : MipsR6Inst, MMR6Arch<instr_asm> { 88 bits<5> rt; 89 bits<5> rs; 90 bits<16> offset; 91 92 bits<32> Inst; 93 94 let Inst{31-26} = 0b011111; 95 let Inst{25-21} = rt; 96 let Inst{20-16} = rs; 97 let Inst{15-0} = offset; 98 } 99 100 class POOL16C_JRCADDIUSP_FM_MM16R6<bits<5> op> { 101 bits<5> imm; 102 103 bits<16> Inst; 104 105 let Inst{15-10} = 0x11; 106 let Inst{9-5} = imm; 107 let Inst{4-0} = op; 108 } 109 110 class POOL16C_LWM_SWM_FM_MM16R6<bits<4> funct> { 111 bits<2> rt; 112 bits<4> addr; 113 114 bits<16> Inst; 115 116 let Inst{15-10} = 0x11; 117 let Inst{9-8} = rt; 118 let Inst{7-4} = addr; 119 let Inst{3-0} = funct; 120 } 121 122 class POOL32A_BITSWAP_FM_MMR6<bits<6> funct> : MipsR6Inst { 123 bits<5> rd; 124 bits<5> rt; 125 126 bits<32> Inst; 127 128 let Inst{31-26} = 0b000000; 129 let Inst{25-21} = rt; 130 let Inst{20-16} = rd; 131 let Inst{15-12} = 0b0000; 132 let Inst{11-6} = funct; 133 let Inst{5-0} = 0b111100; 134 } 135 136 class CACHE_PREF_FM_MMR6<bits<6> opgroup, bits<4> funct> : MipsR6Inst { 137 bits<21> addr; 138 bits<5> hint; 139 140 bits<32> Inst; 141 142 let Inst{31-26} = opgroup; 143 let Inst{25-21} = hint; 144 let Inst{20-16} = addr{20-16}; 145 let Inst{15-12} = funct; 146 let Inst{11-0} = addr{11-0}; 147 } 148 149 class ARITH_FM_MMR6<string instr_asm, bits<10> funct> : MMR6Arch<instr_asm> { 150 bits<5> rd; 151 bits<5> rt; 152 bits<5> rs; 153 154 bits<32> Inst; 155 156 let Inst{31-26} = 0; 157 let Inst{25-21} = rt; 158 let Inst{20-16} = rs; 159 let Inst{15-11} = rd; 160 let Inst{10} = 0; 161 let Inst{9-0} = funct; 162 } 163 164 class ADDI_FM_MMR6<string instr_asm, bits<6> op> : MMR6Arch<instr_asm> { 165 bits<5> rt; 166 bits<5> rs; 167 bits<16> imm16; 168 169 bits<32> Inst; 170 171 let Inst{31-26} = op; 172 let Inst{25-21} = rt; 173 let Inst{20-16} = rs; 174 let Inst{15-0} = imm16; 175 } 176 177 class POOL32C_ST_EVA_FM_MMR6<bits<6> op, bits<3> funct> : MipsR6Inst { 178 bits<21> addr; 179 bits<5> hint; 180 bits<5> base = addr{20-16}; 181 bits<9> offset = addr{8-0}; 182 183 bits<32> Inst; 184 185 let Inst{31-26} = op; 186 let Inst{25-21} = hint; 187 let Inst{20-16} = base; 188 let Inst{15-12} = 0b1010; 189 let Inst{11-9} = funct; 190 let Inst{8-0} = offset; 191 } 192 193 class LB32_FM_MMR6 : MipsR6Inst { 194 bits<21> addr; 195 bits<5> rt; 196 bits<5> base = addr{20-16}; 197 bits<16> offset = addr{15-0}; 198 199 bits<32> Inst; 200 201 let Inst{31-26} = 0b000111; 202 let Inst{25-21} = rt; 203 let Inst{20-16} = base; 204 let Inst{15-0} = offset; 205 } 206 207 class LBU32_FM_MMR6 : MipsR6Inst { 208 bits<21> addr; 209 bits<5> rt; 210 bits<5> base = addr{20-16}; 211 bits<16> offset = addr{15-0}; 212 213 bits<32> Inst; 214 215 let Inst{31-26} = 0b000101; 216 let Inst{25-21} = rt; 217 let Inst{20-16} = base; 218 let Inst{15-0} = offset; 219 } 220 221 class POOL32C_LB_LBU_FM_MMR6<bits<3> funct> : MipsR6Inst { 222 bits<21> addr; 223 bits<5> rt; 224 225 bits<32> Inst; 226 227 let Inst{31-26} = 0b011000; 228 let Inst{25-21} = rt; 229 let Inst{20-16} = addr{20-16}; 230 let Inst{15-12} = 0b0110; 231 let Inst{11-9} = funct; 232 let Inst{8-0} = addr{8-0}; 233 } 234 235 class SIGN_EXTEND_FM_MMR6<string instr_asm, bits<10> funct> 236 : MMR6Arch<instr_asm> { 237 bits<5> rd; 238 bits<5> rt; 239 240 bits<32> Inst; 241 242 let Inst{31-26} = 0b000000; 243 let Inst{25-21} = rd; 244 let Inst{20-16} = rt; 245 let Inst{15-6} = funct; 246 let Inst{5-0} = 0b111100; 247 } 248 249 class PCREL19_FM_MMR6<bits<2> funct> : MipsR6Inst { 250 bits<5> rt; 251 bits<19> imm; 252 253 bits<32> Inst; 254 255 let Inst{31-26} = 0b011110; 256 let Inst{25-21} = rt; 257 let Inst{20-19} = funct; 258 let Inst{18-0} = imm; 259 } 260 261 class PCREL16_FM_MMR6<bits<5> funct> : MipsR6Inst { 262 bits<5> rt; 263 bits<16> imm; 264 265 bits<32> Inst; 266 267 let Inst{31-26} = 0b011110; 268 let Inst{25-21} = rt; 269 let Inst{20-16} = funct; 270 let Inst{15-0} = imm; 271 } 272 273 class POOL32A_FM_MMR6<bits<10> funct> : MipsR6Inst { 274 bits<5> rd; 275 bits<5> rs; 276 bits<5> rt; 277 278 bits<32> Inst; 279 280 let Inst{31-26} = 0b000000; 281 let Inst{25-21} = rt; 282 let Inst{20-16} = rs; 283 let Inst{15-11} = rd; 284 let Inst{10} = 0; 285 let Inst{9-0} = funct; 286 } 287 288 class POOL32A_PAUSE_FM_MMR6<string instr_asm, bits<5> op> : MMR6Arch<instr_asm> { 289 bits<32> Inst; 290 291 let Inst{31-26} = 0; 292 let Inst{25-21} = 0; 293 let Inst{20-16} = 0; 294 let Inst{15-11} = op; 295 let Inst{10-6} = 0; 296 let Inst{5-0} = 0; 297 } 298 299 class POOL32A_RDPGPR_FM_MMR6<bits<10> funct> { 300 bits<5> rt; 301 bits<5> rd; 302 bits<32> Inst; 303 304 let Inst{31-26} = 0; 305 let Inst{25-21} = rt; 306 let Inst{20-16} = rd; 307 let Inst{15-6} = funct; 308 let Inst{5-0} = 0b111100; 309 } 310 311 class POOL32A_RDHWR_FM_MMR6 { 312 bits<5> rt; 313 bits<5> rs; 314 bits<3> sel; 315 bits<32> Inst; 316 317 let Inst{31-26} = 0; 318 let Inst{25-21} = rt; 319 let Inst{20-16} = rs; 320 let Inst{15-14} = 0; 321 let Inst{13-11} = sel; 322 let Inst{10} = 0; 323 let Inst{9-0} = 0b0111000000; 324 } 325 326 class POOL32A_SYNC_FM_MMR6 { 327 bits<5> stype; 328 329 bits<32> Inst; 330 331 let Inst{31-26} = 0; 332 let Inst{25-21} = 0; 333 let Inst{20-16} = stype; 334 let Inst{15-6} = 0b0110101101; 335 let Inst{5-0} = 0b111100; 336 } 337 338 class POOL32I_SYNCI_FM_MMR6 { 339 bits<21> addr; 340 bits<5> base = addr{20-16}; 341 bits<16> immediate = addr{15-0}; 342 343 bits<32> Inst; 344 345 let Inst{31-26} = 0b010000; 346 let Inst{25-21} = 0b01100; 347 let Inst{20-16} = base; 348 let Inst{15-0} = immediate; 349 } 350 351 class POOL32A_2R_FM_MMR6<bits<10> funct> : MipsR6Inst { 352 bits<5> rs; 353 bits<5> rt; 354 355 bits<32> Inst; 356 357 let Inst{31-26} = 0b000000; 358 let Inst{25-21} = rt; 359 let Inst{20-16} = rs; 360 let Inst{15-6} = funct; 361 let Inst{5-0} = 0b111100; 362 } 363 364 class SPECIAL_2R_FM_MMR6<bits<6> funct> : MipsR6Inst { 365 bits<5> rs; 366 bits<5> rt; 367 368 bits<32> Inst; 369 370 let Inst{31-26} = 0b000000; 371 let Inst{25-21} = rs; 372 let Inst{20-16} = 0b00000; 373 let Inst{15-11} = rt; 374 let Inst{10-6} = 0b00001; 375 let Inst{5-0} = funct; 376 } 377 378 class POOL32A_ALIGN_FM_MMR6<bits<6> funct> : MipsR6Inst { 379 bits<5> rd; 380 bits<5> rs; 381 bits<5> rt; 382 bits<2> bp; 383 384 bits<32> Inst; 385 386 let Inst{31-26} = 0b000000; 387 let Inst{25-21} = rs; 388 let Inst{20-16} = rt; 389 let Inst{15-11} = rd; 390 let Inst{10-9} = bp; 391 let Inst{8-6} = 0b000; 392 let Inst{5-0} = funct; 393 } 394 395 class AUI_FM_MMR6 : MipsR6Inst { 396 bits<5> rs; 397 bits<5> rt; 398 bits<16> imm; 399 400 bits<32> Inst; 401 402 let Inst{31-26} = 0b000100; 403 let Inst{25-21} = rt; 404 let Inst{20-16} = rs; 405 let Inst{15-0} = imm; 406 } 407 408 class POOL32A_LSA_FM<bits<6> funct> : MipsR6Inst { 409 bits<5> rd; 410 bits<5> rs; 411 bits<5> rt; 412 bits<2> imm2; 413 414 bits<32> Inst; 415 416 let Inst{31-26} = 0b000000; 417 let Inst{25-21} = rt; 418 let Inst{20-16} = rs; 419 let Inst{15-11} = rd; 420 let Inst{10-9} = imm2; 421 let Inst{8-6} = 0b000; 422 let Inst{5-0} = funct; 423 } 424 425 class SB32_SH32_STORE_FM_MMR6<bits<6> op> { 426 bits<5> rt; 427 bits<21> addr; 428 bits<5> base = addr{20-16}; 429 bits<16> offset = addr{15-0}; 430 431 bits<32> Inst; 432 433 let Inst{31-26} = op; 434 let Inst{25-21} = rt; 435 let Inst{20-16} = base; 436 let Inst{15-0} = offset; 437 } 438 439 class POOL32C_STORE_EVA_FM_MMR6<bits<3> funct> { 440 bits<5> rt; 441 bits<21> addr; 442 bits<5> base = addr{20-16}; 443 bits<9> offset = addr{8-0}; 444 445 bits<32> Inst; 446 447 let Inst{31-26} = 0b011000; 448 let Inst{25-21} = rt; 449 let Inst{20-16} = base; 450 let Inst{15-12} = 0b1010; 451 let Inst{11-9} = funct; 452 let Inst{8-0} = offset; 453 } 454 455 class LOAD_WORD_EVA_FM_MMR6<bits<3> funct> { 456 bits<5> rt; 457 bits<21> addr; 458 bits<5> base = addr{20-16}; 459 bits<9> offset = addr{8-0}; 460 461 bits<32> Inst; 462 463 let Inst{31-26} = 0b011000; 464 let Inst{25-21} = rt; 465 let Inst{20-16} = base; 466 let Inst{15-12} = 0b0110; 467 let Inst{11-9} = funct; 468 let Inst{8-0} = offset; 469 } 470 471 class LOAD_WORD_FM_MMR6 { 472 bits<5> rt; 473 bits<21> addr; 474 bits<5> base = addr{20-16}; 475 bits<16> offset = addr{15-0}; 476 477 bits<32> Inst; 478 479 let Inst{31-26} = 0b111111; 480 let Inst{25-21} = rt; 481 let Inst{20-16} = base; 482 let Inst{15-0} = offset; 483 } 484 485 class LOAD_UPPER_IMM_FM_MMR6 { 486 bits<5> rt; 487 bits<16> imm16; 488 489 bits<32> Inst; 490 491 let Inst{31-26} = 0b000100; 492 let Inst{25-21} = rt; 493 let Inst{20-16} = 0; 494 let Inst{15-0} = imm16; 495 } 496 497 class CMP_BRANCH_1R_RT_OFF16_FM_MMR6<string instr_asm, bits<6> funct> 498 : MMR6Arch<instr_asm>, MipsR6Inst { 499 bits<5> rt; 500 bits<16> offset; 501 502 bits<32> Inst; 503 504 let Inst{31-26} = funct; 505 let Inst{25-21} = rt; 506 let Inst{20-16} = 0b00000; 507 let Inst{15-0} = offset; 508 } 509 510 class CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<string instr_asm, bits<6> funct> 511 : MMR6Arch<instr_asm>, MipsR6Inst { 512 bits<5> rt; 513 bits<16> offset; 514 515 bits<32> Inst; 516 517 let Inst{31-26} = funct; 518 let Inst{25-21} = rt; 519 let Inst{20-16} = rt; 520 let Inst{15-0} = offset; 521 } 522 523 class POOL32A_JALRC_FM_MMR6<string instr_asm, bits<10> funct> 524 : MipsR6Inst, MMR6Arch<instr_asm> { 525 bits<5> rt; 526 bits<5> rs; 527 528 bits<32> Inst; 529 530 let Inst{31-26} = 0; 531 let Inst{25-21} = rt; 532 let Inst{20-16} = rs; 533 let Inst{15-6} = funct; 534 let Inst{5-0} = 0b111100; 535 } 536 537 class POOL32A_EXT_INS_FM_MMR6<string instr_asm, bits<6> funct> 538 : MMR6Arch<instr_asm>, MipsR6Inst { 539 bits<5> rt; 540 bits<5> rs; 541 bits<5> size; 542 bits<5> pos; 543 544 bits<32> Inst; 545 546 let Inst{31-26} = 0; 547 let Inst{25-21} = rt; 548 let Inst{20-16} = rs; 549 let Inst{15-11} = size; 550 let Inst{10-6} = pos; 551 let Inst{5-0} = funct; 552 } 553 554 class POOL32A_ERET_FM_MMR6<string instr_asm, bits<10> funct> 555 : MMR6Arch<instr_asm> { 556 bits<32> Inst; 557 558 let Inst{31-26} = 0x00; 559 let Inst{25-16} = 0x00; 560 let Inst{15-6} = funct; 561 let Inst{5-0} = 0x3c; 562 } 563 564 class ERETNC_FM_MMR6<string instr_asm> : MMR6Arch<instr_asm> { 565 bits<32> Inst; 566 567 let Inst{31-26} = 0x00; 568 let Inst{25-17} = 0x00; 569 let Inst{16-16} = 0x01; 570 let Inst{15-6} = 0x3cd; 571 let Inst{5-0} = 0x3c; 572 } 573 574 class BREAK_MMR6_ENC<string instr_asm> : MMR6Arch<instr_asm> { 575 bits<10> code_1; 576 bits<10> code_2; 577 bits<32> Inst; 578 let Inst{31-26} = 0x0; 579 let Inst{25-16} = code_1; 580 let Inst{15-6} = code_2; 581 let Inst{5-0} = 0x07; 582 } 583 584 class BARRIER_MMR6_ENC<string instr_asm, bits<5> op> : MMR6Arch<instr_asm> { 585 bits<32> Inst; 586 587 let Inst{31-26} = 0x0; 588 let Inst{25-21} = 0x0; 589 let Inst{20-16} = 0x0; 590 let Inst{15-11} = op; 591 let Inst{10-6} = 0x0; 592 let Inst{5-0} = 0x0; 593 } 594 595 class POOL32A_EIDI_MMR6_ENC<string instr_asm, bits<10> funct> 596 : MMR6Arch<instr_asm> { 597 bits<32> Inst; 598 bits<5> rt; // Actually rs but we're sharing code with the standard encodings which call it rt 599 600 let Inst{31-26} = 0x00; 601 let Inst{25-21} = 0x00; 602 let Inst{20-16} = rt; 603 let Inst{15-6} = funct; 604 let Inst{5-0} = 0x3c; 605 } 606 607 class SHIFT_MMR6_ENC<string instr_asm, bits<10> funct, bit rotate> : MMR6Arch<instr_asm> { 608 bits<5> rd; 609 bits<5> rt; 610 bits<5> shamt; 611 612 bits<32> Inst; 613 614 let Inst{31-26} = 0; 615 let Inst{25-21} = rd; 616 let Inst{20-16} = rt; 617 let Inst{15-11} = shamt; 618 let Inst{10} = rotate; 619 let Inst{9-0} = funct; 620 } 621 622 class SW32_FM_MMR6<string instr_asm, bits<6> op> : MMR6Arch<instr_asm> { 623 bits<5> rt; 624 bits<21> addr; 625 626 bits<32> Inst; 627 628 let Inst{31-26} = op; 629 let Inst{25-21} = rt; 630 let Inst{20-16} = addr{20-16}; 631 let Inst{15-0} = addr{15-0}; 632 } 633 634 class POOL32C_SWE_FM_MMR6<string instr_asm, bits<6> op, bits<4> fmt, 635 bits<3> funct> : MMR6Arch<instr_asm> { 636 bits<5> rt; 637 bits<21> addr; 638 bits<5> base = addr{20-16}; 639 bits<9> offset = addr{8-0}; 640 641 bits<32> Inst; 642 643 let Inst{31-26} = op; 644 let Inst{25-21} = rt; 645 let Inst{20-16} = base; 646 let Inst{15-12} = fmt; 647 let Inst{11-9} = funct; 648 let Inst{8-0} = offset; 649 } 650 651 class POOL32F_ARITH_FM_MMR6<string instr_asm, bits<2> fmt, bits<8> funct> 652 : MMR6Arch<instr_asm>, MipsR6Inst { 653 bits<5> ft; 654 bits<5> fs; 655 bits<5> fd; 656 657 bits<32> Inst; 658 659 let Inst{31-26} = 0b010101; 660 let Inst{25-21} = ft; 661 let Inst{20-16} = fs; 662 let Inst{15-11} = fd; 663 let Inst{10} = 0; 664 let Inst{9-8} = fmt; 665 let Inst{7-0} = funct; 666 } 667 668 class POOL32F_ARITHF_FM_MMR6<string instr_asm, bits<2> fmt, bits<9> funct> 669 : MMR6Arch<instr_asm>, MipsR6Inst { 670 bits<5> ft; 671 bits<5> fs; 672 bits<5> fd; 673 674 bits<32> Inst; 675 676 let Inst{31-26} = 0b010101; 677 let Inst{25-21} = ft; 678 let Inst{20-16} = fs; 679 let Inst{15-11} = fd; 680 let Inst{10-9} = fmt; 681 let Inst{8-0} = funct; 682 } 683 684 class POOL32F_MOV_NEG_FM_MMR6<string instr_asm, bits<2> fmt, bits<7> funct> 685 : MMR6Arch<instr_asm>, MipsR6Inst { 686 bits<5> ft; 687 bits<5> fs; 688 689 bits<32> Inst; 690 691 let Inst{31-26} = 0b010101; 692 let Inst{25-21} = ft; 693 let Inst{20-16} = fs; 694 let Inst{15} = 0; 695 let Inst{14-13} = fmt; 696 let Inst{12-6} = funct; 697 let Inst{5-0} = 0b111011; 698 } 699 700 class POOL32F_MINMAX_FM<string instr_asm, bits<2> fmt, bits<9> funct> 701 : MMR6Arch<instr_asm>, MipsR6Inst { 702 bits<5> ft; 703 bits<5> fs; 704 bits<5> fd; 705 706 bits<32> Inst; 707 708 let Inst{31-26} = 0b010101; 709 let Inst{25-21} = ft; 710 let Inst{20-16} = fs; 711 let Inst{15-11} = fd; 712 let Inst{10-9} = fmt; 713 let Inst{8-0} = funct; 714 } 715 716 class POOL32F_CMP_FM<string instr_asm, bits<6> format, FIELD_CMP_COND Cond> 717 : MMR6Arch<instr_asm>, MipsR6Inst { 718 bits<5> ft; 719 bits<5> fs; 720 bits<5> fd; 721 722 bits<32> Inst; 723 724 let Inst{31-26} = 0b010101; 725 let Inst{25-21} = ft; 726 let Inst{20-16} = fs; 727 let Inst{15-11} = fd; 728 let Inst{10-6} = Cond.Value; 729 let Inst{5-0} = format; 730 } 731 732 class POOL32F_CVT_LW_FM<string instr_asm, bit fmt, bits<8> funct> 733 : MMR6Arch<instr_asm>, MipsR6Inst { 734 bits<5> ft; 735 bits<5> fs; 736 737 bits<32> Inst; 738 let Inst{31-26} = 0b010101; 739 let Inst{25-21} = ft; 740 let Inst{20-16} = fs; 741 let Inst{15} = 0; 742 let Inst{14} = fmt; 743 let Inst{13-6} = funct; 744 let Inst{5-0} = 0b111011; 745 } 746 747 class POOL32F_CVT_DS_FM<string instr_asm, bits<2> fmt, bits<7> funct> 748 : MMR6Arch<instr_asm>, MipsR6Inst { 749 bits<5> ft; 750 bits<5> fs; 751 752 bits<32> Inst; 753 let Inst{31-26} = 0b010101; 754 let Inst{25-21} = ft; 755 let Inst{20-16} = fs; 756 let Inst{15} = 0; 757 let Inst{14-13} = fmt; 758 let Inst{12-6} = funct; 759 let Inst{5-0} = 0b111011; 760 } 761 762 class POOL32F_ABS_FM_MMR6<string instr_asm, bits<2> fmt, bits<7> funct> 763 : MMR6Arch<instr_asm>, MipsR6Inst { 764 bits<5> ft; 765 bits<5> fs; 766 767 bits<32> Inst; 768 769 let Inst{31-26} = 0b010101; 770 let Inst{25-21} = ft; 771 let Inst{20-16} = fs; 772 let Inst{15} = 0; 773 let Inst{14-13} = fmt; 774 let Inst{12-6} = funct; 775 let Inst{5-0} = 0b111011; 776 } 777 778 class POOL32F_MATH_FM_MMR6<string instr_asm, bits<1> fmt, bits<8> funct> 779 : MMR6Arch<instr_asm>, MipsR6Inst { 780 bits<5> ft; 781 bits<5> fs; 782 783 bits<32> Inst; 784 785 let Inst{31-26} = 0b010101; 786 let Inst{25-21} = ft; 787 let Inst{20-16} = fs; 788 let Inst{15} = 0; 789 let Inst{14} = fmt; 790 let Inst{13-6} = funct; 791 let Inst{5-0} = 0b111011; 792 } 793 794 class POOL16A_ADDU16_FM_MMR6 : MicroMipsR6Inst16 { 795 bits<3> rs; 796 bits<3> rt; 797 bits<3> rd; 798 799 bits<16> Inst; 800 801 let Inst{15-10} = 0b000001; 802 let Inst{9-7} = rs; 803 let Inst{6-4} = rt; 804 let Inst{3-1} = rd; 805 let Inst{0} = 0; 806 } 807 808 class POOL16C_AND16_FM_MMR6 : MicroMipsR6Inst16 { 809 bits<3> rt; 810 bits<3> rs; 811 812 bits<16> Inst; 813 814 let Inst{15-10} = 0b010001; 815 let Inst{9-7} = rt; 816 let Inst{6-4} = rs; 817 let Inst{3-0} = 0b0001; 818 } 819 820 class POOL16C_NOT16_FM_MMR6 : MicroMipsR6Inst16 { 821 bits<3> rt; 822 bits<3> rs; 823 824 bits<16> Inst; 825 826 let Inst{15-10} = 0x11; 827 let Inst{9-7} = rt; 828 let Inst{6-4} = rs; 829 let Inst{3-0} = 0b0000; 830 } 831 832 class POOL16C_OR16_XOR16_FM_MMR6<bits<4> op> : MicroMipsR6Inst16 { 833 bits<3> rt; 834 bits<3> rs; 835 836 bits<16> Inst; 837 838 let Inst{15-10} = 0b010001; 839 let Inst{9-7} = rt; 840 let Inst{6-4} = rs; 841 let Inst{3-0} = op; 842 } 843 844 class POOL16C_BREAKPOINT_FM_MMR6<bits<6> op> { 845 bits<4> code_; 846 bits<16> Inst; 847 848 let Inst{15-10} = 0b010001; 849 let Inst{9-6} = code_; 850 let Inst{5-0} = op; 851 } 852 853 class POOL16A_SUBU16_FM_MMR6 { 854 bits<3> rs; 855 bits<3> rt; 856 bits<3> rd; 857 858 bits<16> Inst; 859 860 let Inst{15-10} = 0b000001; 861 let Inst{9-7} = rs; 862 let Inst{6-4} = rt; 863 let Inst{3-1} = rd; 864 let Inst{0} = 0b1; 865 } 866 867 class POOL32A_WRPGPR_WSBH_FM_MMR6<bits<10> funct> : MipsR6Inst { 868 bits<5> rt; 869 bits<5> rs; 870 871 bits<32> Inst; 872 873 let Inst{31-26} = 0x00; 874 let Inst{25-21} = rt; 875 let Inst{20-16} = rs; 876 let Inst{15-6} = funct; 877 let Inst{5-0} = 0x3c; 878 } 879 880 class POOL32F_RECIP_ROUND_FM_MMR6<string instr_asm, bits<1> fmt, bits<8> funct> 881 : MMR6Arch<instr_asm>, MipsR6Inst { 882 bits<5> ft; 883 bits<5> fs; 884 885 bits<32> Inst; 886 887 let Inst{31-26} = 0b010101; 888 let Inst{25-21} = ft; 889 let Inst{20-16} = fs; 890 let Inst{15} = 0; 891 let Inst{14} = fmt; 892 let Inst{13-6} = funct; 893 let Inst{5-0} = 0b111011; 894 } 895 896 class POOL32F_RINT_FM_MMR6<string instr_asm, bits<2> fmt> 897 : MMR6Arch<instr_asm>, MipsR6Inst { 898 bits<5> fs; 899 bits<5> fd; 900 901 bits<32> Inst; 902 903 let Inst{31-26} = 0b010101; 904 let Inst{25-21} = fs; 905 let Inst{20-16} = fd; 906 let Inst{15-11} = 0; 907 let Inst{10-9} = fmt; 908 let Inst{8-0} = 0b000100000; 909 } 910 911 class POOL32F_SEL_FM_MMR6<string instr_asm, bits<2> fmt, bits<9> funct> 912 : MMR6Arch<instr_asm>, MipsR6Inst { 913 bits<5> ft; 914 bits<5> fs; 915 bits<5> fd; 916 917 bits<32> Inst; 918 919 let Inst{31-26} = 0b010101; 920 let Inst{25-21} = ft; 921 let Inst{20-16} = fs; 922 let Inst{15-11} = fd; 923 let Inst{10-9} = fmt; 924 let Inst{8-0} = funct; 925 } 926 927 class POOL32F_CLASS_FM_MMR6<string instr_asm, bits<2> fmt, bits<9> funct> 928 : MMR6Arch<instr_asm>, MipsR6Inst { 929 bits<5> fs; 930 bits<5> fd; 931 932 bits<32> Inst; 933 934 let Inst{31-26} = 0b010101; 935 let Inst{25-21} = fs; 936 let Inst{20-16} = fd; 937 let Inst{15-11} = 0b00000; 938 let Inst{10-9} = fmt; 939 let Inst{8-0} = funct; 940 } 941 942 class POOL32A_TLBINV_FM_MMR6<string instr_asm, bits<10> funct> 943 : MMR6Arch<instr_asm>, MipsR6Inst { 944 bits<32> Inst; 945 946 let Inst{31-26} = 0x0; 947 let Inst{25-16} = 0x0; 948 let Inst{15-6} = funct; 949 let Inst{5-0} = 0b111100; 950 } 951 952 class POOL32A_MFTC0_FM_MMR6<string instr_asm, bits<5> funct, bits<6> opcode> 953 : MMR6Arch<instr_asm>, MipsR6Inst { 954 bits<5> rt; 955 bits<5> rs; 956 bits<3> sel; 957 958 bits<32> Inst; 959 960 let Inst{31-26} = 0b000000; 961 let Inst{25-21} = rt; 962 let Inst{20-16} = rs; 963 let Inst{15-14} = 0; 964 let Inst{13-11} = sel; 965 let Inst{10-6} = funct; 966 let Inst{5-0} = opcode; 967 } 968 969 class POOL32F_MFTC1_FM_MMR6<string instr_asm, bits<8> funct> 970 : MMR6Arch<instr_asm> { 971 bits<5> rt; 972 bits<5> fs; 973 974 bits<32> Inst; 975 976 let Inst{31-26} = 0b010101; 977 let Inst{25-21} = rt; 978 let Inst{20-16} = fs; 979 let Inst{15-14} = 0; 980 let Inst{13-6} = funct; 981 let Inst{5-0} = 0b111011; 982 } 983 984 class POOL32A_MFTC2_FM_MMR6<string instr_asm, bits<10> funct> 985 : MMR6Arch<instr_asm>, MipsR6Inst { 986 bits<5> rt; 987 bits<5> impl; 988 989 bits<32> Inst; 990 991 let Inst{31-26} = 0b000000; 992 let Inst{25-21} = rt; 993 let Inst{20-16} = impl; 994 let Inst{15-6} = funct; 995 let Inst{5-0} = 0b111100; 996 } 997 998 class CMP_BRANCH_2R_OFF16_FM_MMR6<string opstr, bits<6> funct> 999 : MipsR6Inst, MMR6Arch<opstr> { 1000 bits<5> rt; 1001 bits<5> rs; 1002 bits<16> offset; 1003 1004 bits<32> Inst; 1005 1006 let Inst{31-26} = funct; 1007 let Inst{25-21} = rt; 1008 let Inst{20-16} = rs; 1009 let Inst{15-0} = offset; 1010 } 1011 1012 class POOL32A_DVPEVP_FM_MMR6<string instr_asm, bits<10> funct> 1013 : MMR6Arch<instr_asm>, MipsR6Inst { 1014 bits<5> rs; 1015 1016 bits<32> Inst; 1017 1018 let Inst{31-26} = 0b000000; 1019 let Inst{25-21} = 0b00000; 1020 let Inst{20-16} = rs; 1021 let Inst{15-6} = funct; 1022 let Inst{5-0} = 0b111100; 1023 } 1024 1025 class POOL32B_LWP_SWP_FM_MMR6<bits<4> funct> : MipsR6Inst { 1026 bits<5> rd; 1027 bits<21> addr; 1028 bits<5> base = addr{20-16}; 1029 bits<12> offset = addr{11-0}; 1030 1031 bits<32> Inst; 1032 1033 let Inst{31-26} = 0x8; 1034 let Inst{25-21} = rd; 1035 let Inst{20-16} = base; 1036 let Inst{15-12} = funct; 1037 let Inst{11-0} = offset; 1038 } 1039 1040 class CMP_BRANCH_OFF21_FM_MMR6<string opstr, bits<6> funct> : MipsR6Inst { 1041 bits<5> rs; 1042 bits<21> offset; 1043 1044 bits<32> Inst; 1045 1046 let Inst{31-26} = funct; 1047 let Inst{25-21} = rs; 1048 let Inst{20-0} = offset; 1049 } 1050 1051 class POOL32I_BRANCH_COP_1_2_FM_MMR6<string instr_asm, bits<5> funct> 1052 : MMR6Arch<instr_asm> { 1053 bits<5> rt; 1054 bits<16> offset; 1055 1056 bits<32> Inst; 1057 1058 let Inst{31-26} = 0b010000; 1059 let Inst{25-21} = funct; 1060 let Inst{20-16} = rt; 1061 let Inst{15-0} = offset; 1062 } 1063 1064 class LDWC1_SDWC1_FM_MMR6<string instr_asm, bits<6> funct> 1065 : MMR6Arch<instr_asm> { 1066 bits<5> ft; 1067 bits<21> addr; 1068 bits<5> base = addr{20-16}; 1069 bits<16> offset = addr{15-0}; 1070 1071 bits<32> Inst; 1072 1073 let Inst{31-26} = funct; 1074 let Inst{25-21} = ft; 1075 let Inst{20-16} = base; 1076 let Inst{15-0} = offset; 1077 } 1078 1079 class POOL32B_LDWC2_SDWC2_FM_MMR6<string instr_asm, bits<4> funct> 1080 : MMR6Arch<instr_asm>, MipsR6Inst { 1081 bits<5> rt; 1082 bits<21> addr; 1083 bits<5> base = addr{20-16}; 1084 bits<11> offset = addr{10-0}; 1085 1086 bits<32> Inst; 1087 1088 let Inst{31-26} = 0b001000; 1089 let Inst{25-21} = rt; 1090 let Inst{20-16} = base; 1091 let Inst{15-12} = funct; 1092 let Inst{11} = 0; 1093 let Inst{10-0} = offset; 1094 } 1095
