1 //=- Mips32r6InstrInfo.td - Mips32r6 Instruction Information -*- tablegen -*-=// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes Mips32r6 instructions. 11 // 12 //===----------------------------------------------------------------------===// 13 14 include "Mips32r6InstrFormats.td" 15 16 // Notes about removals/changes from MIPS32r6: 17 // Reencoded: jr -> jalr 18 // Reencoded: jr.hb -> jalr.hb 19 20 def brtarget21 : Operand<OtherVT> { 21 let EncoderMethod = "getBranchTarget21OpValue"; 22 let OperandType = "OPERAND_PCREL"; 23 let DecoderMethod = "DecodeBranchTarget21"; 24 let ParserMatchClass = MipsJumpTargetAsmOperand; 25 } 26 27 def brtarget26 : Operand<OtherVT> { 28 let EncoderMethod = "getBranchTarget26OpValue"; 29 let OperandType = "OPERAND_PCREL"; 30 let DecoderMethod = "DecodeBranchTarget26"; 31 let ParserMatchClass = MipsJumpTargetAsmOperand; 32 } 33 34 def jmpoffset16 : Operand<OtherVT> { 35 let EncoderMethod = "getJumpOffset16OpValue"; 36 let ParserMatchClass = MipsJumpTargetAsmOperand; 37 } 38 39 def calloffset16 : Operand<iPTR> { 40 let EncoderMethod = "getJumpOffset16OpValue"; 41 let ParserMatchClass = MipsJumpTargetAsmOperand; 42 } 43 44 //===----------------------------------------------------------------------===// 45 // 46 // Instruction Encodings 47 // 48 //===----------------------------------------------------------------------===// 49 50 class ADDIUPC_ENC : PCREL19_FM<OPCODE2_ADDIUPC>; 51 class ALIGN_ENC : SPECIAL3_ALIGN_FM<OPCODE6_ALIGN>; 52 class ALUIPC_ENC : PCREL16_FM<OPCODE5_ALUIPC>; 53 class AUI_ENC : AUI_FM; 54 class AUIPC_ENC : PCREL16_FM<OPCODE5_AUIPC>; 55 56 class BAL_ENC : BAL_FM; 57 class BALC_ENC : BRANCH_OFF26_FM<0b111010>; 58 class BC_ENC : BRANCH_OFF26_FM<0b110010>; 59 class BEQC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_ADDI>, 60 DecodeDisambiguates<"AddiGroupBranch">; 61 class BEQZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_ADDI>, 62 DecodeDisambiguatedBy<"DaddiGroupBranch">; 63 class BNEC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_DADDI>, 64 DecodeDisambiguates<"DaddiGroupBranch">; 65 class BNEZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_DADDI>, 66 DecodeDisambiguatedBy<"DaddiGroupBranch">; 67 68 class BLTZC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BGTZL>, 69 DecodeDisambiguates<"BgtzlGroupBranch">; 70 class BGEC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_BLEZL>, 71 DecodeDisambiguatedBy<"BlezlGroupBranch">; 72 class BGEUC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_BLEZ>, 73 DecodeDisambiguatedBy<"BlezGroupBranch">; 74 class BGEZC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BLEZL>, 75 DecodeDisambiguates<"BlezlGroupBranch">; 76 class BGTZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BGTZ>, 77 DecodeDisambiguatedBy<"BgtzGroupBranch">; 78 79 class BLTC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_BGTZL>, 80 DecodeDisambiguatedBy<"BgtzlGroupBranch">; 81 class BLTUC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_BGTZ>, 82 DecodeDisambiguatedBy<"BgtzGroupBranch">; 83 84 class BLEZC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BLEZL>, 85 DecodeDisambiguatedBy<"BlezlGroupBranch">; 86 class BLTZALC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BGTZ>, 87 DecodeDisambiguates<"BgtzGroupBranch">; 88 class BGTZC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BGTZL>, 89 DecodeDisambiguatedBy<"BgtzlGroupBranch">; 90 91 class BEQZC_ENC : CMP_BRANCH_OFF21_FM<0b110110>; 92 class BGEZALC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BLEZ>, 93 DecodeDisambiguates<"BlezGroupBranch">; 94 class BNEZC_ENC : CMP_BRANCH_OFF21_FM<0b111110>; 95 96 class BC1EQZ_ENC : COP1_BCCZ_FM<OPCODE5_BC1EQZ>; 97 class BC1NEZ_ENC : COP1_BCCZ_FM<OPCODE5_BC1NEZ>; 98 class BC2EQZ_ENC : COP2_BCCZ_FM<OPCODE5_BC2EQZ>; 99 class BC2NEZ_ENC : COP2_BCCZ_FM<OPCODE5_BC2NEZ>; 100 101 class JIALC_ENC : JMP_IDX_COMPACT_FM<0b111110>; 102 class JIC_ENC : JMP_IDX_COMPACT_FM<0b110110>; 103 class JR_HB_R6_ENC : JR_HB_R6_FM<OPCODE6_JALR>; 104 class BITSWAP_ENC : SPECIAL3_2R_FM<OPCODE6_BITSWAP>; 105 class BLEZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BLEZ>, 106 DecodeDisambiguatedBy<"BlezGroupBranch">; 107 class BNVC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_DADDI>, 108 DecodeDisambiguatedBy<"DaddiGroupBranch">; 109 class BOVC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_ADDI>, 110 DecodeDisambiguatedBy<"AddiGroupBranch">; 111 class DIV_ENC : SPECIAL_3R_FM<0b00010, 0b011010>; 112 class DIVU_ENC : SPECIAL_3R_FM<0b00010, 0b011011>; 113 class MOD_ENC : SPECIAL_3R_FM<0b00011, 0b011010>; 114 class MODU_ENC : SPECIAL_3R_FM<0b00011, 0b011011>; 115 class MUH_ENC : SPECIAL_3R_FM<0b00011, 0b011000>; 116 class MUHU_ENC : SPECIAL_3R_FM<0b00011, 0b011001>; 117 class MUL_R6_ENC : SPECIAL_3R_FM<0b00010, 0b011000>; 118 class MULU_ENC : SPECIAL_3R_FM<0b00010, 0b011001>; 119 120 class MADDF_S_ENC : COP1_3R_FM<0b011000, FIELD_FMT_S>; 121 class MADDF_D_ENC : COP1_3R_FM<0b011000, FIELD_FMT_D>; 122 class MSUBF_S_ENC : COP1_3R_FM<0b011001, FIELD_FMT_S>; 123 class MSUBF_D_ENC : COP1_3R_FM<0b011001, FIELD_FMT_D>; 124 125 class SEL_D_ENC : COP1_3R_FM<0b010000, FIELD_FMT_D>; 126 class SEL_S_ENC : COP1_3R_FM<0b010000, FIELD_FMT_S>; 127 128 class SELEQZ_ENC : SPECIAL_3R_FM<0b00000, 0b110101>; 129 class SELNEZ_ENC : SPECIAL_3R_FM<0b00000, 0b110111>; 130 131 class LWPC_ENC : PCREL19_FM<OPCODE2_LWPC>; 132 class LWUPC_ENC : PCREL19_FM<OPCODE2_LWUPC>; 133 134 class MAX_S_ENC : COP1_3R_FM<0b011101, FIELD_FMT_S>; 135 class MAX_D_ENC : COP1_3R_FM<0b011101, FIELD_FMT_D>; 136 class MIN_S_ENC : COP1_3R_FM<0b011100, FIELD_FMT_S>; 137 class MIN_D_ENC : COP1_3R_FM<0b011100, FIELD_FMT_D>; 138 139 class MAXA_S_ENC : COP1_3R_FM<0b011111, FIELD_FMT_S>; 140 class MAXA_D_ENC : COP1_3R_FM<0b011111, FIELD_FMT_D>; 141 class MINA_S_ENC : COP1_3R_FM<0b011110, FIELD_FMT_S>; 142 class MINA_D_ENC : COP1_3R_FM<0b011110, FIELD_FMT_D>; 143 144 class SELEQZ_S_ENC : COP1_3R_FM<0b010100, FIELD_FMT_S>; 145 class SELEQZ_D_ENC : COP1_3R_FM<0b010100, FIELD_FMT_D>; 146 class SELNEZ_S_ENC : COP1_3R_FM<0b010111, FIELD_FMT_S>; 147 class SELNEZ_D_ENC : COP1_3R_FM<0b010111, FIELD_FMT_D>; 148 149 class RINT_S_ENC : COP1_2R_FM<0b011010, FIELD_FMT_S>; 150 class RINT_D_ENC : COP1_2R_FM<0b011010, FIELD_FMT_D>; 151 class CLASS_S_ENC : COP1_2R_FM<0b011011, FIELD_FMT_S>; 152 class CLASS_D_ENC : COP1_2R_FM<0b011011, FIELD_FMT_D>; 153 154 class CACHE_ENC : SPECIAL3_MEM_FM<OPCODE6_CACHE>; 155 class PREF_ENC : SPECIAL3_MEM_FM<OPCODE6_PREF>; 156 157 class LDC2_R6_ENC : COP2LDST_FM<OPCODE5_LDC2>; 158 class LWC2_R6_ENC : COP2LDST_FM<OPCODE5_LWC2>; 159 class SDC2_R6_ENC : COP2LDST_FM<OPCODE5_SDC2>; 160 class SWC2_R6_ENC : COP2LDST_FM<OPCODE5_SWC2>; 161 162 class LSA_R6_ENC : SPECIAL_LSA_FM<OPCODE6_LSA>; 163 164 class LL_R6_ENC : SPECIAL3_LL_SC_FM<OPCODE6_LL>; 165 class SC_R6_ENC : SPECIAL3_LL_SC_FM<OPCODE6_SC>; 166 167 class CLO_R6_ENC : SPECIAL_2R_FM<OPCODE6_CLO>; 168 class CLZ_R6_ENC : SPECIAL_2R_FM<OPCODE6_CLZ>; 169 170 class SDBBP_R6_ENC : SPECIAL_SDBBP_FM; 171 172 //===----------------------------------------------------------------------===// 173 // 174 // Instruction Multiclasses 175 // 176 //===----------------------------------------------------------------------===// 177 178 class CMP_CONDN_DESC_BASE<string CondStr, string Typestr, 179 RegisterOperand FGROpnd, 180 SDPatternOperator Op = null_frag> { 181 dag OutOperandList = (outs FGRCCOpnd:$fd); 182 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft); 183 string AsmString = !strconcat("cmp.", CondStr, ".", Typestr, "\t$fd, $fs, $ft"); 184 list<dag> Pattern = [(set FGRCCOpnd:$fd, (Op FGROpnd:$fs, FGROpnd:$ft))]; 185 bit isCTI = 1; 186 } 187 188 multiclass CMP_CC_M <FIELD_CMP_FORMAT Format, string Typestr, 189 RegisterOperand FGROpnd>{ 190 let AdditionalPredicates = [NotInMicroMips] in { 191 def CMP_F_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_AF>, 192 CMP_CONDN_DESC_BASE<"af", Typestr, FGROpnd>, 193 MipsR6Arch<!strconcat("cmp.af.", Typestr)>, 194 ISA_MIPS32R6, HARDFLOAT; 195 def CMP_UN_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_UN>, 196 CMP_CONDN_DESC_BASE<"un", Typestr, FGROpnd, setuo>, 197 MipsR6Arch<!strconcat("cmp.un.", Typestr)>, 198 ISA_MIPS32R6, HARDFLOAT; 199 def CMP_EQ_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_EQ>, 200 CMP_CONDN_DESC_BASE<"eq", Typestr, FGROpnd, setoeq>, 201 MipsR6Arch<!strconcat("cmp.eq.", Typestr)>, 202 ISA_MIPS32R6, HARDFLOAT; 203 def CMP_UEQ_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format, 204 FIELD_CMP_COND_UEQ>, 205 CMP_CONDN_DESC_BASE<"ueq", Typestr, FGROpnd, setueq>, 206 MipsR6Arch<!strconcat("cmp.ueq.", Typestr)>, 207 ISA_MIPS32R6, HARDFLOAT; 208 def CMP_LT_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_LT>, 209 CMP_CONDN_DESC_BASE<"lt", Typestr, FGROpnd, setolt>, 210 MipsR6Arch<!strconcat("cmp.lt.", Typestr)>, 211 ISA_MIPS32R6, HARDFLOAT; 212 def CMP_ULT_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format, 213 FIELD_CMP_COND_ULT>, 214 CMP_CONDN_DESC_BASE<"ult", Typestr, FGROpnd, setult>, 215 MipsR6Arch<!strconcat("cmp.ult.", Typestr)>, 216 ISA_MIPS32R6, HARDFLOAT; 217 def CMP_LE_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_LE>, 218 CMP_CONDN_DESC_BASE<"le", Typestr, FGROpnd, setole>, 219 MipsR6Arch<!strconcat("cmp.le.", Typestr)>, 220 ISA_MIPS32R6, HARDFLOAT; 221 def CMP_ULE_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format, 222 FIELD_CMP_COND_ULE>, 223 CMP_CONDN_DESC_BASE<"ule", Typestr, FGROpnd, setule>, 224 MipsR6Arch<!strconcat("cmp.ule.", Typestr)>, 225 ISA_MIPS32R6, HARDFLOAT; 226 def CMP_SAF_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format, 227 FIELD_CMP_COND_SAF>, 228 CMP_CONDN_DESC_BASE<"saf", Typestr, FGROpnd>, 229 MipsR6Arch<!strconcat("cmp.saf.", Typestr)>, 230 ISA_MIPS32R6, HARDFLOAT; 231 def CMP_SUN_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format, 232 FIELD_CMP_COND_SUN>, 233 CMP_CONDN_DESC_BASE<"sun", Typestr, FGROpnd>, 234 MipsR6Arch<!strconcat("cmp.sun.", Typestr)>, 235 ISA_MIPS32R6, HARDFLOAT; 236 def CMP_SEQ_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format, 237 FIELD_CMP_COND_SEQ>, 238 CMP_CONDN_DESC_BASE<"seq", Typestr, FGROpnd>, 239 MipsR6Arch<!strconcat("cmp.seq.", Typestr)>, 240 ISA_MIPS32R6, HARDFLOAT; 241 def CMP_SUEQ_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format, 242 FIELD_CMP_COND_SUEQ>, 243 CMP_CONDN_DESC_BASE<"sueq", Typestr, FGROpnd>, 244 MipsR6Arch<!strconcat("cmp.sueq.", Typestr)>, 245 ISA_MIPS32R6, HARDFLOAT; 246 def CMP_SLT_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format, 247 FIELD_CMP_COND_SLT>, 248 CMP_CONDN_DESC_BASE<"slt", Typestr, FGROpnd>, 249 MipsR6Arch<!strconcat("cmp.slt.", Typestr)>, 250 ISA_MIPS32R6, HARDFLOAT; 251 def CMP_SULT_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format, 252 FIELD_CMP_COND_SULT>, 253 CMP_CONDN_DESC_BASE<"sult", Typestr, FGROpnd>, 254 MipsR6Arch<!strconcat("cmp.sult.", Typestr)>, 255 ISA_MIPS32R6, HARDFLOAT; 256 def CMP_SLE_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format, 257 FIELD_CMP_COND_SLE>, 258 CMP_CONDN_DESC_BASE<"sle", Typestr, FGROpnd>, 259 MipsR6Arch<!strconcat("cmp.sle.", Typestr)>, 260 ISA_MIPS32R6, HARDFLOAT; 261 def CMP_SULE_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format, 262 FIELD_CMP_COND_SULE>, 263 CMP_CONDN_DESC_BASE<"sule", Typestr, FGROpnd>, 264 MipsR6Arch<!strconcat("cmp.sule.", Typestr)>, 265 ISA_MIPS32R6, HARDFLOAT; 266 } 267 } 268 269 //===----------------------------------------------------------------------===// 270 // 271 // Instruction Descriptions 272 // 273 //===----------------------------------------------------------------------===// 274 275 class PCREL_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, 276 Operand ImmOpnd, InstrItinClass itin> 277 : MipsR6Arch<instr_asm> { 278 dag OutOperandList = (outs GPROpnd:$rs); 279 dag InOperandList = (ins ImmOpnd:$imm); 280 string AsmString = !strconcat(instr_asm, "\t$rs, $imm"); 281 list<dag> Pattern = []; 282 InstrItinClass Itinerary = itin; 283 } 284 285 class ADDIUPC_DESC : PCREL_DESC_BASE<"addiupc", GPR32Opnd, simm19_lsl2, 286 II_ADDIUPC>; 287 class LWPC_DESC: PCREL_DESC_BASE<"lwpc", GPR32Opnd, simm19_lsl2, II_LWPC>; 288 class LWUPC_DESC: PCREL_DESC_BASE<"lwupc", GPR32Opnd, simm19_lsl2, II_LWUPC>; 289 290 class ALIGN_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, 291 Operand ImmOpnd, InstrItinClass itin> 292 : MipsR6Arch<instr_asm> { 293 dag OutOperandList = (outs GPROpnd:$rd); 294 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$bp); 295 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $bp"); 296 list<dag> Pattern = []; 297 InstrItinClass Itinerary = itin; 298 } 299 300 class ALIGN_DESC : ALIGN_DESC_BASE<"align", GPR32Opnd, uimm2, II_ALIGN>; 301 302 class ALUIPC_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, 303 InstrItinClass itin = NoItinerary> 304 : MipsR6Arch<instr_asm> { 305 dag OutOperandList = (outs GPROpnd:$rs); 306 dag InOperandList = (ins simm16:$imm); 307 string AsmString = !strconcat(instr_asm, "\t$rs, $imm"); 308 list<dag> Pattern = []; 309 InstrItinClass Itinerary = itin; 310 } 311 312 class ALUIPC_DESC : ALUIPC_DESC_BASE<"aluipc", GPR32Opnd, II_ALUIPC>; 313 class AUIPC_DESC : ALUIPC_DESC_BASE<"auipc", GPR32Opnd, II_AUIPC>; 314 315 class AUI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, 316 InstrItinClass itin = NoItinerary> 317 : MipsR6Arch<instr_asm> { 318 dag OutOperandList = (outs GPROpnd:$rs); 319 dag InOperandList = (ins GPROpnd:$rt, simm16:$imm); 320 string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $imm"); 321 list<dag> Pattern = []; 322 InstrItinClass Itinerary = itin; 323 } 324 325 class AUI_DESC : AUI_DESC_BASE<"aui", GPR32Opnd, II_AUI>; 326 327 class BRANCH_DESC_BASE { 328 bit isBranch = 1; 329 bit isTerminator = 1; 330 bit hasDelaySlot = 0; 331 bit isCTI = 1; 332 } 333 334 class BC_DESC_BASE<string instr_asm, DAGOperand opnd> : BRANCH_DESC_BASE, 335 MipsR6Arch<instr_asm> { 336 dag InOperandList = (ins opnd:$offset); 337 dag OutOperandList = (outs); 338 string AsmString = !strconcat(instr_asm, "\t$offset"); 339 bit isBarrier = 1; 340 InstrItinClass Itinerary = II_BC; 341 bit isCTI = 1; 342 } 343 344 class CMP_BC_DESC_BASE<string instr_asm, DAGOperand opnd, 345 RegisterOperand GPROpnd> : BRANCH_DESC_BASE, 346 MipsR6Arch<instr_asm> { 347 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, opnd:$offset); 348 dag OutOperandList = (outs); 349 string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $offset"); 350 list<Register> Defs = [AT]; 351 InstrItinClass Itinerary = II_BCCC; 352 bit hasForbiddenSlot = 1; 353 bit isCTI = 1; 354 } 355 356 class CMP_CBR_EQNE_Z_DESC_BASE<string instr_asm, DAGOperand opnd, 357 RegisterOperand GPROpnd> 358 : BRANCH_DESC_BASE, MipsR6Arch<instr_asm> { 359 dag InOperandList = (ins GPROpnd:$rs, opnd:$offset); 360 dag OutOperandList = (outs); 361 string AsmString = !strconcat(instr_asm, "\t$rs, $offset"); 362 list<Register> Defs = [AT]; 363 InstrItinClass Itinerary = II_BCCZC; 364 bit hasForbiddenSlot = 1; 365 bit isCTI = 1; 366 } 367 368 class CMP_CBR_RT_Z_DESC_BASE<string instr_asm, DAGOperand opnd, 369 RegisterOperand GPROpnd> 370 : BRANCH_DESC_BASE, MipsR6Arch<instr_asm> { 371 dag InOperandList = (ins GPROpnd:$rt, opnd:$offset); 372 dag OutOperandList = (outs); 373 string AsmString = !strconcat(instr_asm, "\t$rt, $offset"); 374 list<Register> Defs = [AT]; 375 InstrItinClass Itinerary = II_BCCZC; 376 bit hasForbiddenSlot = 1; 377 bit isCTI = 1; 378 } 379 380 class BAL_DESC : BC_DESC_BASE<"bal", brtarget> { 381 bit isCall = 1; 382 bit hasDelaySlot = 1; 383 list<Register> Defs = [RA]; 384 bit isCTI = 1; 385 } 386 387 class BALC_DESC : BC_DESC_BASE<"balc", brtarget26> { 388 bit isCall = 1; 389 list<Register> Defs = [RA]; 390 InstrItinClass Itinerary = II_BALC; 391 bit isCTI = 1; 392 } 393 394 class BC_DESC : BC_DESC_BASE<"bc", brtarget26>; 395 class BGEC_DESC : CMP_BC_DESC_BASE<"bgec", brtarget, GPR32Opnd>; 396 class BGEUC_DESC : CMP_BC_DESC_BASE<"bgeuc", brtarget, GPR32Opnd>; 397 class BEQC_DESC : CMP_BC_DESC_BASE<"beqc", brtarget, GPR32Opnd>; 398 class BNEC_DESC : CMP_BC_DESC_BASE<"bnec", brtarget, GPR32Opnd>; 399 400 class BLTC_DESC : CMP_BC_DESC_BASE<"bltc", brtarget, GPR32Opnd>; 401 class BLTUC_DESC : CMP_BC_DESC_BASE<"bltuc", brtarget, GPR32Opnd>; 402 403 class BLTZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bltzc", brtarget, GPR32Opnd>; 404 class BGEZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgezc", brtarget, GPR32Opnd>; 405 406 class BLEZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"blezc", brtarget, GPR32Opnd>; 407 class BGTZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgtzc", brtarget, GPR32Opnd>; 408 409 class BEQZC_DESC : CMP_CBR_EQNE_Z_DESC_BASE<"beqzc", brtarget21, GPR32Opnd>; 410 class BNEZC_DESC : CMP_CBR_EQNE_Z_DESC_BASE<"bnezc", brtarget21, GPR32Opnd>; 411 412 class COP1_BCCZ_DESC_BASE<string instr_asm> : BRANCH_DESC_BASE { 413 dag InOperandList = (ins FGR64Opnd:$ft, brtarget:$offset); 414 dag OutOperandList = (outs); 415 string AsmString = instr_asm; 416 bit hasDelaySlot = 1; 417 InstrItinClass Itinerary = II_BC1CCZ; 418 } 419 420 class BC1EQZ_DESC : COP1_BCCZ_DESC_BASE<"bc1eqz $ft, $offset">; 421 class BC1NEZ_DESC : COP1_BCCZ_DESC_BASE<"bc1nez $ft, $offset">; 422 423 class COP2_BCCZ_DESC_BASE<string instr_asm> : BRANCH_DESC_BASE { 424 dag InOperandList = (ins COP2Opnd:$ct, brtarget:$offset); 425 dag OutOperandList = (outs); 426 string AsmString = instr_asm; 427 bit hasDelaySlot = 1; 428 bit isCTI = 1; 429 } 430 431 class BC2EQZ_DESC : COP2_BCCZ_DESC_BASE<"bc2eqz $ct, $offset">; 432 class BC2NEZ_DESC : COP2_BCCZ_DESC_BASE<"bc2nez $ct, $offset">; 433 434 class BOVC_DESC : CMP_BC_DESC_BASE<"bovc", brtarget, GPR32Opnd>; 435 class BNVC_DESC : CMP_BC_DESC_BASE<"bnvc", brtarget, GPR32Opnd>; 436 437 class JMP_IDX_COMPACT_DESC_BASE<string opstr, DAGOperand opnd, 438 RegisterOperand GPROpnd, 439 InstrItinClass itin = NoItinerary> 440 : MipsR6Arch<opstr> { 441 dag InOperandList = (ins GPROpnd:$rt, opnd:$offset); 442 string AsmString = !strconcat(opstr, "\t$rt, $offset"); 443 list<dag> Pattern = []; 444 bit hasDelaySlot = 0; 445 InstrItinClass Itinerary = itin; 446 bit isCTI = 1; 447 bit isBranch = 1; 448 bit isIndirectBranch = 1; 449 } 450 451 class JIALC_DESC : JMP_IDX_COMPACT_DESC_BASE<"jialc", calloffset16, 452 GPR32Opnd, II_JIALC> { 453 bit isCall = 1; 454 list<Register> Defs = [RA]; 455 } 456 457 class JIC_DESC : JMP_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16, 458 GPR32Opnd, II_JIALC> { 459 bit isBarrier = 1; 460 bit isTerminator = 1; 461 list<Register> Defs = [AT]; 462 } 463 464 class JR_HB_R6_DESC : JR_HB_DESC_BASE<"jr.hb", GPR32Opnd> { 465 bit isBranch = 1; 466 bit isIndirectBranch = 1; 467 bit hasDelaySlot = 1; 468 bit isTerminator=1; 469 bit isBarrier=1; 470 bit isCTI = 1; 471 } 472 473 class BITSWAP_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, 474 InstrItinClass itin> 475 : MipsR6Arch<instr_asm> { 476 dag OutOperandList = (outs GPROpnd:$rd); 477 dag InOperandList = (ins GPROpnd:$rt); 478 string AsmString = !strconcat(instr_asm, "\t$rd, $rt"); 479 list<dag> Pattern = []; 480 InstrItinClass Itinerary = itin; 481 } 482 483 class BITSWAP_DESC : BITSWAP_DESC_BASE<"bitswap", GPR32Opnd, II_BITSWAP>; 484 485 class DIVMOD_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, 486 InstrItinClass itin, 487 SDPatternOperator Op=null_frag> 488 : MipsR6Arch<instr_asm> { 489 dag OutOperandList = (outs GPROpnd:$rd); 490 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt); 491 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt"); 492 list<dag> Pattern = [(set GPROpnd:$rd, (Op GPROpnd:$rs, GPROpnd:$rt))]; 493 InstrItinClass Itinerary = itin; 494 // This instruction doesn't trap division by zero itself. We must insert 495 // teq instructions as well. 496 bit usesCustomInserter = 1; 497 } 498 499 class DIV_DESC : DIVMOD_DESC_BASE<"div", GPR32Opnd, II_DIV, sdiv>; 500 class DIVU_DESC : DIVMOD_DESC_BASE<"divu", GPR32Opnd, II_DIVU, udiv>; 501 class MOD_DESC : DIVMOD_DESC_BASE<"mod", GPR32Opnd, II_MOD, srem>; 502 class MODU_DESC : DIVMOD_DESC_BASE<"modu", GPR32Opnd, II_MODU, urem>; 503 504 class BEQZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"beqzalc", brtarget, GPR32Opnd> { 505 list<Register> Defs = [RA]; 506 } 507 508 class BGEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgezalc", brtarget, GPR32Opnd> { 509 list<Register> Defs = [RA]; 510 } 511 512 class BGTZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgtzalc", brtarget, GPR32Opnd> { 513 list<Register> Defs = [RA]; 514 } 515 516 class BLEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"blezalc", brtarget, GPR32Opnd> { 517 list<Register> Defs = [RA]; 518 } 519 520 class BLTZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bltzalc", brtarget, GPR32Opnd> { 521 list<Register> Defs = [RA]; 522 } 523 524 class BNEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bnezalc", brtarget, GPR32Opnd> { 525 list<Register> Defs = [RA]; 526 } 527 528 class MUL_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, 529 InstrItinClass itin, 530 SDPatternOperator Op=null_frag> : MipsR6Arch<instr_asm> { 531 dag OutOperandList = (outs GPROpnd:$rd); 532 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt); 533 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt"); 534 list<dag> Pattern = [(set GPROpnd:$rd, (Op GPROpnd:$rs, GPROpnd:$rt))]; 535 InstrItinClass Itinerary = itin; 536 } 537 538 class MUH_DESC : MUL_R6_DESC_BASE<"muh", GPR32Opnd, II_MUH, mulhs>; 539 class MUHU_DESC : MUL_R6_DESC_BASE<"muhu", GPR32Opnd, II_MUHU, mulhu>; 540 class MUL_R6_DESC : MUL_R6_DESC_BASE<"mul", GPR32Opnd, II_MUL, mul>; 541 class MULU_DESC : MUL_R6_DESC_BASE<"mulu", GPR32Opnd, II_MULU>; 542 543 class COP1_SEL_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> { 544 dag OutOperandList = (outs FGROpnd:$fd); 545 dag InOperandList = (ins FGRCCOpnd:$fd_in, FGROpnd:$fs, FGROpnd:$ft); 546 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft"); 547 list<dag> Pattern = [(set FGROpnd:$fd, (select FGRCCOpnd:$fd_in, 548 FGROpnd:$ft, 549 FGROpnd:$fs))]; 550 string Constraints = "$fd_in = $fd"; 551 } 552 553 class SEL_D_DESC : COP1_SEL_DESC_BASE<"sel.d", FGR64Opnd>, MipsR6Arch<"sel.d"> { 554 // We must insert a SUBREG_TO_REG around $fd_in 555 bit usesCustomInserter = 1; 556 } 557 class SEL_S_DESC : COP1_SEL_DESC_BASE<"sel.s", FGR32Opnd>, MipsR6Arch<"sel.s">; 558 559 class SELEQNE_Z_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> 560 : MipsR6Arch<instr_asm> { 561 dag OutOperandList = (outs GPROpnd:$rd); 562 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt); 563 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt"); 564 list<dag> Pattern = []; 565 InstrItinClass Itinerary = II_SELCCZ; 566 } 567 568 class SELEQZ_DESC : SELEQNE_Z_DESC_BASE<"seleqz", GPR32Opnd>; 569 class SELNEZ_DESC : SELEQNE_Z_DESC_BASE<"selnez", GPR32Opnd>; 570 571 class COP1_4R_DESC_BASE<string instr_asm, RegisterOperand FGROpnd, 572 InstrItinClass itin = NoItinerary> { 573 dag OutOperandList = (outs FGROpnd:$fd); 574 dag InOperandList = (ins FGROpnd:$fd_in, FGROpnd:$fs, FGROpnd:$ft); 575 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft"); 576 list<dag> Pattern = []; 577 string Constraints = "$fd_in = $fd"; 578 InstrItinClass Itinerary = itin; 579 } 580 581 class MADDF_S_DESC : COP1_4R_DESC_BASE<"maddf.s", FGR32Opnd, II_MADDF_S>; 582 class MADDF_D_DESC : COP1_4R_DESC_BASE<"maddf.d", FGR64Opnd, II_MADDF_D>; 583 class MSUBF_S_DESC : COP1_4R_DESC_BASE<"msubf.s", FGR32Opnd, II_MSUBF_S>; 584 class MSUBF_D_DESC : COP1_4R_DESC_BASE<"msubf.d", FGR64Opnd, II_MSUBF_D>; 585 586 class MAX_MIN_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> { 587 dag OutOperandList = (outs FGROpnd:$fd); 588 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft); 589 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft"); 590 list<dag> Pattern = []; 591 } 592 593 class MAX_S_DESC : MAX_MIN_DESC_BASE<"max.s", FGR32Opnd>; 594 class MAX_D_DESC : MAX_MIN_DESC_BASE<"max.d", FGR64Opnd>; 595 class MIN_S_DESC : MAX_MIN_DESC_BASE<"min.s", FGR32Opnd>; 596 class MIN_D_DESC : MAX_MIN_DESC_BASE<"min.d", FGR64Opnd>; 597 598 class MAXA_S_DESC : MAX_MIN_DESC_BASE<"maxa.s", FGR32Opnd>; 599 class MAXA_D_DESC : MAX_MIN_DESC_BASE<"maxa.d", FGR64Opnd>; 600 class MINA_S_DESC : MAX_MIN_DESC_BASE<"mina.s", FGR32Opnd>; 601 class MINA_D_DESC : MAX_MIN_DESC_BASE<"mina.d", FGR64Opnd>; 602 603 class SELEQNEZ_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> { 604 dag OutOperandList = (outs FGROpnd:$fd); 605 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft); 606 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft"); 607 list<dag> Pattern = []; 608 } 609 610 class SELEQZ_S_DESC : SELEQNEZ_DESC_BASE<"seleqz.s", FGR32Opnd>, 611 MipsR6Arch<"seleqz.s">; 612 class SELEQZ_D_DESC : SELEQNEZ_DESC_BASE<"seleqz.d", FGR64Opnd>, 613 MipsR6Arch<"seleqz.d">; 614 class SELNEZ_S_DESC : SELEQNEZ_DESC_BASE<"selnez.s", FGR32Opnd>, 615 MipsR6Arch<"selnez.s">; 616 class SELNEZ_D_DESC : SELEQNEZ_DESC_BASE<"selnez.d", FGR64Opnd>, 617 MipsR6Arch<"selnez.d">; 618 619 class CLASS_RINT_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> { 620 dag OutOperandList = (outs FGROpnd:$fd); 621 dag InOperandList = (ins FGROpnd:$fs); 622 string AsmString = !strconcat(instr_asm, "\t$fd, $fs"); 623 list<dag> Pattern = []; 624 } 625 626 class RINT_S_DESC : CLASS_RINT_DESC_BASE<"rint.s", FGR32Opnd>; 627 class RINT_D_DESC : CLASS_RINT_DESC_BASE<"rint.d", FGR64Opnd>; 628 class CLASS_S_DESC : CLASS_RINT_DESC_BASE<"class.s", FGR32Opnd>; 629 class CLASS_D_DESC : CLASS_RINT_DESC_BASE<"class.d", FGR64Opnd>; 630 631 class CACHE_HINT_DESC<string instr_asm, Operand MemOpnd, 632 RegisterOperand GPROpnd> : MipsR6Arch<instr_asm> { 633 dag OutOperandList = (outs); 634 dag InOperandList = (ins MemOpnd:$addr, uimm5:$hint); 635 string AsmString = !strconcat(instr_asm, "\t$hint, $addr"); 636 list<dag> Pattern = []; 637 string DecoderMethod = "DecodeCacheeOp_CacheOpR6"; 638 } 639 640 class CACHE_DESC : CACHE_HINT_DESC<"cache", mem_simm9, GPR32Opnd>; 641 class PREF_DESC : CACHE_HINT_DESC<"pref", mem_simm9, GPR32Opnd>; 642 643 class COP2LD_DESC_BASE<string instr_asm, RegisterOperand COPOpnd> { 644 dag OutOperandList = (outs COPOpnd:$rt); 645 dag InOperandList = (ins mem_simm11:$addr); 646 string AsmString = !strconcat(instr_asm, "\t$rt, $addr"); 647 list<dag> Pattern = []; 648 bit mayLoad = 1; 649 string DecoderMethod = "DecodeFMemCop2R6"; 650 } 651 652 class LDC2_R6_DESC : COP2LD_DESC_BASE<"ldc2", COP2Opnd>; 653 class LWC2_R6_DESC : COP2LD_DESC_BASE<"lwc2", COP2Opnd>; 654 655 class COP2ST_DESC_BASE<string instr_asm, RegisterOperand COPOpnd> { 656 dag OutOperandList = (outs); 657 dag InOperandList = (ins COPOpnd:$rt, mem_simm11:$addr); 658 string AsmString = !strconcat(instr_asm, "\t$rt, $addr"); 659 list<dag> Pattern = []; 660 bit mayStore = 1; 661 string DecoderMethod = "DecodeFMemCop2R6"; 662 } 663 664 class SDC2_R6_DESC : COP2ST_DESC_BASE<"sdc2", COP2Opnd>; 665 class SWC2_R6_DESC : COP2ST_DESC_BASE<"swc2", COP2Opnd>; 666 667 class LSA_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, 668 Operand ImmOpnd, InstrItinClass itin> 669 : MipsR6Arch<instr_asm> { 670 dag OutOperandList = (outs GPROpnd:$rd); 671 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$imm2); 672 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $imm2"); 673 list<dag> Pattern = []; 674 InstrItinClass Itinerary = itin; 675 } 676 677 class LSA_R6_DESC : LSA_R6_DESC_BASE<"lsa", GPR32Opnd, uimm2_plus1, II_LSA>; 678 679 class LL_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, 680 Operand MemOpnd, InstrItinClass itin> 681 : MipsR6Arch<instr_asm> { 682 dag OutOperandList = (outs GPROpnd:$rt); 683 dag InOperandList = (ins MemOpnd:$addr); 684 string AsmString = !strconcat(instr_asm, "\t$rt, $addr"); 685 list<dag> Pattern = []; 686 bit mayLoad = 1; 687 InstrItinClass Itinerary = itin; 688 } 689 690 class LL_R6_DESC : LL_R6_DESC_BASE<"ll", GPR32Opnd, mem_simm9, II_LL>; 691 692 class SC_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, 693 InstrItinClass itin> { 694 dag OutOperandList = (outs GPROpnd:$dst); 695 dag InOperandList = (ins GPROpnd:$rt, mem_simm9:$addr); 696 string AsmString = !strconcat(instr_asm, "\t$rt, $addr"); 697 list<dag> Pattern = []; 698 bit mayStore = 1; 699 string Constraints = "$rt = $dst"; 700 InstrItinClass Itinerary = itin; 701 } 702 703 class SC_R6_DESC : SC_R6_DESC_BASE<"sc", GPR32Opnd, II_SC>; 704 705 class CLO_CLZ_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, 706 InstrItinClass itin> 707 : MipsR6Arch<instr_asm> { 708 dag OutOperandList = (outs GPROpnd:$rd); 709 dag InOperandList = (ins GPROpnd:$rs); 710 string AsmString = !strconcat(instr_asm, "\t$rd, $rs"); 711 InstrItinClass Itinerary = itin; 712 } 713 714 class CLO_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, 715 InstrItinClass itin> : 716 CLO_CLZ_R6_DESC_BASE<instr_asm, GPROpnd, itin> { 717 list<dag> Pattern = [(set GPROpnd:$rd, (ctlz (not GPROpnd:$rs)))]; 718 } 719 720 class CLZ_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, 721 InstrItinClass itin> : 722 CLO_CLZ_R6_DESC_BASE<instr_asm, GPROpnd, itin> { 723 list<dag> Pattern = [(set GPROpnd:$rd, (ctlz GPROpnd:$rs))]; 724 } 725 726 class CLO_R6_DESC : CLO_R6_DESC_BASE<"clo", GPR32Opnd, II_CLO>; 727 class CLZ_R6_DESC : CLZ_R6_DESC_BASE<"clz", GPR32Opnd, II_CLZ>; 728 729 class SDBBP_R6_DESC { 730 dag OutOperandList = (outs); 731 dag InOperandList = (ins uimm20:$code_); 732 string AsmString = "sdbbp\t$code_"; 733 list<dag> Pattern = []; 734 bit isCTI = 1; 735 } 736 737 //===----------------------------------------------------------------------===// 738 // 739 // Instruction Definitions 740 // 741 //===----------------------------------------------------------------------===// 742 743 def ADDIUPC : R6MMR6Rel, ADDIUPC_ENC, ADDIUPC_DESC, ISA_MIPS32R6; 744 def ALIGN : R6MMR6Rel, ALIGN_ENC, ALIGN_DESC, ISA_MIPS32R6; 745 def ALUIPC : R6MMR6Rel, ALUIPC_ENC, ALUIPC_DESC, ISA_MIPS32R6; 746 def AUI : R6MMR6Rel, AUI_ENC, AUI_DESC, ISA_MIPS32R6; 747 def AUIPC : R6MMR6Rel, AUIPC_ENC, AUIPC_DESC, ISA_MIPS32R6; 748 def BAL : BAL_ENC, BAL_DESC, ISA_MIPS32R6; 749 def BALC : R6MMR6Rel, BALC_ENC, BALC_DESC, ISA_MIPS32R6; 750 let AdditionalPredicates = [NotInMicroMips] in { 751 def BC1EQZ : BC1EQZ_ENC, BC1EQZ_DESC, ISA_MIPS32R6, HARDFLOAT; 752 def BC1NEZ : BC1NEZ_ENC, BC1NEZ_DESC, ISA_MIPS32R6, HARDFLOAT; 753 def BC2EQZ : BC2EQZ_ENC, BC2EQZ_DESC, ISA_MIPS32R6; 754 def BC2NEZ : BC2NEZ_ENC, BC2NEZ_DESC, ISA_MIPS32R6; 755 } 756 def BC : R6MMR6Rel, BC_ENC, BC_DESC, ISA_MIPS32R6; 757 def BEQC : R6MMR6Rel, BEQC_ENC, BEQC_DESC, ISA_MIPS32R6; 758 def BEQZALC : R6MMR6Rel, BEQZALC_ENC, BEQZALC_DESC, ISA_MIPS32R6; 759 def BEQZC : R6MMR6Rel, BEQZC_ENC, BEQZC_DESC, ISA_MIPS32R6; 760 def BGEC : R6MMR6Rel, BGEC_ENC, BGEC_DESC, ISA_MIPS32R6; 761 def BGEUC : R6MMR6Rel, BGEUC_ENC, BGEUC_DESC, ISA_MIPS32R6; 762 def BGEZALC : R6MMR6Rel, BGEZALC_ENC, BGEZALC_DESC, ISA_MIPS32R6; 763 def BGEZC : BGEZC_ENC, BGEZC_DESC, ISA_MIPS32R6; 764 def BGTZALC : R6MMR6Rel, BGTZALC_ENC, BGTZALC_DESC, ISA_MIPS32R6; 765 def BGTZC : BGTZC_ENC, BGTZC_DESC, ISA_MIPS32R6; 766 def BITSWAP : R6MMR6Rel, BITSWAP_ENC, BITSWAP_DESC, ISA_MIPS32R6; 767 def BLEZALC : R6MMR6Rel, BLEZALC_ENC, BLEZALC_DESC, ISA_MIPS32R6; 768 def BLEZC : BLEZC_ENC, BLEZC_DESC, ISA_MIPS32R6; 769 def BLTC : R6MMR6Rel, BLTC_ENC, BLTC_DESC, ISA_MIPS32R6; 770 def BLTUC : R6MMR6Rel, BLTUC_ENC, BLTUC_DESC, ISA_MIPS32R6; 771 def BLTZALC : R6MMR6Rel, BLTZALC_ENC, BLTZALC_DESC, ISA_MIPS32R6; 772 def BLTZC : BLTZC_ENC, BLTZC_DESC, ISA_MIPS32R6; 773 def BNEC : R6MMR6Rel, BNEC_ENC, BNEC_DESC, ISA_MIPS32R6; 774 def BNEZALC : R6MMR6Rel, BNEZALC_ENC, BNEZALC_DESC, ISA_MIPS32R6; 775 def BNEZC : R6MMR6Rel, BNEZC_ENC, BNEZC_DESC, ISA_MIPS32R6; 776 let AdditionalPredicates = [NotInMicroMips] in { 777 def BNVC : R6MMR6Rel, BNVC_ENC, BNVC_DESC, ISA_MIPS32R6; 778 def BOVC : R6MMR6Rel, BOVC_ENC, BOVC_DESC, ISA_MIPS32R6; 779 } 780 def CACHE_R6 : R6MMR6Rel, CACHE_ENC, CACHE_DESC, ISA_MIPS32R6; 781 let AdditionalPredicates = [NotInMicroMips] in { 782 def CLASS_D : CLASS_D_ENC, CLASS_D_DESC, ISA_MIPS32R6, HARDFLOAT; 783 def CLASS_S : CLASS_S_ENC, CLASS_S_DESC, ISA_MIPS32R6, HARDFLOAT; 784 } 785 def CLO_R6 : R6MMR6Rel, CLO_R6_ENC, CLO_R6_DESC, ISA_MIPS32R6; 786 def CLZ_R6 : R6MMR6Rel, CLZ_R6_ENC, CLZ_R6_DESC, ISA_MIPS32R6; 787 defm S : CMP_CC_M<FIELD_CMP_FORMAT_S, "s", FGR32Opnd>; 788 defm D : CMP_CC_M<FIELD_CMP_FORMAT_D, "d", FGR64Opnd>; 789 let AdditionalPredicates = [NotInMicroMips] in { 790 def DIV : R6MMR6Rel, DIV_ENC, DIV_DESC, ISA_MIPS32R6; 791 def DIVU : R6MMR6Rel, DIVU_ENC, DIVU_DESC, ISA_MIPS32R6; 792 } 793 def JIALC : R6MMR6Rel, JIALC_ENC, JIALC_DESC, ISA_MIPS32R6; 794 def JIC : R6MMR6Rel, JIC_ENC, JIC_DESC, ISA_MIPS32R6; 795 def JR_HB_R6 : JR_HB_R6_ENC, JR_HB_R6_DESC, ISA_MIPS32R6; 796 let AdditionalPredicates = [NotInMicroMips] in { 797 def LDC2_R6 : LDC2_R6_ENC, LDC2_R6_DESC, ISA_MIPS32R6; 798 def LL_R6 : LL_R6_ENC, LL_R6_DESC, PTR_32, ISA_MIPS32R6; 799 } 800 def LSA_R6 : R6MMR6Rel, LSA_R6_ENC, LSA_R6_DESC, ISA_MIPS32R6; 801 let AdditionalPredicates = [NotInMicroMips] in { 802 def LWC2_R6 : LWC2_R6_ENC, LWC2_R6_DESC, ISA_MIPS32R6; 803 } 804 def LWPC : R6MMR6Rel, LWPC_ENC, LWPC_DESC, ISA_MIPS32R6; 805 def LWUPC : LWUPC_ENC, LWUPC_DESC, ISA_MIPS32R6; 806 let AdditionalPredicates = [NotInMicroMips] in { 807 def MADDF_S : MADDF_S_ENC, MADDF_S_DESC, ISA_MIPS32R6, HARDFLOAT; 808 def MADDF_D : MADDF_D_ENC, MADDF_D_DESC, ISA_MIPS32R6, HARDFLOAT; 809 def MAXA_D : MAXA_D_ENC, MAXA_D_DESC, ISA_MIPS32R6, HARDFLOAT; 810 def MAXA_S : MAXA_S_ENC, MAXA_S_DESC, ISA_MIPS32R6, HARDFLOAT; 811 def MAX_D : MAX_D_ENC, MAX_D_DESC, ISA_MIPS32R6, HARDFLOAT; 812 def MAX_S : MAX_S_ENC, MAX_S_DESC, ISA_MIPS32R6, HARDFLOAT; 813 def MINA_D : MINA_D_ENC, MINA_D_DESC, ISA_MIPS32R6, HARDFLOAT; 814 def MINA_S : MINA_S_ENC, MINA_S_DESC, ISA_MIPS32R6, HARDFLOAT; 815 def MIN_D : MIN_D_ENC, MIN_D_DESC, ISA_MIPS32R6, HARDFLOAT; 816 def MIN_S : MIN_S_ENC, MIN_S_DESC, ISA_MIPS32R6, HARDFLOAT; 817 818 def MOD : R6MMR6Rel, MOD_ENC, MOD_DESC, ISA_MIPS32R6; 819 def MODU : R6MMR6Rel, MODU_ENC, MODU_DESC, ISA_MIPS32R6; 820 821 def MSUBF_S : MSUBF_S_ENC, MSUBF_S_DESC, ISA_MIPS32R6, HARDFLOAT; 822 def MSUBF_D : MSUBF_D_ENC, MSUBF_D_DESC, ISA_MIPS32R6, HARDFLOAT; 823 824 def MUH : R6MMR6Rel, MUH_ENC, MUH_DESC, ISA_MIPS32R6; 825 def MUHU : R6MMR6Rel, MUHU_ENC, MUHU_DESC, ISA_MIPS32R6; 826 def MUL_R6 : R6MMR6Rel, MUL_R6_ENC, MUL_R6_DESC, ISA_MIPS32R6; 827 def MULU : R6MMR6Rel, MULU_ENC, MULU_DESC, ISA_MIPS32R6; 828 } 829 def NAL; // BAL with rd=0 830 def PREF_R6 : R6MMR6Rel, PREF_ENC, PREF_DESC, ISA_MIPS32R6; 831 let AdditionalPredicates = [NotInMicroMips] in { 832 def RINT_D : RINT_D_ENC, RINT_D_DESC, ISA_MIPS32R6, HARDFLOAT; 833 def RINT_S : RINT_S_ENC, RINT_S_DESC, ISA_MIPS32R6, HARDFLOAT; 834 def SC_R6 : SC_R6_ENC, SC_R6_DESC, PTR_32, ISA_MIPS32R6; 835 def SDBBP_R6 : SDBBP_R6_ENC, SDBBP_R6_DESC, ISA_MIPS32R6; 836 def SELEQZ : R6MMR6Rel, SELEQZ_ENC, SELEQZ_DESC, ISA_MIPS32R6, GPR_32; 837 def SELNEZ : R6MMR6Rel, SELNEZ_ENC, SELNEZ_DESC, ISA_MIPS32R6, GPR_32; 838 def SELEQZ_D : R6MMR6Rel, SELEQZ_D_ENC, SELEQZ_D_DESC, ISA_MIPS32R6, 839 HARDFLOAT; 840 def SELEQZ_S : R6MMR6Rel, SELEQZ_S_ENC, SELEQZ_S_DESC, ISA_MIPS32R6, 841 HARDFLOAT; 842 def SELNEZ_D : R6MMR6Rel, SELNEZ_D_ENC, SELNEZ_D_DESC, ISA_MIPS32R6, 843 HARDFLOAT; 844 def SELNEZ_S : R6MMR6Rel, SELNEZ_S_ENC, SELNEZ_S_DESC, ISA_MIPS32R6, 845 HARDFLOAT; 846 def SEL_D : R6MMR6Rel, SEL_D_ENC, SEL_D_DESC, ISA_MIPS32R6, HARDFLOAT; 847 def SEL_S : R6MMR6Rel, SEL_S_ENC, SEL_S_DESC, ISA_MIPS32R6, HARDFLOAT; 848 def SDC2_R6 : SDC2_R6_ENC, SDC2_R6_DESC, ISA_MIPS32R6; 849 def SWC2_R6 : SWC2_R6_ENC, SWC2_R6_DESC, ISA_MIPS32R6; 850 } 851 852 //===----------------------------------------------------------------------===// 853 // 854 // Instruction Aliases 855 // 856 //===----------------------------------------------------------------------===// 857 858 let AdditionalPredicates = [NotInMicroMips] in { 859 def : MipsInstAlias<"sdbbp", (SDBBP_R6 0)>, ISA_MIPS32R6; 860 def : MipsInstAlias<"jr $rs", (JALR ZERO, GPR32Opnd:$rs), 1>, ISA_MIPS32R6, GPR_32; 861 } 862 863 def : MipsInstAlias<"jrc $rs", (JIC GPR32Opnd:$rs, 0), 1>, ISA_MIPS32R6, GPR_32; 864 865 let AdditionalPredicates = [NotInMicroMips] in { 866 def : MipsInstAlias<"jalrc $rs", (JIALC GPR32Opnd:$rs, 0), 1>, ISA_MIPS32R6, GPR_32; 867 } 868 //===----------------------------------------------------------------------===// 869 // 870 // Patterns and Pseudo Instructions 871 // 872 //===----------------------------------------------------------------------===// 873 874 // comparisons supported via another comparison 875 multiclass Cmp_Pats<ValueType VT, Instruction NOROp, Register ZEROReg> { 876 def : MipsPat<(setone VT:$lhs, VT:$rhs), 877 (NOROp (!cast<Instruction>("CMP_UEQ_"#NAME) VT:$lhs, VT:$rhs), ZEROReg)>; 878 def : MipsPat<(seto VT:$lhs, VT:$rhs), 879 (NOROp (!cast<Instruction>("CMP_UN_"#NAME) VT:$lhs, VT:$rhs), ZEROReg)>; 880 def : MipsPat<(setune VT:$lhs, VT:$rhs), 881 (NOROp (!cast<Instruction>("CMP_EQ_"#NAME) VT:$lhs, VT:$rhs), ZEROReg)>; 882 def : MipsPat<(seteq VT:$lhs, VT:$rhs), 883 (!cast<Instruction>("CMP_EQ_"#NAME) VT:$lhs, VT:$rhs)>; 884 def : MipsPat<(setgt VT:$lhs, VT:$rhs), 885 (!cast<Instruction>("CMP_LE_"#NAME) VT:$rhs, VT:$lhs)>; 886 def : MipsPat<(setge VT:$lhs, VT:$rhs), 887 (!cast<Instruction>("CMP_LT_"#NAME) VT:$rhs, VT:$lhs)>; 888 def : MipsPat<(setlt VT:$lhs, VT:$rhs), 889 (!cast<Instruction>("CMP_LT_"#NAME) VT:$lhs, VT:$rhs)>; 890 def : MipsPat<(setle VT:$lhs, VT:$rhs), 891 (!cast<Instruction>("CMP_LE_"#NAME) VT:$lhs, VT:$rhs)>; 892 def : MipsPat<(setne VT:$lhs, VT:$rhs), 893 (NOROp (!cast<Instruction>("CMP_EQ_"#NAME) VT:$lhs, VT:$rhs), ZEROReg)>; 894 } 895 896 let AdditionalPredicates = [NotInMicroMips] in { 897 defm S : Cmp_Pats<f32, NOR, ZERO>, ISA_MIPS32R6; 898 defm D : Cmp_Pats<f64, NOR, ZERO>, ISA_MIPS32R6; 899 } 900 901 // i32 selects 902 multiclass SelectInt_Pats<ValueType RC, Instruction OROp, Instruction XORiOp, 903 Instruction SLTiOp, Instruction SLTiuOp, 904 Instruction SELEQZOp, Instruction SELNEZOp, 905 SDPatternOperator imm_type, ValueType Opg> { 906 // reg, immz 907 def : MipsPat<(select (Opg (seteq RC:$cond, immz)), RC:$t, RC:$f), 908 (OROp (SELEQZOp RC:$t, RC:$cond), (SELNEZOp RC:$f, RC:$cond))>; 909 def : MipsPat<(select (Opg (setne RC:$cond, immz)), RC:$t, RC:$f), 910 (OROp (SELNEZOp RC:$t, RC:$cond), (SELEQZOp RC:$f, RC:$cond))>; 911 912 // reg, immZExt16[_64] 913 def : MipsPat<(select (Opg (seteq RC:$cond, imm_type:$imm)), RC:$t, RC:$f), 914 (OROp (SELEQZOp RC:$t, (XORiOp RC:$cond, imm_type:$imm)), 915 (SELNEZOp RC:$f, (XORiOp RC:$cond, imm_type:$imm)))>; 916 def : MipsPat<(select (Opg (setne RC:$cond, imm_type:$imm)), RC:$t, RC:$f), 917 (OROp (SELNEZOp RC:$t, (XORiOp RC:$cond, imm_type:$imm)), 918 (SELEQZOp RC:$f, (XORiOp RC:$cond, imm_type:$imm)))>; 919 920 // reg, immSExt16Plus1 921 def : MipsPat<(select (Opg (setgt RC:$cond, immSExt16Plus1:$imm)), RC:$t, RC:$f), 922 (OROp (SELEQZOp RC:$t, (SLTiOp RC:$cond, (Plus1 imm:$imm))), 923 (SELNEZOp RC:$f, (SLTiOp RC:$cond, (Plus1 imm:$imm))))>; 924 def : MipsPat<(select (Opg (setugt RC:$cond, immSExt16Plus1:$imm)), RC:$t, RC:$f), 925 (OROp (SELEQZOp RC:$t, (SLTiuOp RC:$cond, (Plus1 imm:$imm))), 926 (SELNEZOp RC:$f, (SLTiuOp RC:$cond, (Plus1 imm:$imm))))>; 927 928 def : MipsPat<(select (Opg (seteq RC:$cond, immz)), RC:$t, immz), 929 (SELEQZOp RC:$t, RC:$cond)>; 930 def : MipsPat<(select (Opg (setne RC:$cond, immz)), RC:$t, immz), 931 (SELNEZOp RC:$t, RC:$cond)>; 932 def : MipsPat<(select (Opg (seteq RC:$cond, immz)), immz, RC:$f), 933 (SELNEZOp RC:$f, RC:$cond)>; 934 def : MipsPat<(select (Opg (setne RC:$cond, immz)), immz, RC:$f), 935 (SELEQZOp RC:$f, RC:$cond)>; 936 } 937 938 let AdditionalPredicates = [NotInMicroMips] in { 939 defm : SelectInt_Pats<i32, OR, XORi, SLTi, SLTiu, SELEQZ, SELNEZ, 940 immZExt16, i32>, ISA_MIPS32R6; 941 942 def : MipsPat<(select i32:$cond, i32:$t, i32:$f), 943 (OR (SELNEZ i32:$t, i32:$cond), 944 (SELEQZ i32:$f, i32:$cond))>, 945 ISA_MIPS32R6; 946 def : MipsPat<(select i32:$cond, i32:$t, immz), 947 (SELNEZ i32:$t, i32:$cond)>, 948 ISA_MIPS32R6; 949 def : MipsPat<(select i32:$cond, immz, i32:$f), 950 (SELEQZ i32:$f, i32:$cond)>, 951 ISA_MIPS32R6; 952 } 953
