1 //===-- X86InstComments.cpp - Generate verbose-asm comments for instrs ----===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This defines functionality used to emit comments about X86 instructions to 11 // an output stream for -fverbose-asm. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "X86InstComments.h" 16 #include "MCTargetDesc/X86MCTargetDesc.h" 17 #include "Utils/X86ShuffleDecode.h" 18 #include "llvm/MC/MCInst.h" 19 #include "llvm/CodeGen/MachineValueType.h" 20 #include "llvm/Support/raw_ostream.h" 21 22 using namespace llvm; 23 24 #define CASE_SSE_INS_COMMON(Inst, src) \ 25 case X86::Inst##src: 26 27 #define CASE_AVX_INS_COMMON(Inst, Suffix, src) \ 28 case X86::V##Inst##Suffix##src: 29 30 #define CASE_MASK_INS_COMMON(Inst, Suffix, src) \ 31 case X86::V##Inst##Suffix##src##k: 32 33 #define CASE_MASKZ_INS_COMMON(Inst, Suffix, src) \ 34 case X86::V##Inst##Suffix##src##kz: 35 36 #define CASE_AVX512_INS_COMMON(Inst, Suffix, src) \ 37 CASE_AVX_INS_COMMON(Inst, Suffix, src) \ 38 CASE_MASK_INS_COMMON(Inst, Suffix, src) \ 39 CASE_MASKZ_INS_COMMON(Inst, Suffix, src) 40 41 #define CASE_MOVDUP(Inst, src) \ 42 CASE_AVX512_INS_COMMON(Inst, Z, r##src) \ 43 CASE_AVX512_INS_COMMON(Inst, Z256, r##src) \ 44 CASE_AVX512_INS_COMMON(Inst, Z128, r##src) \ 45 CASE_AVX_INS_COMMON(Inst, , r##src) \ 46 CASE_AVX_INS_COMMON(Inst, Y, r##src) \ 47 CASE_SSE_INS_COMMON(Inst, r##src) 48 49 #define CASE_MASK_MOVDUP(Inst, src) \ 50 CASE_MASK_INS_COMMON(Inst, Z, r##src) \ 51 CASE_MASK_INS_COMMON(Inst, Z256, r##src) \ 52 CASE_MASK_INS_COMMON(Inst, Z128, r##src) 53 54 #define CASE_MASKZ_MOVDUP(Inst, src) \ 55 CASE_MASKZ_INS_COMMON(Inst, Z, r##src) \ 56 CASE_MASKZ_INS_COMMON(Inst, Z256, r##src) \ 57 CASE_MASKZ_INS_COMMON(Inst, Z128, r##src) 58 59 #define CASE_PMOVZX(Inst, src) \ 60 CASE_AVX512_INS_COMMON(Inst, Z, r##src) \ 61 CASE_AVX512_INS_COMMON(Inst, Z256, r##src) \ 62 CASE_AVX512_INS_COMMON(Inst, Z128, r##src) \ 63 CASE_AVX_INS_COMMON(Inst, , r##src) \ 64 CASE_AVX_INS_COMMON(Inst, Y, r##src) \ 65 CASE_SSE_INS_COMMON(Inst, r##src) 66 67 #define CASE_MASK_PMOVZX(Inst, src) \ 68 CASE_MASK_INS_COMMON(Inst, Z, r##src) \ 69 CASE_MASK_INS_COMMON(Inst, Z256, r##src) \ 70 CASE_MASK_INS_COMMON(Inst, Z128, r##src) 71 72 #define CASE_MASKZ_PMOVZX(Inst, src) \ 73 CASE_MASKZ_INS_COMMON(Inst, Z, r##src) \ 74 CASE_MASKZ_INS_COMMON(Inst, Z256, r##src) \ 75 CASE_MASKZ_INS_COMMON(Inst, Z128, r##src) 76 77 #define CASE_UNPCK(Inst, src) \ 78 CASE_AVX512_INS_COMMON(Inst, Z, r##src) \ 79 CASE_AVX512_INS_COMMON(Inst, Z256, r##src) \ 80 CASE_AVX512_INS_COMMON(Inst, Z128, r##src) \ 81 CASE_AVX_INS_COMMON(Inst, , r##src) \ 82 CASE_AVX_INS_COMMON(Inst, Y, r##src) \ 83 CASE_SSE_INS_COMMON(Inst, r##src) 84 85 #define CASE_MASK_UNPCK(Inst, src) \ 86 CASE_MASK_INS_COMMON(Inst, Z, r##src) \ 87 CASE_MASK_INS_COMMON(Inst, Z256, r##src) \ 88 CASE_MASK_INS_COMMON(Inst, Z128, r##src) 89 90 #define CASE_MASKZ_UNPCK(Inst, src) \ 91 CASE_MASKZ_INS_COMMON(Inst, Z, r##src) \ 92 CASE_MASKZ_INS_COMMON(Inst, Z256, r##src) \ 93 CASE_MASKZ_INS_COMMON(Inst, Z128, r##src) 94 95 #define CASE_SHUF(Inst, suf) \ 96 CASE_AVX512_INS_COMMON(Inst, Z, suf) \ 97 CASE_AVX512_INS_COMMON(Inst, Z256, suf) \ 98 CASE_AVX512_INS_COMMON(Inst, Z128, suf) \ 99 CASE_AVX_INS_COMMON(Inst, , suf) \ 100 CASE_AVX_INS_COMMON(Inst, Y, suf) \ 101 CASE_SSE_INS_COMMON(Inst, suf) 102 103 #define CASE_MASK_SHUF(Inst, src) \ 104 CASE_MASK_INS_COMMON(Inst, Z, r##src##i) \ 105 CASE_MASK_INS_COMMON(Inst, Z256, r##src##i) \ 106 CASE_MASK_INS_COMMON(Inst, Z128, r##src##i) 107 108 #define CASE_MASKZ_SHUF(Inst, src) \ 109 CASE_MASKZ_INS_COMMON(Inst, Z, r##src##i) \ 110 CASE_MASKZ_INS_COMMON(Inst, Z256, r##src##i) \ 111 CASE_MASKZ_INS_COMMON(Inst, Z128, r##src##i) 112 113 #define CASE_VPERMILPI(Inst, src) \ 114 CASE_AVX512_INS_COMMON(Inst, Z, src##i) \ 115 CASE_AVX512_INS_COMMON(Inst, Z256, src##i) \ 116 CASE_AVX512_INS_COMMON(Inst, Z128, src##i) \ 117 CASE_AVX_INS_COMMON(Inst, , src##i) \ 118 CASE_AVX_INS_COMMON(Inst, Y, src##i) 119 120 #define CASE_MASK_VPERMILPI(Inst, src) \ 121 CASE_MASK_INS_COMMON(Inst, Z, src##i) \ 122 CASE_MASK_INS_COMMON(Inst, Z256, src##i) \ 123 CASE_MASK_INS_COMMON(Inst, Z128, src##i) 124 125 #define CASE_MASKZ_VPERMILPI(Inst, src) \ 126 CASE_MASKZ_INS_COMMON(Inst, Z, src##i) \ 127 CASE_MASKZ_INS_COMMON(Inst, Z256, src##i) \ 128 CASE_MASKZ_INS_COMMON(Inst, Z128, src##i) 129 130 #define CASE_VPERM(Inst, src) \ 131 CASE_AVX512_INS_COMMON(Inst, Z, src##i) \ 132 CASE_AVX512_INS_COMMON(Inst, Z256, src##i) \ 133 CASE_AVX_INS_COMMON(Inst, Y, src##i) 134 135 #define CASE_MASK_VPERM(Inst, src) \ 136 CASE_MASK_INS_COMMON(Inst, Z, src##i) \ 137 CASE_MASK_INS_COMMON(Inst, Z256, src##i) 138 139 #define CASE_MASKZ_VPERM(Inst, src) \ 140 CASE_MASKZ_INS_COMMON(Inst, Z, src##i) \ 141 CASE_MASKZ_INS_COMMON(Inst, Z256, src##i) 142 143 #define CASE_VSHUF(Inst, src) \ 144 CASE_AVX512_INS_COMMON(SHUFF##Inst, Z, r##src##i) \ 145 CASE_AVX512_INS_COMMON(SHUFI##Inst, Z, r##src##i) \ 146 CASE_AVX512_INS_COMMON(SHUFF##Inst, Z256, r##src##i) \ 147 CASE_AVX512_INS_COMMON(SHUFI##Inst, Z256, r##src##i) 148 149 #define CASE_MASK_VSHUF(Inst, src) \ 150 CASE_MASK_INS_COMMON(SHUFF##Inst, Z, r##src##i) \ 151 CASE_MASK_INS_COMMON(SHUFI##Inst, Z, r##src##i) \ 152 CASE_MASK_INS_COMMON(SHUFF##Inst, Z256, r##src##i) \ 153 CASE_MASK_INS_COMMON(SHUFI##Inst, Z256, r##src##i) 154 155 #define CASE_MASKZ_VSHUF(Inst, src) \ 156 CASE_MASKZ_INS_COMMON(SHUFF##Inst, Z, r##src##i) \ 157 CASE_MASKZ_INS_COMMON(SHUFI##Inst, Z, r##src##i) \ 158 CASE_MASKZ_INS_COMMON(SHUFF##Inst, Z256, r##src##i) \ 159 CASE_MASKZ_INS_COMMON(SHUFI##Inst, Z256, r##src##i) 160 161 static unsigned getVectorRegSize(unsigned RegNo) { 162 if (X86::ZMM0 <= RegNo && RegNo <= X86::ZMM31) 163 return 512; 164 if (X86::YMM0 <= RegNo && RegNo <= X86::YMM31) 165 return 256; 166 if (X86::XMM0 <= RegNo && RegNo <= X86::XMM31) 167 return 128; 168 if (X86::MM0 <= RegNo && RegNo <= X86::MM7) 169 return 64; 170 171 llvm_unreachable("Unknown vector reg!"); 172 } 173 174 static MVT getRegOperandVectorVT(const MCInst *MI, const MVT &ScalarVT, 175 unsigned OperandIndex) { 176 unsigned OpReg = MI->getOperand(OperandIndex).getReg(); 177 return MVT::getVectorVT(ScalarVT, 178 getVectorRegSize(OpReg)/ScalarVT.getSizeInBits()); 179 } 180 181 /// \brief Extracts the dst type for a given zero extension instruction. 182 static MVT getZeroExtensionResultType(const MCInst *MI) { 183 switch (MI->getOpcode()) { 184 default: 185 llvm_unreachable("Unknown zero extension instruction"); 186 // zero extension to i16 187 CASE_PMOVZX(PMOVZXBW, m) 188 CASE_PMOVZX(PMOVZXBW, r) 189 return getRegOperandVectorVT(MI, MVT::i16, 0); 190 // zero extension to i32 191 CASE_PMOVZX(PMOVZXBD, m) 192 CASE_PMOVZX(PMOVZXBD, r) 193 CASE_PMOVZX(PMOVZXWD, m) 194 CASE_PMOVZX(PMOVZXWD, r) 195 return getRegOperandVectorVT(MI, MVT::i32, 0); 196 // zero extension to i64 197 CASE_PMOVZX(PMOVZXBQ, m) 198 CASE_PMOVZX(PMOVZXBQ, r) 199 CASE_PMOVZX(PMOVZXWQ, m) 200 CASE_PMOVZX(PMOVZXWQ, r) 201 CASE_PMOVZX(PMOVZXDQ, m) 202 CASE_PMOVZX(PMOVZXDQ, r) 203 return getRegOperandVectorVT(MI, MVT::i64, 0); 204 } 205 } 206 207 /// Wraps the destination register name with AVX512 mask/maskz filtering. 208 static std::string getMaskName(const MCInst *MI, const char *DestName, 209 const char *(*getRegName)(unsigned)) { 210 std::string OpMaskName(DestName); 211 212 bool MaskWithZero = false; 213 const char *MaskRegName = nullptr; 214 215 switch (MI->getOpcode()) { 216 default: 217 return OpMaskName; 218 CASE_MASKZ_MOVDUP(MOVDDUP, m) 219 CASE_MASKZ_MOVDUP(MOVDDUP, r) 220 CASE_MASKZ_MOVDUP(MOVSHDUP, m) 221 CASE_MASKZ_MOVDUP(MOVSHDUP, r) 222 CASE_MASKZ_MOVDUP(MOVSLDUP, m) 223 CASE_MASKZ_MOVDUP(MOVSLDUP, r) 224 CASE_MASKZ_PMOVZX(PMOVZXBD, m) 225 CASE_MASKZ_PMOVZX(PMOVZXBD, r) 226 CASE_MASKZ_PMOVZX(PMOVZXBQ, m) 227 CASE_MASKZ_PMOVZX(PMOVZXBQ, r) 228 CASE_MASKZ_PMOVZX(PMOVZXBW, m) 229 CASE_MASKZ_PMOVZX(PMOVZXBW, r) 230 CASE_MASKZ_PMOVZX(PMOVZXDQ, m) 231 CASE_MASKZ_PMOVZX(PMOVZXDQ, r) 232 CASE_MASKZ_PMOVZX(PMOVZXWD, m) 233 CASE_MASKZ_PMOVZX(PMOVZXWD, r) 234 CASE_MASKZ_PMOVZX(PMOVZXWQ, m) 235 CASE_MASKZ_PMOVZX(PMOVZXWQ, r) 236 CASE_MASKZ_UNPCK(PUNPCKHBW, m) 237 CASE_MASKZ_UNPCK(PUNPCKHBW, r) 238 CASE_MASKZ_UNPCK(PUNPCKHWD, m) 239 CASE_MASKZ_UNPCK(PUNPCKHWD, r) 240 CASE_MASKZ_UNPCK(PUNPCKHDQ, m) 241 CASE_MASKZ_UNPCK(PUNPCKHDQ, r) 242 CASE_MASKZ_UNPCK(PUNPCKLBW, m) 243 CASE_MASKZ_UNPCK(PUNPCKLBW, r) 244 CASE_MASKZ_UNPCK(PUNPCKLWD, m) 245 CASE_MASKZ_UNPCK(PUNPCKLWD, r) 246 CASE_MASKZ_UNPCK(PUNPCKLDQ, m) 247 CASE_MASKZ_UNPCK(PUNPCKLDQ, r) 248 CASE_MASKZ_UNPCK(UNPCKHPD, m) 249 CASE_MASKZ_UNPCK(UNPCKHPD, r) 250 CASE_MASKZ_UNPCK(UNPCKHPS, m) 251 CASE_MASKZ_UNPCK(UNPCKHPS, r) 252 CASE_MASKZ_UNPCK(UNPCKLPD, m) 253 CASE_MASKZ_UNPCK(UNPCKLPD, r) 254 CASE_MASKZ_UNPCK(UNPCKLPS, m) 255 CASE_MASKZ_UNPCK(UNPCKLPS, r) 256 CASE_MASKZ_SHUF(PALIGNR, r) 257 CASE_MASKZ_SHUF(PALIGNR, m) 258 CASE_MASKZ_SHUF(SHUFPD, m) 259 CASE_MASKZ_SHUF(SHUFPD, r) 260 CASE_MASKZ_SHUF(SHUFPS, m) 261 CASE_MASKZ_SHUF(SHUFPS, r) 262 CASE_MASKZ_VPERMILPI(PERMILPD, m) 263 CASE_MASKZ_VPERMILPI(PERMILPD, r) 264 CASE_MASKZ_VPERMILPI(PERMILPS, m) 265 CASE_MASKZ_VPERMILPI(PERMILPS, r) 266 CASE_MASKZ_VPERMILPI(PSHUFD, m) 267 CASE_MASKZ_VPERMILPI(PSHUFD, r) 268 CASE_MASKZ_VPERMILPI(PSHUFHW, m) 269 CASE_MASKZ_VPERMILPI(PSHUFHW, r) 270 CASE_MASKZ_VPERMILPI(PSHUFLW, m) 271 CASE_MASKZ_VPERMILPI(PSHUFLW, r) 272 CASE_MASKZ_VPERM(PERMPD, m) 273 CASE_MASKZ_VPERM(PERMPD, r) 274 CASE_MASKZ_VPERM(PERMQ, m) 275 CASE_MASKZ_VPERM(PERMQ, r) 276 CASE_MASKZ_VSHUF(64X2, m) 277 CASE_MASKZ_VSHUF(64X2, r) 278 CASE_MASKZ_VSHUF(32X4, m) 279 CASE_MASKZ_VSHUF(32X4, r) 280 MaskWithZero = true; 281 MaskRegName = getRegName(MI->getOperand(1).getReg()); 282 break; 283 CASE_MASK_MOVDUP(MOVDDUP, m) 284 CASE_MASK_MOVDUP(MOVDDUP, r) 285 CASE_MASK_MOVDUP(MOVSHDUP, m) 286 CASE_MASK_MOVDUP(MOVSHDUP, r) 287 CASE_MASK_MOVDUP(MOVSLDUP, m) 288 CASE_MASK_MOVDUP(MOVSLDUP, r) 289 CASE_MASK_PMOVZX(PMOVZXBD, m) 290 CASE_MASK_PMOVZX(PMOVZXBD, r) 291 CASE_MASK_PMOVZX(PMOVZXBQ, m) 292 CASE_MASK_PMOVZX(PMOVZXBQ, r) 293 CASE_MASK_PMOVZX(PMOVZXBW, m) 294 CASE_MASK_PMOVZX(PMOVZXBW, r) 295 CASE_MASK_PMOVZX(PMOVZXDQ, m) 296 CASE_MASK_PMOVZX(PMOVZXDQ, r) 297 CASE_MASK_PMOVZX(PMOVZXWD, m) 298 CASE_MASK_PMOVZX(PMOVZXWD, r) 299 CASE_MASK_PMOVZX(PMOVZXWQ, m) 300 CASE_MASK_PMOVZX(PMOVZXWQ, r) 301 CASE_MASK_UNPCK(PUNPCKHBW, m) 302 CASE_MASK_UNPCK(PUNPCKHBW, r) 303 CASE_MASK_UNPCK(PUNPCKHWD, m) 304 CASE_MASK_UNPCK(PUNPCKHWD, r) 305 CASE_MASK_UNPCK(PUNPCKHDQ, m) 306 CASE_MASK_UNPCK(PUNPCKHDQ, r) 307 CASE_MASK_UNPCK(PUNPCKLBW, m) 308 CASE_MASK_UNPCK(PUNPCKLBW, r) 309 CASE_MASK_UNPCK(PUNPCKLWD, m) 310 CASE_MASK_UNPCK(PUNPCKLWD, r) 311 CASE_MASK_UNPCK(PUNPCKLDQ, m) 312 CASE_MASK_UNPCK(PUNPCKLDQ, r) 313 CASE_MASK_UNPCK(UNPCKHPD, m) 314 CASE_MASK_UNPCK(UNPCKHPD, r) 315 CASE_MASK_UNPCK(UNPCKHPS, m) 316 CASE_MASK_UNPCK(UNPCKHPS, r) 317 CASE_MASK_UNPCK(UNPCKLPD, m) 318 CASE_MASK_UNPCK(UNPCKLPD, r) 319 CASE_MASK_UNPCK(UNPCKLPS, m) 320 CASE_MASK_UNPCK(UNPCKLPS, r) 321 CASE_MASK_SHUF(PALIGNR, r) 322 CASE_MASK_SHUF(PALIGNR, m) 323 CASE_MASK_SHUF(SHUFPD, m) 324 CASE_MASK_SHUF(SHUFPD, r) 325 CASE_MASK_SHUF(SHUFPS, m) 326 CASE_MASK_SHUF(SHUFPS, r) 327 CASE_MASK_VPERMILPI(PERMILPD, m) 328 CASE_MASK_VPERMILPI(PERMILPD, r) 329 CASE_MASK_VPERMILPI(PERMILPS, m) 330 CASE_MASK_VPERMILPI(PERMILPS, r) 331 CASE_MASK_VPERMILPI(PSHUFD, m) 332 CASE_MASK_VPERMILPI(PSHUFD, r) 333 CASE_MASK_VPERMILPI(PSHUFHW, m) 334 CASE_MASK_VPERMILPI(PSHUFHW, r) 335 CASE_MASK_VPERMILPI(PSHUFLW, m) 336 CASE_MASK_VPERMILPI(PSHUFLW, r) 337 CASE_MASK_VPERM(PERMPD, m) 338 CASE_MASK_VPERM(PERMPD, r) 339 CASE_MASK_VPERM(PERMQ, m) 340 CASE_MASK_VPERM(PERMQ, r) 341 CASE_MASK_VSHUF(64X2, m) 342 CASE_MASK_VSHUF(64X2, r) 343 CASE_MASK_VSHUF(32X4, m) 344 CASE_MASK_VSHUF(32X4, r) 345 MaskRegName = getRegName(MI->getOperand(2).getReg()); 346 break; 347 } 348 349 // MASK: zmmX {%kY} 350 OpMaskName += " {%"; 351 OpMaskName += MaskRegName; 352 OpMaskName += "}"; 353 354 // MASKZ: zmmX {%kY} {z} 355 if (MaskWithZero) 356 OpMaskName += " {z}"; 357 358 return OpMaskName; 359 } 360 361 //===----------------------------------------------------------------------===// 362 // Top Level Entrypoint 363 //===----------------------------------------------------------------------===// 364 365 /// EmitAnyX86InstComments - This function decodes x86 instructions and prints 366 /// newline terminated strings to the specified string if desired. This 367 /// information is shown in disassembly dumps when verbose assembly is enabled. 368 bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, 369 const char *(*getRegName)(unsigned)) { 370 // If this is a shuffle operation, the switch should fill in this state. 371 SmallVector<int, 8> ShuffleMask; 372 const char *DestName = nullptr, *Src1Name = nullptr, *Src2Name = nullptr; 373 unsigned NumOperands = MI->getNumOperands(); 374 bool RegForm = false; 375 376 switch (MI->getOpcode()) { 377 default: 378 // Not an instruction for which we can decode comments. 379 return false; 380 381 case X86::BLENDPDrri: 382 case X86::VBLENDPDrri: 383 case X86::VBLENDPDYrri: 384 Src2Name = getRegName(MI->getOperand(2).getReg()); 385 // FALL THROUGH. 386 case X86::BLENDPDrmi: 387 case X86::VBLENDPDrmi: 388 case X86::VBLENDPDYrmi: 389 if (MI->getOperand(NumOperands - 1).isImm()) 390 DecodeBLENDMask(getRegOperandVectorVT(MI, MVT::f64, 0), 391 MI->getOperand(NumOperands - 1).getImm(), 392 ShuffleMask); 393 Src1Name = getRegName(MI->getOperand(1).getReg()); 394 DestName = getRegName(MI->getOperand(0).getReg()); 395 break; 396 397 case X86::BLENDPSrri: 398 case X86::VBLENDPSrri: 399 case X86::VBLENDPSYrri: 400 Src2Name = getRegName(MI->getOperand(2).getReg()); 401 // FALL THROUGH. 402 case X86::BLENDPSrmi: 403 case X86::VBLENDPSrmi: 404 case X86::VBLENDPSYrmi: 405 if (MI->getOperand(NumOperands - 1).isImm()) 406 DecodeBLENDMask(getRegOperandVectorVT(MI, MVT::f32, 0), 407 MI->getOperand(NumOperands - 1).getImm(), 408 ShuffleMask); 409 Src1Name = getRegName(MI->getOperand(1).getReg()); 410 DestName = getRegName(MI->getOperand(0).getReg()); 411 break; 412 413 case X86::PBLENDWrri: 414 case X86::VPBLENDWrri: 415 case X86::VPBLENDWYrri: 416 Src2Name = getRegName(MI->getOperand(2).getReg()); 417 // FALL THROUGH. 418 case X86::PBLENDWrmi: 419 case X86::VPBLENDWrmi: 420 case X86::VPBLENDWYrmi: 421 if (MI->getOperand(NumOperands - 1).isImm()) 422 DecodeBLENDMask(getRegOperandVectorVT(MI, MVT::i16, 0), 423 MI->getOperand(NumOperands - 1).getImm(), 424 ShuffleMask); 425 Src1Name = getRegName(MI->getOperand(1).getReg()); 426 DestName = getRegName(MI->getOperand(0).getReg()); 427 break; 428 429 case X86::VPBLENDDrri: 430 case X86::VPBLENDDYrri: 431 Src2Name = getRegName(MI->getOperand(2).getReg()); 432 // FALL THROUGH. 433 case X86::VPBLENDDrmi: 434 case X86::VPBLENDDYrmi: 435 if (MI->getOperand(NumOperands - 1).isImm()) 436 DecodeBLENDMask(getRegOperandVectorVT(MI, MVT::i32, 0), 437 MI->getOperand(NumOperands - 1).getImm(), 438 ShuffleMask); 439 Src1Name = getRegName(MI->getOperand(1).getReg()); 440 DestName = getRegName(MI->getOperand(0).getReg()); 441 break; 442 443 case X86::INSERTPSrr: 444 case X86::VINSERTPSrr: 445 case X86::VINSERTPSzrr: 446 Src2Name = getRegName(MI->getOperand(2).getReg()); 447 // FALL THROUGH. 448 case X86::INSERTPSrm: 449 case X86::VINSERTPSrm: 450 case X86::VINSERTPSzrm: 451 DestName = getRegName(MI->getOperand(0).getReg()); 452 Src1Name = getRegName(MI->getOperand(1).getReg()); 453 if (MI->getOperand(NumOperands - 1).isImm()) 454 DecodeINSERTPSMask(MI->getOperand(NumOperands - 1).getImm(), 455 ShuffleMask); 456 break; 457 458 case X86::MOVLHPSrr: 459 case X86::VMOVLHPSrr: 460 case X86::VMOVLHPSZrr: 461 Src2Name = getRegName(MI->getOperand(2).getReg()); 462 Src1Name = getRegName(MI->getOperand(1).getReg()); 463 DestName = getRegName(MI->getOperand(0).getReg()); 464 DecodeMOVLHPSMask(2, ShuffleMask); 465 break; 466 467 case X86::MOVHLPSrr: 468 case X86::VMOVHLPSrr: 469 case X86::VMOVHLPSZrr: 470 Src2Name = getRegName(MI->getOperand(2).getReg()); 471 Src1Name = getRegName(MI->getOperand(1).getReg()); 472 DestName = getRegName(MI->getOperand(0).getReg()); 473 DecodeMOVHLPSMask(2, ShuffleMask); 474 break; 475 476 case X86::MOVHPDrm: 477 case X86::VMOVHPDrm: 478 case X86::VMOVHPDZ128rm: 479 Src1Name = getRegName(MI->getOperand(1).getReg()); 480 DestName = getRegName(MI->getOperand(0).getReg()); 481 DecodeInsertElementMask(MVT::v2f64, 1, 1, ShuffleMask); 482 break; 483 484 case X86::MOVHPSrm: 485 case X86::VMOVHPSrm: 486 case X86::VMOVHPSZ128rm: 487 Src1Name = getRegName(MI->getOperand(1).getReg()); 488 DestName = getRegName(MI->getOperand(0).getReg()); 489 DecodeInsertElementMask(MVT::v4f32, 2, 2, ShuffleMask); 490 break; 491 492 case X86::MOVLPDrm: 493 case X86::VMOVLPDrm: 494 case X86::VMOVLPDZ128rm: 495 Src1Name = getRegName(MI->getOperand(1).getReg()); 496 DestName = getRegName(MI->getOperand(0).getReg()); 497 DecodeInsertElementMask(MVT::v2f64, 0, 1, ShuffleMask); 498 break; 499 500 case X86::MOVLPSrm: 501 case X86::VMOVLPSrm: 502 case X86::VMOVLPSZ128rm: 503 Src1Name = getRegName(MI->getOperand(1).getReg()); 504 DestName = getRegName(MI->getOperand(0).getReg()); 505 DecodeInsertElementMask(MVT::v4f32, 0, 2, ShuffleMask); 506 break; 507 508 CASE_MOVDUP(MOVSLDUP, r) 509 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); 510 // FALL THROUGH. 511 CASE_MOVDUP(MOVSLDUP, m) 512 DestName = getRegName(MI->getOperand(0).getReg()); 513 DecodeMOVSLDUPMask(getRegOperandVectorVT(MI, MVT::f32, 0), ShuffleMask); 514 break; 515 516 CASE_MOVDUP(MOVSHDUP, r) 517 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); 518 // FALL THROUGH. 519 CASE_MOVDUP(MOVSHDUP, m) 520 DestName = getRegName(MI->getOperand(0).getReg()); 521 DecodeMOVSHDUPMask(getRegOperandVectorVT(MI, MVT::f32, 0), ShuffleMask); 522 break; 523 524 CASE_MOVDUP(MOVDDUP, r) 525 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); 526 // FALL THROUGH. 527 CASE_MOVDUP(MOVDDUP, m) 528 DestName = getRegName(MI->getOperand(0).getReg()); 529 DecodeMOVDDUPMask(getRegOperandVectorVT(MI, MVT::f64, 0), ShuffleMask); 530 break; 531 532 case X86::PSLLDQri: 533 case X86::VPSLLDQri: 534 case X86::VPSLLDQYri: 535 case X86::VPSLLDQZ128rr: 536 case X86::VPSLLDQZ256rr: 537 case X86::VPSLLDQZ512rr: 538 Src1Name = getRegName(MI->getOperand(1).getReg()); 539 case X86::VPSLLDQZ128rm: 540 case X86::VPSLLDQZ256rm: 541 case X86::VPSLLDQZ512rm: 542 DestName = getRegName(MI->getOperand(0).getReg()); 543 if (MI->getOperand(NumOperands - 1).isImm()) 544 DecodePSLLDQMask(getRegOperandVectorVT(MI, MVT::i8, 0), 545 MI->getOperand(NumOperands - 1).getImm(), 546 ShuffleMask); 547 break; 548 549 case X86::PSRLDQri: 550 case X86::VPSRLDQri: 551 case X86::VPSRLDQYri: 552 case X86::VPSRLDQZ128rr: 553 case X86::VPSRLDQZ256rr: 554 case X86::VPSRLDQZ512rr: 555 Src1Name = getRegName(MI->getOperand(1).getReg()); 556 case X86::VPSRLDQZ128rm: 557 case X86::VPSRLDQZ256rm: 558 case X86::VPSRLDQZ512rm: 559 DestName = getRegName(MI->getOperand(0).getReg()); 560 if (MI->getOperand(NumOperands - 1).isImm()) 561 DecodePSRLDQMask(getRegOperandVectorVT(MI, MVT::i8, 0), 562 MI->getOperand(NumOperands - 1).getImm(), 563 ShuffleMask); 564 break; 565 566 CASE_SHUF(PALIGNR, rri) 567 Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg()); 568 RegForm = true; 569 // FALL THROUGH. 570 CASE_SHUF(PALIGNR, rmi) 571 Src2Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg()); 572 DestName = getRegName(MI->getOperand(0).getReg()); 573 if (MI->getOperand(NumOperands - 1).isImm()) 574 DecodePALIGNRMask(getRegOperandVectorVT(MI, MVT::i8, 0), 575 MI->getOperand(NumOperands - 1).getImm(), 576 ShuffleMask); 577 break; 578 579 CASE_SHUF(PSHUFD, ri) 580 Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg()); 581 // FALL THROUGH. 582 CASE_SHUF(PSHUFD, mi) 583 DestName = getRegName(MI->getOperand(0).getReg()); 584 if (MI->getOperand(NumOperands - 1).isImm()) 585 DecodePSHUFMask(getRegOperandVectorVT(MI, MVT::i32, 0), 586 MI->getOperand(NumOperands - 1).getImm(), 587 ShuffleMask); 588 break; 589 590 CASE_SHUF(PSHUFHW, ri) 591 Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg()); 592 // FALL THROUGH. 593 CASE_SHUF(PSHUFHW, mi) 594 DestName = getRegName(MI->getOperand(0).getReg()); 595 if (MI->getOperand(NumOperands - 1).isImm()) 596 DecodePSHUFHWMask(getRegOperandVectorVT(MI, MVT::i16, 0), 597 MI->getOperand(NumOperands - 1).getImm(), 598 ShuffleMask); 599 break; 600 601 CASE_SHUF(PSHUFLW, ri) 602 Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg()); 603 // FALL THROUGH. 604 CASE_SHUF(PSHUFLW, mi) 605 DestName = getRegName(MI->getOperand(0).getReg()); 606 if (MI->getOperand(NumOperands - 1).isImm()) 607 DecodePSHUFLWMask(getRegOperandVectorVT(MI, MVT::i16, 0), 608 MI->getOperand(NumOperands - 1).getImm(), 609 ShuffleMask); 610 break; 611 612 case X86::MMX_PSHUFWri: 613 Src1Name = getRegName(MI->getOperand(1).getReg()); 614 // FALL THROUGH. 615 case X86::MMX_PSHUFWmi: 616 DestName = getRegName(MI->getOperand(0).getReg()); 617 if (MI->getOperand(NumOperands - 1).isImm()) 618 DecodePSHUFMask(MVT::v4i16, 619 MI->getOperand(NumOperands - 1).getImm(), 620 ShuffleMask); 621 break; 622 623 case X86::PSWAPDrr: 624 Src1Name = getRegName(MI->getOperand(1).getReg()); 625 // FALL THROUGH. 626 case X86::PSWAPDrm: 627 DestName = getRegName(MI->getOperand(0).getReg()); 628 DecodePSWAPMask(MVT::v2i32, ShuffleMask); 629 break; 630 631 CASE_UNPCK(PUNPCKHBW, r) 632 case X86::MMX_PUNPCKHBWirr: 633 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); 634 RegForm = true; 635 // FALL THROUGH. 636 CASE_UNPCK(PUNPCKHBW, m) 637 case X86::MMX_PUNPCKHBWirm: 638 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); 639 DestName = getRegName(MI->getOperand(0).getReg()); 640 DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::i8, 0), ShuffleMask); 641 break; 642 643 CASE_UNPCK(PUNPCKHWD, r) 644 case X86::MMX_PUNPCKHWDirr: 645 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); 646 RegForm = true; 647 // FALL THROUGH. 648 CASE_UNPCK(PUNPCKHWD, m) 649 case X86::MMX_PUNPCKHWDirm: 650 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); 651 DestName = getRegName(MI->getOperand(0).getReg()); 652 DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::i16, 0), ShuffleMask); 653 break; 654 655 CASE_UNPCK(PUNPCKHDQ, r) 656 case X86::MMX_PUNPCKHDQirr: 657 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); 658 RegForm = true; 659 // FALL THROUGH. 660 CASE_UNPCK(PUNPCKHDQ, m) 661 case X86::MMX_PUNPCKHDQirm: 662 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); 663 DestName = getRegName(MI->getOperand(0).getReg()); 664 DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::i32, 0), ShuffleMask); 665 break; 666 667 CASE_UNPCK(PUNPCKHQDQ, r) 668 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); 669 RegForm = true; 670 // FALL THROUGH. 671 CASE_UNPCK(PUNPCKHQDQ, m) 672 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); 673 DestName = getRegName(MI->getOperand(0).getReg()); 674 DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::i64, 0), ShuffleMask); 675 break; 676 677 CASE_UNPCK(PUNPCKLBW, r) 678 case X86::MMX_PUNPCKLBWirr: 679 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); 680 RegForm = true; 681 // FALL THROUGH. 682 CASE_UNPCK(PUNPCKLBW, m) 683 case X86::MMX_PUNPCKLBWirm: 684 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); 685 DestName = getRegName(MI->getOperand(0).getReg()); 686 DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::i8, 0), ShuffleMask); 687 break; 688 689 CASE_UNPCK(PUNPCKLWD, r) 690 case X86::MMX_PUNPCKLWDirr: 691 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); 692 RegForm = true; 693 // FALL THROUGH. 694 CASE_UNPCK(PUNPCKLWD, m) 695 case X86::MMX_PUNPCKLWDirm: 696 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); 697 DestName = getRegName(MI->getOperand(0).getReg()); 698 DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::i16, 0), ShuffleMask); 699 break; 700 701 CASE_UNPCK(PUNPCKLDQ, r) 702 case X86::MMX_PUNPCKLDQirr: 703 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); 704 RegForm = true; 705 // FALL THROUGH. 706 CASE_UNPCK(PUNPCKLDQ, m) 707 case X86::MMX_PUNPCKLDQirm: 708 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); 709 DestName = getRegName(MI->getOperand(0).getReg()); 710 DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::i32, 0), ShuffleMask); 711 break; 712 713 CASE_UNPCK(PUNPCKLQDQ, r) 714 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); 715 RegForm = true; 716 // FALL THROUGH. 717 CASE_UNPCK(PUNPCKLQDQ, m) 718 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); 719 DestName = getRegName(MI->getOperand(0).getReg()); 720 DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::i64, 0), ShuffleMask); 721 break; 722 723 CASE_SHUF(SHUFPD, rri) 724 Src2Name = getRegName(MI->getOperand(NumOperands - 2).getReg()); 725 RegForm = true; 726 // FALL THROUGH. 727 CASE_SHUF(SHUFPD, rmi) 728 if (MI->getOperand(NumOperands - 1).isImm()) 729 DecodeSHUFPMask(getRegOperandVectorVT(MI, MVT::f64, 0), 730 MI->getOperand(NumOperands - 1).getImm(), 731 ShuffleMask); 732 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg()); 733 DestName = getRegName(MI->getOperand(0).getReg()); 734 break; 735 736 CASE_SHUF(SHUFPS, rri) 737 Src2Name = getRegName(MI->getOperand(NumOperands - 2).getReg()); 738 RegForm = true; 739 // FALL THROUGH. 740 CASE_SHUF(SHUFPS, rmi) 741 if (MI->getOperand(NumOperands - 1).isImm()) 742 DecodeSHUFPMask(getRegOperandVectorVT(MI, MVT::f32, 0), 743 MI->getOperand(NumOperands - 1).getImm(), 744 ShuffleMask); 745 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg()); 746 DestName = getRegName(MI->getOperand(0).getReg()); 747 break; 748 749 CASE_VSHUF(64X2, r) 750 Src2Name = getRegName(MI->getOperand(NumOperands - 2).getReg()); 751 RegForm = true; 752 // FALL THROUGH. 753 CASE_VSHUF(64X2, m) 754 decodeVSHUF64x2FamilyMask(getRegOperandVectorVT(MI, MVT::i64, 0), 755 MI->getOperand(NumOperands - 1).getImm(), 756 ShuffleMask); 757 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg()); 758 DestName = getRegName(MI->getOperand(0).getReg()); 759 break; 760 761 CASE_VSHUF(32X4, r) 762 Src2Name = getRegName(MI->getOperand(NumOperands - 2).getReg()); 763 RegForm = true; 764 // FALL THROUGH. 765 CASE_VSHUF(32X4, m) 766 decodeVSHUF64x2FamilyMask(getRegOperandVectorVT(MI, MVT::i32, 0), 767 MI->getOperand(NumOperands - 1).getImm(), 768 ShuffleMask); 769 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg()); 770 DestName = getRegName(MI->getOperand(0).getReg()); 771 break; 772 773 CASE_UNPCK(UNPCKLPD, r) 774 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); 775 RegForm = true; 776 // FALL THROUGH. 777 CASE_UNPCK(UNPCKLPD, m) 778 DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::f64, 0), ShuffleMask); 779 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); 780 DestName = getRegName(MI->getOperand(0).getReg()); 781 break; 782 783 CASE_UNPCK(UNPCKLPS, r) 784 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); 785 RegForm = true; 786 // FALL THROUGH. 787 CASE_UNPCK(UNPCKLPS, m) 788 DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::f32, 0), ShuffleMask); 789 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); 790 DestName = getRegName(MI->getOperand(0).getReg()); 791 break; 792 793 CASE_UNPCK(UNPCKHPD, r) 794 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); 795 RegForm = true; 796 // FALL THROUGH. 797 CASE_UNPCK(UNPCKHPD, m) 798 DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::f64, 0), ShuffleMask); 799 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); 800 DestName = getRegName(MI->getOperand(0).getReg()); 801 break; 802 803 CASE_UNPCK(UNPCKHPS, r) 804 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); 805 RegForm = true; 806 // FALL THROUGH. 807 CASE_UNPCK(UNPCKHPS, m) 808 DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::f32, 0), ShuffleMask); 809 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); 810 DestName = getRegName(MI->getOperand(0).getReg()); 811 break; 812 813 CASE_VPERMILPI(PERMILPS, r) 814 Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg()); 815 // FALL THROUGH. 816 CASE_VPERMILPI(PERMILPS, m) 817 if (MI->getOperand(NumOperands - 1).isImm()) 818 DecodePSHUFMask(getRegOperandVectorVT(MI, MVT::f32, 0), 819 MI->getOperand(NumOperands - 1).getImm(), 820 ShuffleMask); 821 DestName = getRegName(MI->getOperand(0).getReg()); 822 break; 823 824 CASE_VPERMILPI(PERMILPD, r) 825 Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg()); 826 // FALL THROUGH. 827 CASE_VPERMILPI(PERMILPD, m) 828 if (MI->getOperand(NumOperands - 1).isImm()) 829 DecodePSHUFMask(getRegOperandVectorVT(MI, MVT::f64, 0), 830 MI->getOperand(NumOperands - 1).getImm(), 831 ShuffleMask); 832 DestName = getRegName(MI->getOperand(0).getReg()); 833 break; 834 835 case X86::VPERM2F128rr: 836 case X86::VPERM2I128rr: 837 Src2Name = getRegName(MI->getOperand(2).getReg()); 838 // FALL THROUGH. 839 case X86::VPERM2F128rm: 840 case X86::VPERM2I128rm: 841 // For instruction comments purpose, assume the 256-bit vector is v4i64. 842 if (MI->getOperand(NumOperands - 1).isImm()) 843 DecodeVPERM2X128Mask(MVT::v4i64, 844 MI->getOperand(NumOperands - 1).getImm(), 845 ShuffleMask); 846 Src1Name = getRegName(MI->getOperand(1).getReg()); 847 DestName = getRegName(MI->getOperand(0).getReg()); 848 break; 849 850 CASE_VPERM(PERMPD, r) 851 Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg()); 852 // FALL THROUGH. 853 CASE_VPERM(PERMPD, m) 854 if (MI->getOperand(NumOperands - 1).isImm()) 855 DecodeVPERMMask(getRegOperandVectorVT(MI, MVT::f64, 0), 856 MI->getOperand(NumOperands - 1).getImm(), 857 ShuffleMask); 858 DestName = getRegName(MI->getOperand(0).getReg()); 859 break; 860 861 CASE_VPERM(PERMQ, r) 862 Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg()); 863 // FALL THROUGH. 864 CASE_VPERM(PERMQ, m) 865 if (MI->getOperand(NumOperands - 1).isImm()) 866 DecodeVPERMMask(getRegOperandVectorVT(MI, MVT::i64, 0), 867 MI->getOperand(NumOperands - 1).getImm(), 868 ShuffleMask); 869 DestName = getRegName(MI->getOperand(0).getReg()); 870 break; 871 872 case X86::MOVSDrr: 873 case X86::VMOVSDrr: 874 case X86::VMOVSDZrr: 875 Src2Name = getRegName(MI->getOperand(2).getReg()); 876 Src1Name = getRegName(MI->getOperand(1).getReg()); 877 // FALL THROUGH. 878 case X86::MOVSDrm: 879 case X86::VMOVSDrm: 880 case X86::VMOVSDZrm: 881 DecodeScalarMoveMask(MVT::v2f64, nullptr == Src2Name, ShuffleMask); 882 DestName = getRegName(MI->getOperand(0).getReg()); 883 break; 884 885 case X86::MOVSSrr: 886 case X86::VMOVSSrr: 887 case X86::VMOVSSZrr: 888 Src2Name = getRegName(MI->getOperand(2).getReg()); 889 Src1Name = getRegName(MI->getOperand(1).getReg()); 890 // FALL THROUGH. 891 case X86::MOVSSrm: 892 case X86::VMOVSSrm: 893 case X86::VMOVSSZrm: 894 DecodeScalarMoveMask(MVT::v4f32, nullptr == Src2Name, ShuffleMask); 895 DestName = getRegName(MI->getOperand(0).getReg()); 896 break; 897 898 case X86::MOVPQI2QIrr: 899 case X86::MOVZPQILo2PQIrr: 900 case X86::VMOVPQI2QIrr: 901 case X86::VMOVZPQILo2PQIrr: 902 case X86::VMOVZPQILo2PQIZrr: 903 Src1Name = getRegName(MI->getOperand(1).getReg()); 904 // FALL THROUGH. 905 case X86::MOVQI2PQIrm: 906 case X86::MOVZQI2PQIrm: 907 case X86::MOVZPQILo2PQIrm: 908 case X86::VMOVQI2PQIrm: 909 case X86::VMOVQI2PQIZrm: 910 case X86::VMOVZQI2PQIrm: 911 case X86::VMOVZPQILo2PQIrm: 912 case X86::VMOVZPQILo2PQIZrm: 913 DecodeZeroMoveLowMask(MVT::v2i64, ShuffleMask); 914 DestName = getRegName(MI->getOperand(0).getReg()); 915 break; 916 917 case X86::MOVDI2PDIrm: 918 case X86::VMOVDI2PDIrm: 919 case X86::VMOVDI2PDIZrm: 920 DecodeZeroMoveLowMask(MVT::v4i32, ShuffleMask); 921 DestName = getRegName(MI->getOperand(0).getReg()); 922 break; 923 924 case X86::EXTRQI: 925 if (MI->getOperand(2).isImm() && 926 MI->getOperand(3).isImm()) 927 DecodeEXTRQIMask(MI->getOperand(2).getImm(), 928 MI->getOperand(3).getImm(), 929 ShuffleMask); 930 931 DestName = getRegName(MI->getOperand(0).getReg()); 932 Src1Name = getRegName(MI->getOperand(1).getReg()); 933 break; 934 935 case X86::INSERTQI: 936 if (MI->getOperand(3).isImm() && 937 MI->getOperand(4).isImm()) 938 DecodeINSERTQIMask(MI->getOperand(3).getImm(), 939 MI->getOperand(4).getImm(), 940 ShuffleMask); 941 942 DestName = getRegName(MI->getOperand(0).getReg()); 943 Src1Name = getRegName(MI->getOperand(1).getReg()); 944 Src2Name = getRegName(MI->getOperand(2).getReg()); 945 break; 946 947 case X86::VBROADCASTF128: 948 case X86::VBROADCASTI128: 949 DecodeSubVectorBroadcast(MVT::v4f64, MVT::v2f64, ShuffleMask); 950 DestName = getRegName(MI->getOperand(0).getReg()); 951 break; 952 953 CASE_PMOVZX(PMOVZXBW, r) 954 CASE_PMOVZX(PMOVZXBD, r) 955 CASE_PMOVZX(PMOVZXBQ, r) 956 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); 957 // FALL THROUGH. 958 CASE_PMOVZX(PMOVZXBW, m) 959 CASE_PMOVZX(PMOVZXBD, m) 960 CASE_PMOVZX(PMOVZXBQ, m) 961 DecodeZeroExtendMask(MVT::i8, getZeroExtensionResultType(MI), ShuffleMask); 962 DestName = getRegName(MI->getOperand(0).getReg()); 963 break; 964 965 CASE_PMOVZX(PMOVZXWD, r) 966 CASE_PMOVZX(PMOVZXWQ, r) 967 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); 968 // FALL THROUGH. 969 CASE_PMOVZX(PMOVZXWD, m) 970 CASE_PMOVZX(PMOVZXWQ, m) 971 DecodeZeroExtendMask(MVT::i16, getZeroExtensionResultType(MI), ShuffleMask); 972 DestName = getRegName(MI->getOperand(0).getReg()); 973 break; 974 975 CASE_PMOVZX(PMOVZXDQ, r) 976 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); 977 // FALL THROUGH. 978 CASE_PMOVZX(PMOVZXDQ, m) 979 DecodeZeroExtendMask(MVT::i32, getZeroExtensionResultType(MI), ShuffleMask); 980 DestName = getRegName(MI->getOperand(0).getReg()); 981 break; 982 } 983 984 // The only comments we decode are shuffles, so give up if we were unable to 985 // decode a shuffle mask. 986 if (ShuffleMask.empty()) 987 return false; 988 989 if (!DestName) DestName = Src1Name; 990 OS << (DestName ? getMaskName(MI, DestName, getRegName) : "mem") << " = "; 991 992 // If the two sources are the same, canonicalize the input elements to be 993 // from the first src so that we get larger element spans. 994 if (Src1Name == Src2Name) { 995 for (unsigned i = 0, e = ShuffleMask.size(); i != e; ++i) { 996 if ((int)ShuffleMask[i] >= 0 && // Not sentinel. 997 ShuffleMask[i] >= (int)e) // From second mask. 998 ShuffleMask[i] -= e; 999 } 1000 } 1001 1002 // The shuffle mask specifies which elements of the src1/src2 fill in the 1003 // destination, with a few sentinel values. Loop through and print them 1004 // out. 1005 for (unsigned i = 0, e = ShuffleMask.size(); i != e; ++i) { 1006 if (i != 0) 1007 OS << ','; 1008 if (ShuffleMask[i] == SM_SentinelZero) { 1009 OS << "zero"; 1010 continue; 1011 } 1012 1013 // Otherwise, it must come from src1 or src2. Print the span of elements 1014 // that comes from this src. 1015 bool isSrc1 = ShuffleMask[i] < (int)ShuffleMask.size(); 1016 const char *SrcName = isSrc1 ? Src1Name : Src2Name; 1017 OS << (SrcName ? SrcName : "mem") << '['; 1018 bool IsFirst = true; 1019 while (i != e && (int)ShuffleMask[i] != SM_SentinelZero && 1020 (ShuffleMask[i] < (int)ShuffleMask.size()) == isSrc1) { 1021 if (!IsFirst) 1022 OS << ','; 1023 else 1024 IsFirst = false; 1025 if (ShuffleMask[i] == SM_SentinelUndef) 1026 OS << "u"; 1027 else 1028 OS << ShuffleMask[i] % ShuffleMask.size(); 1029 ++i; 1030 } 1031 OS << ']'; 1032 --i; // For loop increments element #. 1033 } 1034 //MI->print(OS, 0); 1035 OS << "\n"; 1036 1037 // We successfully added a comment to this instruction. 1038 return true; 1039 } 1040
