1 //===-- X86.td - Target definition file for the Intel X86 --*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This is a target description file for the Intel i386 architecture, referred 11 // to here as the "X86" architecture. 12 // 13 //===----------------------------------------------------------------------===// 14 15 // Get the target-independent interfaces which we are implementing... 16 // 17 include "llvm/Target/Target.td" 18 19 //===----------------------------------------------------------------------===// 20 // X86 Subtarget state 21 // 22 23 def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true", 24 "64-bit mode (x86_64)">; 25 def Mode32Bit : SubtargetFeature<"32bit-mode", "In32BitMode", "true", 26 "32-bit mode (80386)">; 27 def Mode16Bit : SubtargetFeature<"16bit-mode", "In16BitMode", "true", 28 "16-bit mode (i8086)">; 29 30 //===----------------------------------------------------------------------===// 31 // X86 Subtarget features 32 //===----------------------------------------------------------------------===// 33 34 def FeatureX87 : SubtargetFeature<"x87","HasX87", "true", 35 "Enable X87 float instructions">; 36 37 def FeatureCMOV : SubtargetFeature<"cmov","HasCMov", "true", 38 "Enable conditional move instructions">; 39 40 def FeaturePOPCNT : SubtargetFeature<"popcnt", "HasPOPCNT", "true", 41 "Support POPCNT instruction">; 42 43 def FeatureFXSR : SubtargetFeature<"fxsr", "HasFXSR", "true", 44 "Support fxsave/fxrestore instructions">; 45 46 def FeatureXSAVE : SubtargetFeature<"xsave", "HasXSAVE", "true", 47 "Support xsave instructions">; 48 49 def FeatureXSAVEOPT: SubtargetFeature<"xsaveopt", "HasXSAVEOPT", "true", 50 "Support xsaveopt instructions">; 51 52 def FeatureXSAVEC : SubtargetFeature<"xsavec", "HasXSAVEC", "true", 53 "Support xsavec instructions">; 54 55 def FeatureXSAVES : SubtargetFeature<"xsaves", "HasXSAVES", "true", 56 "Support xsaves instructions">; 57 58 def FeatureSSE1 : SubtargetFeature<"sse", "X86SSELevel", "SSE1", 59 "Enable SSE instructions", 60 // SSE codegen depends on cmovs, and all 61 // SSE1+ processors support them. 62 [FeatureCMOV]>; 63 def FeatureSSE2 : SubtargetFeature<"sse2", "X86SSELevel", "SSE2", 64 "Enable SSE2 instructions", 65 [FeatureSSE1]>; 66 def FeatureSSE3 : SubtargetFeature<"sse3", "X86SSELevel", "SSE3", 67 "Enable SSE3 instructions", 68 [FeatureSSE2]>; 69 def FeatureSSSE3 : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3", 70 "Enable SSSE3 instructions", 71 [FeatureSSE3]>; 72 def FeatureSSE41 : SubtargetFeature<"sse4.1", "X86SSELevel", "SSE41", 73 "Enable SSE 4.1 instructions", 74 [FeatureSSSE3]>; 75 def FeatureSSE42 : SubtargetFeature<"sse4.2", "X86SSELevel", "SSE42", 76 "Enable SSE 4.2 instructions", 77 [FeatureSSE41]>; 78 // The MMX subtarget feature is separate from the rest of the SSE features 79 // because it's important (for odd compatibility reasons) to be able to 80 // turn it off explicitly while allowing SSE+ to be on. 81 def FeatureMMX : SubtargetFeature<"mmx","X863DNowLevel", "MMX", 82 "Enable MMX instructions">; 83 def Feature3DNow : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow", 84 "Enable 3DNow! instructions", 85 [FeatureMMX]>; 86 def Feature3DNowA : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA", 87 "Enable 3DNow! Athlon instructions", 88 [Feature3DNow]>; 89 // All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied 90 // feature, because SSE2 can be disabled (e.g. for compiling OS kernels) 91 // without disabling 64-bit mode. 92 def Feature64Bit : SubtargetFeature<"64bit", "HasX86_64", "true", 93 "Support 64-bit instructions", 94 [FeatureCMOV]>; 95 def FeatureCMPXCHG16B : SubtargetFeature<"cx16", "HasCmpxchg16b", "true", 96 "64-bit with cmpxchg16b", 97 [Feature64Bit]>; 98 def FeatureSlowBTMem : SubtargetFeature<"slow-bt-mem", "IsBTMemSlow", "true", 99 "Bit testing of memory is slow">; 100 def FeatureSlowSHLD : SubtargetFeature<"slow-shld", "IsSHLDSlow", "true", 101 "SHLD instruction is slow">; 102 // FIXME: This should not apply to CPUs that do not have SSE. 103 def FeatureSlowUAMem16 : SubtargetFeature<"slow-unaligned-mem-16", 104 "IsUAMem16Slow", "true", 105 "Slow unaligned 16-byte memory access">; 106 def FeatureSlowUAMem32 : SubtargetFeature<"slow-unaligned-mem-32", 107 "IsUAMem32Slow", "true", 108 "Slow unaligned 32-byte memory access">; 109 def FeatureSSE4A : SubtargetFeature<"sse4a", "HasSSE4A", "true", 110 "Support SSE 4a instructions", 111 [FeatureSSE3]>; 112 113 def FeatureAVX : SubtargetFeature<"avx", "X86SSELevel", "AVX", 114 "Enable AVX instructions", 115 [FeatureSSE42]>; 116 def FeatureAVX2 : SubtargetFeature<"avx2", "X86SSELevel", "AVX2", 117 "Enable AVX2 instructions", 118 [FeatureAVX]>; 119 def FeatureAVX512 : SubtargetFeature<"avx512f", "X86SSELevel", "AVX512F", 120 "Enable AVX-512 instructions", 121 [FeatureAVX2]>; 122 def FeatureERI : SubtargetFeature<"avx512er", "HasERI", "true", 123 "Enable AVX-512 Exponential and Reciprocal Instructions", 124 [FeatureAVX512]>; 125 def FeatureCDI : SubtargetFeature<"avx512cd", "HasCDI", "true", 126 "Enable AVX-512 Conflict Detection Instructions", 127 [FeatureAVX512]>; 128 def FeaturePFI : SubtargetFeature<"avx512pf", "HasPFI", "true", 129 "Enable AVX-512 PreFetch Instructions", 130 [FeatureAVX512]>; 131 def FeaturePREFETCHWT1 : SubtargetFeature<"prefetchwt1", "HasPFPREFETCHWT1", 132 "true", 133 "Prefetch with Intent to Write and T1 Hint">; 134 def FeatureDQI : SubtargetFeature<"avx512dq", "HasDQI", "true", 135 "Enable AVX-512 Doubleword and Quadword Instructions", 136 [FeatureAVX512]>; 137 def FeatureBWI : SubtargetFeature<"avx512bw", "HasBWI", "true", 138 "Enable AVX-512 Byte and Word Instructions", 139 [FeatureAVX512]>; 140 def FeatureVLX : SubtargetFeature<"avx512vl", "HasVLX", "true", 141 "Enable AVX-512 Vector Length eXtensions", 142 [FeatureAVX512]>; 143 def FeatureVBMI : SubtargetFeature<"avx512vbmi", "HasVBMI", "true", 144 "Enable AVX-512 Vector Bit Manipulation Instructions", 145 [FeatureAVX512]>; 146 def FeatureIFMA : SubtargetFeature<"avx512ifma", "HasIFMA", "true", 147 "Enable AVX-512 Integer Fused Multiple-Add", 148 [FeatureAVX512]>; 149 def FeaturePKU : SubtargetFeature<"pku", "HasPKU", "true", 150 "Enable protection keys">; 151 def FeaturePCLMUL : SubtargetFeature<"pclmul", "HasPCLMUL", "true", 152 "Enable packed carry-less multiplication instructions", 153 [FeatureSSE2]>; 154 def FeatureFMA : SubtargetFeature<"fma", "HasFMA", "true", 155 "Enable three-operand fused multiple-add", 156 [FeatureAVX]>; 157 def FeatureFMA4 : SubtargetFeature<"fma4", "HasFMA4", "true", 158 "Enable four-operand fused multiple-add", 159 [FeatureAVX, FeatureSSE4A]>; 160 def FeatureXOP : SubtargetFeature<"xop", "HasXOP", "true", 161 "Enable XOP instructions", 162 [FeatureFMA4]>; 163 def FeatureSSEUnalignedMem : SubtargetFeature<"sse-unaligned-mem", 164 "HasSSEUnalignedMem", "true", 165 "Allow unaligned memory operands with SSE instructions">; 166 def FeatureAES : SubtargetFeature<"aes", "HasAES", "true", 167 "Enable AES instructions", 168 [FeatureSSE2]>; 169 def FeatureTBM : SubtargetFeature<"tbm", "HasTBM", "true", 170 "Enable TBM instructions">; 171 def FeatureMOVBE : SubtargetFeature<"movbe", "HasMOVBE", "true", 172 "Support MOVBE instruction">; 173 def FeatureRDRAND : SubtargetFeature<"rdrnd", "HasRDRAND", "true", 174 "Support RDRAND instruction">; 175 def FeatureF16C : SubtargetFeature<"f16c", "HasF16C", "true", 176 "Support 16-bit floating point conversion instructions", 177 [FeatureAVX]>; 178 def FeatureFSGSBase : SubtargetFeature<"fsgsbase", "HasFSGSBase", "true", 179 "Support FS/GS Base instructions">; 180 def FeatureLZCNT : SubtargetFeature<"lzcnt", "HasLZCNT", "true", 181 "Support LZCNT instruction">; 182 def FeatureBMI : SubtargetFeature<"bmi", "HasBMI", "true", 183 "Support BMI instructions">; 184 def FeatureBMI2 : SubtargetFeature<"bmi2", "HasBMI2", "true", 185 "Support BMI2 instructions">; 186 def FeatureRTM : SubtargetFeature<"rtm", "HasRTM", "true", 187 "Support RTM instructions">; 188 def FeatureHLE : SubtargetFeature<"hle", "HasHLE", "true", 189 "Support HLE">; 190 def FeatureADX : SubtargetFeature<"adx", "HasADX", "true", 191 "Support ADX instructions">; 192 def FeatureSHA : SubtargetFeature<"sha", "HasSHA", "true", 193 "Enable SHA instructions", 194 [FeatureSSE2]>; 195 def FeaturePRFCHW : SubtargetFeature<"prfchw", "HasPRFCHW", "true", 196 "Support PRFCHW instructions">; 197 def FeatureRDSEED : SubtargetFeature<"rdseed", "HasRDSEED", "true", 198 "Support RDSEED instruction">; 199 def FeatureLAHFSAHF : SubtargetFeature<"sahf", "HasLAHFSAHF", "true", 200 "Support LAHF and SAHF instructions">; 201 def FeatureMWAITX : SubtargetFeature<"mwaitx", "HasMWAITX", "true", 202 "Enable MONITORX/MWAITX timer functionality">; 203 def FeatureMPX : SubtargetFeature<"mpx", "HasMPX", "true", 204 "Support MPX instructions">; 205 def FeatureLEAForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true", 206 "Use LEA for adjusting the stack pointer">; 207 def FeatureSlowDivide32 : SubtargetFeature<"idivl-to-divb", 208 "HasSlowDivide32", "true", 209 "Use 8-bit divide for positive values less than 256">; 210 def FeatureSlowDivide64 : SubtargetFeature<"idivq-to-divw", 211 "HasSlowDivide64", "true", 212 "Use 16-bit divide for positive values less than 65536">; 213 def FeaturePadShortFunctions : SubtargetFeature<"pad-short-functions", 214 "PadShortFunctions", "true", 215 "Pad short functions">; 216 def FeatureINVPCID : SubtargetFeature<"invpcid", "HasInvPCId", "true", 217 "Invalidate Process-Context Identifier">; 218 def FeatureVMFUNC : SubtargetFeature<"vmfunc", "HasVMFUNC", "true", 219 "VM Functions">; 220 def FeatureSMAP : SubtargetFeature<"smap", "HasSMAP", "true", 221 "Supervisor Mode Access Protection">; 222 def FeatureSGX : SubtargetFeature<"sgx", "HasSGX", "true", 223 "Enable Software Guard Extensions">; 224 def FeatureCLFLUSHOPT : SubtargetFeature<"clflushopt", "HasCLFLUSHOPT", "true", 225 "Flush A Cache Line Optimized">; 226 def FeaturePCOMMIT : SubtargetFeature<"pcommit", "HasPCOMMIT", "true", 227 "Enable Persistent Commit">; 228 def FeatureCLWB : SubtargetFeature<"clwb", "HasCLWB", "true", 229 "Cache Line Write Back">; 230 // TODO: This feature ought to be renamed. 231 // What it really refers to are CPUs for which certain instructions 232 // (which ones besides the example below?) are microcoded. 233 // The best examples of this are the memory forms of CALL and PUSH 234 // instructions, which should be avoided in favor of a MOV + register CALL/PUSH. 235 def FeatureCallRegIndirect : SubtargetFeature<"call-reg-indirect", 236 "CallRegIndirect", "true", 237 "Call register indirect">; 238 def FeatureLEAUsesAG : SubtargetFeature<"lea-uses-ag", "LEAUsesAG", "true", 239 "LEA instruction needs inputs at AG stage">; 240 def FeatureSlowLEA : SubtargetFeature<"slow-lea", "SlowLEA", "true", 241 "LEA instruction with certain arguments is slow">; 242 def FeatureSlowIncDec : SubtargetFeature<"slow-incdec", "SlowIncDec", "true", 243 "INC and DEC instructions are slower than ADD and SUB">; 244 def FeatureSoftFloat 245 : SubtargetFeature<"soft-float", "UseSoftFloat", "true", 246 "Use software floating point features.">; 247 // On at least some AMD processors, there is no performance hazard to writing 248 // only the lower parts of a YMM register without clearing the upper part. 249 def FeatureFastPartialYMMWrite 250 : SubtargetFeature<"fast-partial-ymm-write", "HasFastPartialYMMWrite", 251 "true", "Partial writes to YMM registers are fast">; 252 253 //===----------------------------------------------------------------------===// 254 // X86 processors supported. 255 //===----------------------------------------------------------------------===// 256 257 include "X86Schedule.td" 258 259 def ProcIntelAtom : SubtargetFeature<"atom", "X86ProcFamily", "IntelAtom", 260 "Intel Atom processors">; 261 def ProcIntelSLM : SubtargetFeature<"slm", "X86ProcFamily", "IntelSLM", 262 "Intel Silvermont processors">; 263 264 class Proc<string Name, list<SubtargetFeature> Features> 265 : ProcessorModel<Name, GenericModel, Features>; 266 267 def : Proc<"generic", [FeatureX87, FeatureSlowUAMem16]>; 268 def : Proc<"i386", [FeatureX87, FeatureSlowUAMem16]>; 269 def : Proc<"i486", [FeatureX87, FeatureSlowUAMem16]>; 270 def : Proc<"i586", [FeatureX87, FeatureSlowUAMem16]>; 271 def : Proc<"pentium", [FeatureX87, FeatureSlowUAMem16]>; 272 def : Proc<"pentium-mmx", [FeatureX87, FeatureSlowUAMem16, FeatureMMX]>; 273 def : Proc<"i686", [FeatureX87, FeatureSlowUAMem16]>; 274 def : Proc<"pentiumpro", [FeatureX87, FeatureSlowUAMem16, FeatureCMOV]>; 275 def : Proc<"pentium2", [FeatureX87, FeatureSlowUAMem16, FeatureMMX, 276 FeatureCMOV, FeatureFXSR]>; 277 def : Proc<"pentium3", [FeatureX87, FeatureSlowUAMem16, FeatureMMX, 278 FeatureSSE1, FeatureFXSR]>; 279 def : Proc<"pentium3m", [FeatureX87, FeatureSlowUAMem16, FeatureMMX, 280 FeatureSSE1, FeatureFXSR, FeatureSlowBTMem]>; 281 282 // Enable the PostRAScheduler for SSE2 and SSE3 class cpus. 283 // The intent is to enable it for pentium4 which is the current default 284 // processor in a vanilla 32-bit clang compilation when no specific 285 // architecture is specified. This generally gives a nice performance 286 // increase on silvermont, with largely neutral behavior on other 287 // contemporary large core processors. 288 // pentium-m, pentium4m, prescott and nocona are included as a preventative 289 // measure to avoid performance surprises, in case clang's default cpu 290 // changes slightly. 291 292 def : ProcessorModel<"pentium-m", GenericPostRAModel, 293 [FeatureX87, FeatureSlowUAMem16, FeatureMMX, 294 FeatureSSE2, FeatureFXSR, FeatureSlowBTMem]>; 295 296 def : ProcessorModel<"pentium4", GenericPostRAModel, 297 [FeatureX87, FeatureSlowUAMem16, FeatureMMX, 298 FeatureSSE2, FeatureFXSR]>; 299 300 def : ProcessorModel<"pentium4m", GenericPostRAModel, 301 [FeatureX87, FeatureSlowUAMem16, FeatureMMX, 302 FeatureSSE2, FeatureFXSR, FeatureSlowBTMem]>; 303 304 // Intel Quark. 305 def : Proc<"lakemont", []>; 306 307 // Intel Core Duo. 308 def : ProcessorModel<"yonah", SandyBridgeModel, 309 [FeatureX87, FeatureSlowUAMem16, FeatureMMX, FeatureSSE3, 310 FeatureFXSR, FeatureSlowBTMem]>; 311 312 // NetBurst. 313 def : ProcessorModel<"prescott", GenericPostRAModel, 314 [FeatureX87, FeatureSlowUAMem16, FeatureMMX, FeatureSSE3, 315 FeatureFXSR, FeatureSlowBTMem]>; 316 def : ProcessorModel<"nocona", GenericPostRAModel, [ 317 FeatureX87, 318 FeatureSlowUAMem16, 319 FeatureMMX, 320 FeatureSSE3, 321 FeatureFXSR, 322 FeatureCMPXCHG16B, 323 FeatureSlowBTMem 324 ]>; 325 326 // Intel Core 2 Solo/Duo. 327 def : ProcessorModel<"core2", SandyBridgeModel, [ 328 FeatureX87, 329 FeatureSlowUAMem16, 330 FeatureMMX, 331 FeatureSSSE3, 332 FeatureFXSR, 333 FeatureCMPXCHG16B, 334 FeatureSlowBTMem, 335 FeatureLAHFSAHF 336 ]>; 337 def : ProcessorModel<"penryn", SandyBridgeModel, [ 338 FeatureX87, 339 FeatureSlowUAMem16, 340 FeatureMMX, 341 FeatureSSE41, 342 FeatureFXSR, 343 FeatureCMPXCHG16B, 344 FeatureSlowBTMem, 345 FeatureLAHFSAHF 346 ]>; 347 348 // Atom CPUs. 349 class BonnellProc<string Name> : ProcessorModel<Name, AtomModel, [ 350 ProcIntelAtom, 351 FeatureX87, 352 FeatureSlowUAMem16, 353 FeatureMMX, 354 FeatureSSSE3, 355 FeatureFXSR, 356 FeatureCMPXCHG16B, 357 FeatureMOVBE, 358 FeatureSlowBTMem, 359 FeatureLEAForSP, 360 FeatureSlowDivide32, 361 FeatureSlowDivide64, 362 FeatureCallRegIndirect, 363 FeatureLEAUsesAG, 364 FeaturePadShortFunctions, 365 FeatureLAHFSAHF 366 ]>; 367 def : BonnellProc<"bonnell">; 368 def : BonnellProc<"atom">; // Pin the generic name to the baseline. 369 370 class SilvermontProc<string Name> : ProcessorModel<Name, SLMModel, [ 371 ProcIntelSLM, 372 FeatureX87, 373 FeatureMMX, 374 FeatureSSE42, 375 FeatureFXSR, 376 FeatureCMPXCHG16B, 377 FeatureMOVBE, 378 FeaturePOPCNT, 379 FeaturePCLMUL, 380 FeatureAES, 381 FeatureSlowDivide64, 382 FeatureCallRegIndirect, 383 FeaturePRFCHW, 384 FeatureSlowLEA, 385 FeatureSlowIncDec, 386 FeatureSlowBTMem, 387 FeatureLAHFSAHF 388 ]>; 389 def : SilvermontProc<"silvermont">; 390 def : SilvermontProc<"slm">; // Legacy alias. 391 392 // "Arrandale" along with corei3 and corei5 393 class NehalemProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [ 394 FeatureX87, 395 FeatureMMX, 396 FeatureSSE42, 397 FeatureFXSR, 398 FeatureCMPXCHG16B, 399 FeatureSlowBTMem, 400 FeaturePOPCNT, 401 FeatureLAHFSAHF 402 ]>; 403 def : NehalemProc<"nehalem">; 404 def : NehalemProc<"corei7">; 405 406 // Westmere is a similar machine to nehalem with some additional features. 407 // Westmere is the corei3/i5/i7 path from nehalem to sandybridge 408 class WestmereProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [ 409 FeatureX87, 410 FeatureMMX, 411 FeatureSSE42, 412 FeatureFXSR, 413 FeatureCMPXCHG16B, 414 FeatureSlowBTMem, 415 FeaturePOPCNT, 416 FeatureAES, 417 FeaturePCLMUL, 418 FeatureLAHFSAHF 419 ]>; 420 def : WestmereProc<"westmere">; 421 422 class ProcessorFeatures<list<SubtargetFeature> Inherited, 423 list<SubtargetFeature> NewFeatures> { 424 list<SubtargetFeature> Value = !listconcat(Inherited, NewFeatures); 425 } 426 427 class ProcModel<string Name, SchedMachineModel Model, 428 list<SubtargetFeature> ProcFeatures, 429 list<SubtargetFeature> OtherFeatures> : 430 ProcessorModel<Name, Model, !listconcat(ProcFeatures, OtherFeatures)>; 431 432 // SSE is not listed here since llvm treats AVX as a reimplementation of SSE, 433 // rather than a superset. 434 def SNBFeatures : ProcessorFeatures<[], [ 435 FeatureX87, 436 FeatureMMX, 437 FeatureAVX, 438 FeatureFXSR, 439 FeatureCMPXCHG16B, 440 FeaturePOPCNT, 441 FeatureAES, 442 FeaturePCLMUL, 443 FeatureXSAVE, 444 FeatureXSAVEOPT, 445 FeatureLAHFSAHF 446 ]>; 447 448 class SandyBridgeProc<string Name> : ProcModel<Name, SandyBridgeModel, 449 SNBFeatures.Value, [ 450 FeatureSlowBTMem, 451 FeatureSlowUAMem32 452 ]>; 453 def : SandyBridgeProc<"sandybridge">; 454 def : SandyBridgeProc<"corei7-avx">; // Legacy alias. 455 456 def IVBFeatures : ProcessorFeatures<SNBFeatures.Value, [ 457 FeatureRDRAND, 458 FeatureF16C, 459 FeatureFSGSBase 460 ]>; 461 462 class IvyBridgeProc<string Name> : ProcModel<Name, SandyBridgeModel, 463 IVBFeatures.Value, [ 464 FeatureSlowBTMem, 465 FeatureSlowUAMem32 466 ]>; 467 def : IvyBridgeProc<"ivybridge">; 468 def : IvyBridgeProc<"core-avx-i">; // Legacy alias. 469 470 def HSWFeatures : ProcessorFeatures<IVBFeatures.Value, [ 471 FeatureAVX2, 472 FeatureBMI, 473 FeatureBMI2, 474 FeatureFMA, 475 FeatureLZCNT, 476 FeatureMOVBE, 477 FeatureINVPCID, 478 FeatureVMFUNC, 479 FeatureRTM, 480 FeatureHLE, 481 FeatureSlowIncDec 482 ]>; 483 484 class HaswellProc<string Name> : ProcModel<Name, HaswellModel, 485 HSWFeatures.Value, []>; 486 def : HaswellProc<"haswell">; 487 def : HaswellProc<"core-avx2">; // Legacy alias. 488 489 def BDWFeatures : ProcessorFeatures<HSWFeatures.Value, [ 490 FeatureADX, 491 FeatureRDSEED, 492 FeatureSMAP 493 ]>; 494 class BroadwellProc<string Name> : ProcModel<Name, HaswellModel, 495 BDWFeatures.Value, []>; 496 def : BroadwellProc<"broadwell">; 497 498 def SKLFeatures : ProcessorFeatures<BDWFeatures.Value, [ 499 FeatureMPX, 500 FeatureXSAVEC, 501 FeatureXSAVES, 502 FeatureSGX, 503 FeatureCLFLUSHOPT 504 ]>; 505 506 // FIXME: define SKL model 507 class SkylakeClientProc<string Name> : ProcModel<Name, HaswellModel, 508 SKLFeatures.Value, []>; 509 def : SkylakeClientProc<"skylake">; 510 511 // FIXME: define KNL model 512 class KnightsLandingProc<string Name> : ProcModel<Name, HaswellModel, 513 IVBFeatures.Value, [ 514 FeatureAVX512, 515 FeatureERI, 516 FeatureCDI, 517 FeaturePFI, 518 FeaturePREFETCHWT1, 519 FeatureADX, 520 FeatureRDSEED, 521 FeatureMOVBE, 522 FeatureLZCNT, 523 FeatureBMI, 524 FeatureBMI2, 525 FeatureFMA 526 ]>; 527 def : KnightsLandingProc<"knl">; 528 529 def SKXFeatures : ProcessorFeatures<SKLFeatures.Value, [ 530 FeatureAVX512, 531 FeatureCDI, 532 FeatureDQI, 533 FeatureBWI, 534 FeatureVLX, 535 FeaturePKU, 536 FeaturePCOMMIT, 537 FeatureCLWB 538 ]>; 539 540 // FIXME: define SKX model 541 class SkylakeServerProc<string Name> : ProcModel<Name, HaswellModel, 542 SKXFeatures.Value, []>; 543 def : SkylakeServerProc<"skylake-avx512">; 544 def : SkylakeServerProc<"skx">; // Legacy alias. 545 546 def CNLFeatures : ProcessorFeatures<SKXFeatures.Value, [ 547 FeatureVBMI, 548 FeatureIFMA, 549 FeatureSHA 550 ]>; 551 552 class CannonlakeProc<string Name> : ProcModel<Name, HaswellModel, 553 CNLFeatures.Value, []>; 554 def : CannonlakeProc<"cannonlake">; 555 556 // AMD CPUs. 557 558 def : Proc<"k6", [FeatureX87, FeatureSlowUAMem16, FeatureMMX]>; 559 def : Proc<"k6-2", [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>; 560 def : Proc<"k6-3", [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>; 561 def : Proc<"athlon", [FeatureX87, FeatureSlowUAMem16, Feature3DNowA, 562 FeatureSlowBTMem, FeatureSlowSHLD]>; 563 def : Proc<"athlon-tbird", [FeatureX87, FeatureSlowUAMem16, Feature3DNowA, 564 FeatureSlowBTMem, FeatureSlowSHLD]>; 565 def : Proc<"athlon-4", [FeatureX87, FeatureSlowUAMem16, FeatureSSE1, 566 Feature3DNowA, FeatureFXSR, FeatureSlowBTMem, 567 FeatureSlowSHLD]>; 568 def : Proc<"athlon-xp", [FeatureX87, FeatureSlowUAMem16, FeatureSSE1, 569 Feature3DNowA, FeatureFXSR, FeatureSlowBTMem, 570 FeatureSlowSHLD]>; 571 def : Proc<"athlon-mp", [FeatureX87, FeatureSlowUAMem16, FeatureSSE1, 572 Feature3DNowA, FeatureFXSR, FeatureSlowBTMem, 573 FeatureSlowSHLD]>; 574 def : Proc<"k8", [FeatureX87, FeatureSlowUAMem16, FeatureSSE2, 575 Feature3DNowA, FeatureFXSR, Feature64Bit, 576 FeatureSlowBTMem, FeatureSlowSHLD]>; 577 def : Proc<"opteron", [FeatureX87, FeatureSlowUAMem16, FeatureSSE2, 578 Feature3DNowA, FeatureFXSR, Feature64Bit, 579 FeatureSlowBTMem, FeatureSlowSHLD]>; 580 def : Proc<"athlon64", [FeatureX87, FeatureSlowUAMem16, FeatureSSE2, 581 Feature3DNowA, FeatureFXSR, Feature64Bit, 582 FeatureSlowBTMem, FeatureSlowSHLD]>; 583 def : Proc<"athlon-fx", [FeatureX87, FeatureSlowUAMem16, FeatureSSE2, 584 Feature3DNowA, FeatureFXSR, Feature64Bit, 585 FeatureSlowBTMem, FeatureSlowSHLD]>; 586 def : Proc<"k8-sse3", [FeatureX87, FeatureSlowUAMem16, FeatureSSE3, 587 Feature3DNowA, FeatureFXSR, FeatureCMPXCHG16B, 588 FeatureSlowBTMem, FeatureSlowSHLD]>; 589 def : Proc<"opteron-sse3", [FeatureX87, FeatureSlowUAMem16, FeatureSSE3, 590 Feature3DNowA, FeatureFXSR, FeatureCMPXCHG16B, 591 FeatureSlowBTMem, FeatureSlowSHLD]>; 592 def : Proc<"athlon64-sse3", [FeatureX87, FeatureSlowUAMem16, FeatureSSE3, 593 Feature3DNowA, FeatureFXSR, FeatureCMPXCHG16B, 594 FeatureSlowBTMem, FeatureSlowSHLD]>; 595 def : Proc<"amdfam10", [FeatureX87, FeatureSSE4A, Feature3DNowA, 596 FeatureFXSR, FeatureCMPXCHG16B, FeatureLZCNT, 597 FeaturePOPCNT, FeatureSlowBTMem, FeatureSlowSHLD, 598 FeatureLAHFSAHF]>; 599 def : Proc<"barcelona", [FeatureX87, FeatureSSE4A, Feature3DNowA, 600 FeatureFXSR, FeatureCMPXCHG16B, FeatureLZCNT, 601 FeaturePOPCNT, FeatureSlowBTMem, FeatureSlowSHLD, 602 FeatureLAHFSAHF]>; 603 604 // Bobcat 605 def : Proc<"btver1", [ 606 FeatureX87, 607 FeatureMMX, 608 FeatureSSSE3, 609 FeatureSSE4A, 610 FeatureFXSR, 611 FeatureCMPXCHG16B, 612 FeaturePRFCHW, 613 FeatureLZCNT, 614 FeaturePOPCNT, 615 FeatureSlowSHLD, 616 FeatureLAHFSAHF 617 ]>; 618 619 // Jaguar 620 def : ProcessorModel<"btver2", BtVer2Model, [ 621 FeatureX87, 622 FeatureMMX, 623 FeatureAVX, 624 FeatureFXSR, 625 FeatureSSE4A, 626 FeatureCMPXCHG16B, 627 FeaturePRFCHW, 628 FeatureAES, 629 FeaturePCLMUL, 630 FeatureBMI, 631 FeatureF16C, 632 FeatureMOVBE, 633 FeatureLZCNT, 634 FeaturePOPCNT, 635 FeatureXSAVE, 636 FeatureXSAVEOPT, 637 FeatureSlowSHLD, 638 FeatureLAHFSAHF, 639 FeatureFastPartialYMMWrite 640 ]>; 641 642 // Bulldozer 643 def : Proc<"bdver1", [ 644 FeatureX87, 645 FeatureXOP, 646 FeatureFMA4, 647 FeatureCMPXCHG16B, 648 FeatureAES, 649 FeaturePRFCHW, 650 FeaturePCLMUL, 651 FeatureMMX, 652 FeatureAVX, 653 FeatureFXSR, 654 FeatureSSE4A, 655 FeatureLZCNT, 656 FeaturePOPCNT, 657 FeatureXSAVE, 658 FeatureSlowSHLD, 659 FeatureLAHFSAHF 660 ]>; 661 // Piledriver 662 def : Proc<"bdver2", [ 663 FeatureX87, 664 FeatureXOP, 665 FeatureFMA4, 666 FeatureCMPXCHG16B, 667 FeatureAES, 668 FeaturePRFCHW, 669 FeaturePCLMUL, 670 FeatureMMX, 671 FeatureAVX, 672 FeatureFXSR, 673 FeatureSSE4A, 674 FeatureF16C, 675 FeatureLZCNT, 676 FeaturePOPCNT, 677 FeatureXSAVE, 678 FeatureBMI, 679 FeatureTBM, 680 FeatureFMA, 681 FeatureSlowSHLD, 682 FeatureLAHFSAHF 683 ]>; 684 685 // Steamroller 686 def : Proc<"bdver3", [ 687 FeatureX87, 688 FeatureXOP, 689 FeatureFMA4, 690 FeatureCMPXCHG16B, 691 FeatureAES, 692 FeaturePRFCHW, 693 FeaturePCLMUL, 694 FeatureMMX, 695 FeatureAVX, 696 FeatureFXSR, 697 FeatureSSE4A, 698 FeatureF16C, 699 FeatureLZCNT, 700 FeaturePOPCNT, 701 FeatureXSAVE, 702 FeatureBMI, 703 FeatureTBM, 704 FeatureFMA, 705 FeatureXSAVEOPT, 706 FeatureSlowSHLD, 707 FeatureFSGSBase, 708 FeatureLAHFSAHF 709 ]>; 710 711 // Excavator 712 def : Proc<"bdver4", [ 713 FeatureX87, 714 FeatureMMX, 715 FeatureAVX2, 716 FeatureFXSR, 717 FeatureXOP, 718 FeatureFMA4, 719 FeatureCMPXCHG16B, 720 FeatureAES, 721 FeaturePRFCHW, 722 FeaturePCLMUL, 723 FeatureF16C, 724 FeatureLZCNT, 725 FeaturePOPCNT, 726 FeatureXSAVE, 727 FeatureBMI, 728 FeatureBMI2, 729 FeatureTBM, 730 FeatureFMA, 731 FeatureXSAVEOPT, 732 FeatureFSGSBase, 733 FeatureLAHFSAHF, 734 FeatureMWAITX 735 ]>; 736 737 def : Proc<"geode", [FeatureX87, FeatureSlowUAMem16, Feature3DNowA]>; 738 739 def : Proc<"winchip-c6", [FeatureX87, FeatureSlowUAMem16, FeatureMMX]>; 740 def : Proc<"winchip2", [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>; 741 def : Proc<"c3", [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>; 742 def : Proc<"c3-2", [FeatureX87, FeatureSlowUAMem16, FeatureMMX, 743 FeatureSSE1, FeatureFXSR]>; 744 745 // We also provide a generic 64-bit specific x86 processor model which tries to 746 // be good for modern chips without enabling instruction set encodings past the 747 // basic SSE2 and 64-bit ones. It disables slow things from any mainstream and 748 // modern 64-bit x86 chip, and enables features that are generally beneficial. 749 // 750 // We currently use the Sandy Bridge model as the default scheduling model as 751 // we use it across Nehalem, Westmere, Sandy Bridge, and Ivy Bridge which 752 // covers a huge swath of x86 processors. If there are specific scheduling 753 // knobs which need to be tuned differently for AMD chips, we might consider 754 // forming a common base for them. 755 def : ProcessorModel<"x86-64", SandyBridgeModel, 756 [FeatureX87, FeatureMMX, FeatureSSE2, FeatureFXSR, 757 Feature64Bit, FeatureSlowBTMem ]>; 758 759 //===----------------------------------------------------------------------===// 760 // Register File Description 761 //===----------------------------------------------------------------------===// 762 763 include "X86RegisterInfo.td" 764 765 //===----------------------------------------------------------------------===// 766 // Instruction Descriptions 767 //===----------------------------------------------------------------------===// 768 769 include "X86InstrInfo.td" 770 771 def X86InstrInfo : InstrInfo; 772 773 //===----------------------------------------------------------------------===// 774 // Calling Conventions 775 //===----------------------------------------------------------------------===// 776 777 include "X86CallingConv.td" 778 779 780 //===----------------------------------------------------------------------===// 781 // Assembly Parser 782 //===----------------------------------------------------------------------===// 783 784 def ATTAsmParserVariant : AsmParserVariant { 785 int Variant = 0; 786 787 // Variant name. 788 string Name = "att"; 789 790 // Discard comments in assembly strings. 791 string CommentDelimiter = "#"; 792 793 // Recognize hard coded registers. 794 string RegisterPrefix = "%"; 795 } 796 797 def IntelAsmParserVariant : AsmParserVariant { 798 int Variant = 1; 799 800 // Variant name. 801 string Name = "intel"; 802 803 // Discard comments in assembly strings. 804 string CommentDelimiter = ";"; 805 806 // Recognize hard coded registers. 807 string RegisterPrefix = ""; 808 } 809 810 //===----------------------------------------------------------------------===// 811 // Assembly Printers 812 //===----------------------------------------------------------------------===// 813 814 // The X86 target supports two different syntaxes for emitting machine code. 815 // This is controlled by the -x86-asm-syntax={att|intel} 816 def ATTAsmWriter : AsmWriter { 817 string AsmWriterClassName = "ATTInstPrinter"; 818 int Variant = 0; 819 } 820 def IntelAsmWriter : AsmWriter { 821 string AsmWriterClassName = "IntelInstPrinter"; 822 int Variant = 1; 823 } 824 825 def X86 : Target { 826 // Information about the instructions... 827 let InstructionSet = X86InstrInfo; 828 let AssemblyParserVariants = [ATTAsmParserVariant, IntelAsmParserVariant]; 829 let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter]; 830 } 831
