1 //===- X86InstrFPStack.td - FPU Instruction Set ------------*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes the X86 x87 FPU instruction set, defining the 11 // instructions, and properties of the instructions which are needed for code 12 // generation, machine code emission, and analysis. 13 // 14 //===----------------------------------------------------------------------===// 15 16 //===----------------------------------------------------------------------===// 17 // FPStack specific DAG Nodes. 18 //===----------------------------------------------------------------------===// 19 20 def SDTX86FpGet2 : SDTypeProfile<2, 0, [SDTCisVT<0, f80>, 21 SDTCisVT<1, f80>]>; 22 def SDTX86Fld : SDTypeProfile<1, 2, [SDTCisFP<0>, 23 SDTCisPtrTy<1>, 24 SDTCisVT<2, OtherVT>]>; 25 def SDTX86Fst : SDTypeProfile<0, 3, [SDTCisFP<0>, 26 SDTCisPtrTy<1>, 27 SDTCisVT<2, OtherVT>]>; 28 def SDTX86Fild : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisPtrTy<1>, 29 SDTCisVT<2, OtherVT>]>; 30 def SDTX86Fnstsw : SDTypeProfile<1, 1, [SDTCisVT<0, i16>, SDTCisVT<1, i16>]>; 31 def SDTX86FpToIMem : SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisPtrTy<1>]>; 32 33 def SDTX86CwdStore : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; 34 35 def X86fld : SDNode<"X86ISD::FLD", SDTX86Fld, 36 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 37 def X86fst : SDNode<"X86ISD::FST", SDTX86Fst, 38 [SDNPHasChain, SDNPInGlue, SDNPMayStore, 39 SDNPMemOperand]>; 40 def X86fild : SDNode<"X86ISD::FILD", SDTX86Fild, 41 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 42 def X86fildflag : SDNode<"X86ISD::FILD_FLAG", SDTX86Fild, 43 [SDNPHasChain, SDNPOutGlue, SDNPMayLoad, 44 SDNPMemOperand]>; 45 def X86fp_stsw : SDNode<"X86ISD::FNSTSW16r", SDTX86Fnstsw>; 46 def X86fp_to_i16mem : SDNode<"X86ISD::FP_TO_INT16_IN_MEM", SDTX86FpToIMem, 47 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 48 def X86fp_to_i32mem : SDNode<"X86ISD::FP_TO_INT32_IN_MEM", SDTX86FpToIMem, 49 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 50 def X86fp_to_i64mem : SDNode<"X86ISD::FP_TO_INT64_IN_MEM", SDTX86FpToIMem, 51 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 52 def X86fp_cwd_get16 : SDNode<"X86ISD::FNSTCW16m", SDTX86CwdStore, 53 [SDNPHasChain, SDNPMayStore, SDNPSideEffect, 54 SDNPMemOperand]>; 55 56 //===----------------------------------------------------------------------===// 57 // FPStack pattern fragments 58 //===----------------------------------------------------------------------===// 59 60 def fpimm0 : PatLeaf<(fpimm), [{ 61 return N->isExactlyValue(+0.0); 62 }]>; 63 64 def fpimmneg0 : PatLeaf<(fpimm), [{ 65 return N->isExactlyValue(-0.0); 66 }]>; 67 68 def fpimm1 : PatLeaf<(fpimm), [{ 69 return N->isExactlyValue(+1.0); 70 }]>; 71 72 def fpimmneg1 : PatLeaf<(fpimm), [{ 73 return N->isExactlyValue(-1.0); 74 }]>; 75 76 // Some 'special' instructions 77 let usesCustomInserter = 1 in { // Expanded after instruction selection. 78 def FP32_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP32:$src), 79 [(X86fp_to_i16mem RFP32:$src, addr:$dst)]>; 80 def FP32_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP32:$src), 81 [(X86fp_to_i32mem RFP32:$src, addr:$dst)]>; 82 def FP32_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP32:$src), 83 [(X86fp_to_i64mem RFP32:$src, addr:$dst)]>; 84 def FP64_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP64:$src), 85 [(X86fp_to_i16mem RFP64:$src, addr:$dst)]>; 86 def FP64_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP64:$src), 87 [(X86fp_to_i32mem RFP64:$src, addr:$dst)]>; 88 def FP64_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP64:$src), 89 [(X86fp_to_i64mem RFP64:$src, addr:$dst)]>; 90 def FP80_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP80:$src), 91 [(X86fp_to_i16mem RFP80:$src, addr:$dst)]>; 92 def FP80_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP80:$src), 93 [(X86fp_to_i32mem RFP80:$src, addr:$dst)]>; 94 def FP80_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP80:$src), 95 [(X86fp_to_i64mem RFP80:$src, addr:$dst)]>; 96 } 97 98 // All FP Stack operations are represented with four instructions here. The 99 // first three instructions, generated by the instruction selector, use "RFP32" 100 // "RFP64" or "RFP80" registers: traditional register files to reference 32-bit, 101 // 64-bit or 80-bit floating point values. These sizes apply to the values, 102 // not the registers, which are always 80 bits; RFP32, RFP64 and RFP80 can be 103 // copied to each other without losing information. These instructions are all 104 // pseudo instructions and use the "_Fp" suffix. 105 // In some cases there are additional variants with a mixture of different 106 // register sizes. 107 // The second instruction is defined with FPI, which is the actual instruction 108 // emitted by the assembler. These use "RST" registers, although frequently 109 // the actual register(s) used are implicit. These are always 80 bits. 110 // The FP stackifier pass converts one to the other after register allocation 111 // occurs. 112 // 113 // Note that the FpI instruction should have instruction selection info (e.g. 114 // a pattern) and the FPI instruction should have emission info (e.g. opcode 115 // encoding and asm printing info). 116 117 // FpIf32, FpIf64 - Floating Point Pseudo Instruction template. 118 // f32 instructions can use SSE1 and are predicated on FPStackf32 == !SSE1. 119 // f64 instructions can use SSE2 and are predicated on FPStackf64 == !SSE2. 120 // f80 instructions cannot use SSE and use neither of these. 121 class FpIf32<dag outs, dag ins, FPFormat fp, list<dag> pattern> : 122 FpI_<outs, ins, fp, pattern>, Requires<[FPStackf32]>; 123 class FpIf64<dag outs, dag ins, FPFormat fp, list<dag> pattern> : 124 FpI_<outs, ins, fp, pattern>, Requires<[FPStackf64]>; 125 126 // Factoring for arithmetic. 127 multiclass FPBinary_rr<SDNode OpNode> { 128 // Register op register -> register 129 // These are separated out because they have no reversed form. 130 def _Fp32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2), TwoArgFP, 131 [(set RFP32:$dst, (OpNode RFP32:$src1, RFP32:$src2))]>; 132 def _Fp64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2), TwoArgFP, 133 [(set RFP64:$dst, (OpNode RFP64:$src1, RFP64:$src2))]>; 134 def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2), TwoArgFP, 135 [(set RFP80:$dst, (OpNode RFP80:$src1, RFP80:$src2))]>; 136 } 137 // The FopST0 series are not included here because of the irregularities 138 // in where the 'r' goes in assembly output. 139 // These instructions cannot address 80-bit memory. 140 multiclass FPBinary<SDNode OpNode, Format fp, string asmstring, 141 bit Forward = 1> { 142 // ST(0) = ST(0) + [mem] 143 def _Fp32m : FpIf32<(outs RFP32:$dst), 144 (ins RFP32:$src1, f32mem:$src2), OneArgFPRW, 145 [!if(Forward, 146 (set RFP32:$dst, 147 (OpNode RFP32:$src1, (loadf32 addr:$src2))), 148 (set RFP32:$dst, 149 (OpNode (loadf32 addr:$src2), RFP32:$src1)))]>; 150 def _Fp64m : FpIf64<(outs RFP64:$dst), 151 (ins RFP64:$src1, f64mem:$src2), OneArgFPRW, 152 [!if(Forward, 153 (set RFP64:$dst, 154 (OpNode RFP64:$src1, (loadf64 addr:$src2))), 155 (set RFP64:$dst, 156 (OpNode (loadf64 addr:$src2), RFP64:$src1)))]>; 157 def _Fp64m32: FpIf64<(outs RFP64:$dst), 158 (ins RFP64:$src1, f32mem:$src2), OneArgFPRW, 159 [!if(Forward, 160 (set RFP64:$dst, 161 (OpNode RFP64:$src1, (f64 (extloadf32 addr:$src2)))), 162 (set RFP64:$dst, 163 (OpNode (f64 (extloadf32 addr:$src2)), RFP64:$src1)))]>; 164 def _Fp80m32: FpI_<(outs RFP80:$dst), 165 (ins RFP80:$src1, f32mem:$src2), OneArgFPRW, 166 [!if(Forward, 167 (set RFP80:$dst, 168 (OpNode RFP80:$src1, (f80 (extloadf32 addr:$src2)))), 169 (set RFP80:$dst, 170 (OpNode (f80 (extloadf32 addr:$src2)), RFP80:$src1)))]>; 171 def _Fp80m64: FpI_<(outs RFP80:$dst), 172 (ins RFP80:$src1, f64mem:$src2), OneArgFPRW, 173 [!if(Forward, 174 (set RFP80:$dst, 175 (OpNode RFP80:$src1, (f80 (extloadf64 addr:$src2)))), 176 (set RFP80:$dst, 177 (OpNode (f80 (extloadf64 addr:$src2)), RFP80:$src1)))]>; 178 let mayLoad = 1 in 179 def _F32m : FPI<0xD8, fp, (outs), (ins f32mem:$src), 180 !strconcat("f", asmstring, "{s}\t$src")>; 181 let mayLoad = 1 in 182 def _F64m : FPI<0xDC, fp, (outs), (ins f64mem:$src), 183 !strconcat("f", asmstring, "{l}\t$src")>; 184 // ST(0) = ST(0) + [memint] 185 def _FpI16m32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, i16mem:$src2), 186 OneArgFPRW, 187 [!if(Forward, 188 (set RFP32:$dst, 189 (OpNode RFP32:$src1, (X86fild addr:$src2, i16))), 190 (set RFP32:$dst, 191 (OpNode (X86fild addr:$src2, i16), RFP32:$src1)))]>; 192 def _FpI32m32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, i32mem:$src2), 193 OneArgFPRW, 194 [!if(Forward, 195 (set RFP32:$dst, 196 (OpNode RFP32:$src1, (X86fild addr:$src2, i32))), 197 (set RFP32:$dst, 198 (OpNode (X86fild addr:$src2, i32), RFP32:$src1)))]>; 199 def _FpI16m64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, i16mem:$src2), 200 OneArgFPRW, 201 [!if(Forward, 202 (set RFP64:$dst, 203 (OpNode RFP64:$src1, (X86fild addr:$src2, i16))), 204 (set RFP64:$dst, 205 (OpNode (X86fild addr:$src2, i16), RFP64:$src1)))]>; 206 def _FpI32m64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, i32mem:$src2), 207 OneArgFPRW, 208 [!if(Forward, 209 (set RFP64:$dst, 210 (OpNode RFP64:$src1, (X86fild addr:$src2, i32))), 211 (set RFP64:$dst, 212 (OpNode (X86fild addr:$src2, i32), RFP64:$src1)))]>; 213 def _FpI16m80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, i16mem:$src2), 214 OneArgFPRW, 215 [!if(Forward, 216 (set RFP80:$dst, 217 (OpNode RFP80:$src1, (X86fild addr:$src2, i16))), 218 (set RFP80:$dst, 219 (OpNode (X86fild addr:$src2, i16), RFP80:$src1)))]>; 220 def _FpI32m80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, i32mem:$src2), 221 OneArgFPRW, 222 [!if(Forward, 223 (set RFP80:$dst, 224 (OpNode RFP80:$src1, (X86fild addr:$src2, i32))), 225 (set RFP80:$dst, 226 (OpNode (X86fild addr:$src2, i32), RFP80:$src1)))]>; 227 let mayLoad = 1 in 228 def _FI16m : FPI<0xDE, fp, (outs), (ins i16mem:$src), 229 !strconcat("fi", asmstring, "{s}\t$src")>; 230 let mayLoad = 1 in 231 def _FI32m : FPI<0xDA, fp, (outs), (ins i32mem:$src), 232 !strconcat("fi", asmstring, "{l}\t$src")>; 233 } 234 235 let Defs = [FPSW] in { 236 // FPBinary_rr just defines pseudo-instructions, no need to set a scheduling 237 // resources. 238 defm ADD : FPBinary_rr<fadd>; 239 defm SUB : FPBinary_rr<fsub>; 240 defm MUL : FPBinary_rr<fmul>; 241 defm DIV : FPBinary_rr<fdiv>; 242 // Sets the scheduling resources for the actual NAME#_F<size>m defintions. 243 let SchedRW = [WriteFAddLd] in { 244 defm ADD : FPBinary<fadd, MRM0m, "add">; 245 defm SUB : FPBinary<fsub, MRM4m, "sub">; 246 defm SUBR: FPBinary<fsub ,MRM5m, "subr", 0>; 247 } 248 let SchedRW = [WriteFMulLd] in { 249 defm MUL : FPBinary<fmul, MRM1m, "mul">; 250 } 251 let SchedRW = [WriteFDivLd] in { 252 defm DIV : FPBinary<fdiv, MRM6m, "div">; 253 defm DIVR: FPBinary<fdiv, MRM7m, "divr", 0>; 254 } 255 } 256 257 class FPST0rInst<Format fp, string asm> 258 : FPI<0xD8, fp, (outs), (ins RST:$op), asm>; 259 class FPrST0Inst<Format fp, string asm> 260 : FPI<0xDC, fp, (outs), (ins RST:$op), asm>; 261 class FPrST0PInst<Format fp, string asm> 262 : FPI<0xDE, fp, (outs), (ins RST:$op), asm>; 263 264 // NOTE: GAS and apparently all other AT&T style assemblers have a broken notion 265 // of some of the 'reverse' forms of the fsub and fdiv instructions. As such, 266 // we have to put some 'r's in and take them out of weird places. 267 let SchedRW = [WriteFAdd] in { 268 def ADD_FST0r : FPST0rInst <MRM0r, "fadd\t$op">; 269 def ADD_FrST0 : FPrST0Inst <MRM0r, "fadd\t{%st(0), $op|$op, st(0)}">; 270 def ADD_FPrST0 : FPrST0PInst<MRM0r, "faddp\t$op">; 271 def SUBR_FST0r : FPST0rInst <MRM5r, "fsubr\t$op">; 272 def SUB_FrST0 : FPrST0Inst <MRM5r, "fsub{r}\t{%st(0), $op|$op, st(0)}">; 273 def SUB_FPrST0 : FPrST0PInst<MRM5r, "fsub{r}p\t$op">; 274 def SUB_FST0r : FPST0rInst <MRM4r, "fsub\t$op">; 275 def SUBR_FrST0 : FPrST0Inst <MRM4r, "fsub{|r}\t{%st(0), $op|$op, st(0)}">; 276 def SUBR_FPrST0 : FPrST0PInst<MRM4r, "fsub{|r}p\t$op">; 277 } // SchedRW 278 let SchedRW = [WriteFMul] in { 279 def MUL_FST0r : FPST0rInst <MRM1r, "fmul\t$op">; 280 def MUL_FrST0 : FPrST0Inst <MRM1r, "fmul\t{%st(0), $op|$op, st(0)}">; 281 def MUL_FPrST0 : FPrST0PInst<MRM1r, "fmulp\t$op">; 282 } // SchedRW 283 let SchedRW = [WriteFDiv] in { 284 def DIVR_FST0r : FPST0rInst <MRM7r, "fdivr\t$op">; 285 def DIV_FrST0 : FPrST0Inst <MRM7r, "fdiv{r}\t{%st(0), $op|$op, st(0)}">; 286 def DIV_FPrST0 : FPrST0PInst<MRM7r, "fdiv{r}p\t$op">; 287 def DIV_FST0r : FPST0rInst <MRM6r, "fdiv\t$op">; 288 def DIVR_FrST0 : FPrST0Inst <MRM6r, "fdiv{|r}\t{%st(0), $op|$op, st(0)}">; 289 def DIVR_FPrST0 : FPrST0PInst<MRM6r, "fdiv{|r}p\t$op">; 290 } // SchedRW 291 292 def COM_FST0r : FPST0rInst <MRM2r, "fcom\t$op">; 293 def COMP_FST0r : FPST0rInst <MRM3r, "fcomp\t$op">; 294 295 // Unary operations. 296 multiclass FPUnary<SDNode OpNode, Format fp, string asmstring> { 297 def _Fp32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src), OneArgFPRW, 298 [(set RFP32:$dst, (OpNode RFP32:$src))]>; 299 def _Fp64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src), OneArgFPRW, 300 [(set RFP64:$dst, (OpNode RFP64:$src))]>; 301 def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src), OneArgFPRW, 302 [(set RFP80:$dst, (OpNode RFP80:$src))]>; 303 def _F : FPI<0xD9, fp, (outs), (ins), asmstring>; 304 } 305 306 let Defs = [FPSW] in { 307 defm CHS : FPUnary<fneg, MRM_E0, "fchs">; 308 defm ABS : FPUnary<fabs, MRM_E1, "fabs">; 309 let SchedRW = [WriteFSqrt] in { 310 defm SQRT: FPUnary<fsqrt,MRM_FA, "fsqrt">; 311 } 312 defm SIN : FPUnary<fsin, MRM_FE, "fsin">; 313 defm COS : FPUnary<fcos, MRM_FF, "fcos">; 314 315 let hasSideEffects = 0 in { 316 def TST_Fp32 : FpIf32<(outs), (ins RFP32:$src), OneArgFP, []>; 317 def TST_Fp64 : FpIf64<(outs), (ins RFP64:$src), OneArgFP, []>; 318 def TST_Fp80 : FpI_<(outs), (ins RFP80:$src), OneArgFP, []>; 319 } 320 def TST_F : FPI<0xD9, MRM_E4, (outs), (ins), "ftst">; 321 } // Defs = [FPSW] 322 323 // Versions of FP instructions that take a single memory operand. Added for the 324 // disassembler; remove as they are included with patterns elsewhere. 325 def FCOM32m : FPI<0xD8, MRM2m, (outs), (ins f32mem:$src), "fcom{s}\t$src">; 326 def FCOMP32m : FPI<0xD8, MRM3m, (outs), (ins f32mem:$src), "fcomp{s}\t$src">; 327 328 def FLDENVm : FPI<0xD9, MRM4m, (outs), (ins f32mem:$src), "fldenv\t$src">; 329 def FSTENVm : FPI<0xD9, MRM6m, (outs), (ins f32mem:$dst), "fnstenv\t$dst">; 330 331 def FICOM32m : FPI<0xDA, MRM2m, (outs), (ins i32mem:$src), "ficom{l}\t$src">; 332 def FICOMP32m: FPI<0xDA, MRM3m, (outs), (ins i32mem:$src), "ficomp{l}\t$src">; 333 334 def FCOM64m : FPI<0xDC, MRM2m, (outs), (ins f64mem:$src), "fcom{l}\t$src">; 335 def FCOMP64m : FPI<0xDC, MRM3m, (outs), (ins f64mem:$src), "fcomp{l}\t$src">; 336 337 def FRSTORm : FPI<0xDD, MRM4m, (outs), (ins f32mem:$dst), "frstor\t$dst">; 338 def FSAVEm : FPI<0xDD, MRM6m, (outs), (ins f32mem:$dst), "fnsave\t$dst">; 339 def FNSTSWm : FPI<0xDD, MRM7m, (outs), (ins i16mem:$dst), "fnstsw\t$dst">; 340 341 def FICOM16m : FPI<0xDE, MRM2m, (outs), (ins i16mem:$src), "ficom{s}\t$src">; 342 def FICOMP16m: FPI<0xDE, MRM3m, (outs), (ins i16mem:$src), "ficomp{s}\t$src">; 343 344 def FBLDm : FPI<0xDF, MRM4m, (outs), (ins f80mem:$src), "fbld\t$src">; 345 def FBSTPm : FPI<0xDF, MRM6m, (outs), (ins f80mem:$dst), "fbstp\t$dst">; 346 347 // Floating point cmovs. 348 class FpIf32CMov<dag outs, dag ins, FPFormat fp, list<dag> pattern> : 349 FpI_<outs, ins, fp, pattern>, Requires<[FPStackf32, HasCMov]>; 350 class FpIf64CMov<dag outs, dag ins, FPFormat fp, list<dag> pattern> : 351 FpI_<outs, ins, fp, pattern>, Requires<[FPStackf64, HasCMov]>; 352 353 multiclass FPCMov<PatLeaf cc> { 354 def _Fp32 : FpIf32CMov<(outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2), 355 CondMovFP, 356 [(set RFP32:$dst, (X86cmov RFP32:$src1, RFP32:$src2, 357 cc, EFLAGS))]>; 358 def _Fp64 : FpIf64CMov<(outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2), 359 CondMovFP, 360 [(set RFP64:$dst, (X86cmov RFP64:$src1, RFP64:$src2, 361 cc, EFLAGS))]>; 362 def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2), 363 CondMovFP, 364 [(set RFP80:$dst, (X86cmov RFP80:$src1, RFP80:$src2, 365 cc, EFLAGS))]>, 366 Requires<[HasCMov]>; 367 } 368 369 let Defs = [FPSW] in { 370 let Uses = [EFLAGS], Constraints = "$src1 = $dst" in { 371 defm CMOVB : FPCMov<X86_COND_B>; 372 defm CMOVBE : FPCMov<X86_COND_BE>; 373 defm CMOVE : FPCMov<X86_COND_E>; 374 defm CMOVP : FPCMov<X86_COND_P>; 375 defm CMOVNB : FPCMov<X86_COND_AE>; 376 defm CMOVNBE: FPCMov<X86_COND_A>; 377 defm CMOVNE : FPCMov<X86_COND_NE>; 378 defm CMOVNP : FPCMov<X86_COND_NP>; 379 } // Uses = [EFLAGS], Constraints = "$src1 = $dst" 380 381 let Predicates = [HasCMov] in { 382 // These are not factored because there's no clean way to pass DA/DB. 383 def CMOVB_F : FPI<0xDA, MRM0r, (outs), (ins RST:$op), 384 "fcmovb\t{$op, %st(0)|st(0), $op}">; 385 def CMOVBE_F : FPI<0xDA, MRM2r, (outs), (ins RST:$op), 386 "fcmovbe\t{$op, %st(0)|st(0), $op}">; 387 def CMOVE_F : FPI<0xDA, MRM1r, (outs), (ins RST:$op), 388 "fcmove\t{$op, %st(0)|st(0), $op}">; 389 def CMOVP_F : FPI<0xDA, MRM3r, (outs), (ins RST:$op), 390 "fcmovu\t{$op, %st(0)|st(0), $op}">; 391 def CMOVNB_F : FPI<0xDB, MRM0r, (outs), (ins RST:$op), 392 "fcmovnb\t{$op, %st(0)|st(0), $op}">; 393 def CMOVNBE_F: FPI<0xDB, MRM2r, (outs), (ins RST:$op), 394 "fcmovnbe\t{$op, %st(0)|st(0), $op}">; 395 def CMOVNE_F : FPI<0xDB, MRM1r, (outs), (ins RST:$op), 396 "fcmovne\t{$op, %st(0)|st(0), $op}">; 397 def CMOVNP_F : FPI<0xDB, MRM3r, (outs), (ins RST:$op), 398 "fcmovnu\t{$op, %st(0)|st(0), $op}">; 399 } // Predicates = [HasCMov] 400 401 // Floating point loads & stores. 402 let canFoldAsLoad = 1 in { 403 def LD_Fp32m : FpIf32<(outs RFP32:$dst), (ins f32mem:$src), ZeroArgFP, 404 [(set RFP32:$dst, (loadf32 addr:$src))]>; 405 let isReMaterializable = 1 in 406 def LD_Fp64m : FpIf64<(outs RFP64:$dst), (ins f64mem:$src), ZeroArgFP, 407 [(set RFP64:$dst, (loadf64 addr:$src))]>; 408 def LD_Fp80m : FpI_<(outs RFP80:$dst), (ins f80mem:$src), ZeroArgFP, 409 [(set RFP80:$dst, (loadf80 addr:$src))]>; 410 } 411 def LD_Fp32m64 : FpIf64<(outs RFP64:$dst), (ins f32mem:$src), ZeroArgFP, 412 [(set RFP64:$dst, (f64 (extloadf32 addr:$src)))]>; 413 def LD_Fp64m80 : FpI_<(outs RFP80:$dst), (ins f64mem:$src), ZeroArgFP, 414 [(set RFP80:$dst, (f80 (extloadf64 addr:$src)))]>; 415 def LD_Fp32m80 : FpI_<(outs RFP80:$dst), (ins f32mem:$src), ZeroArgFP, 416 [(set RFP80:$dst, (f80 (extloadf32 addr:$src)))]>; 417 def ILD_Fp16m32: FpIf32<(outs RFP32:$dst), (ins i16mem:$src), ZeroArgFP, 418 [(set RFP32:$dst, (X86fild addr:$src, i16))]>; 419 def ILD_Fp32m32: FpIf32<(outs RFP32:$dst), (ins i32mem:$src), ZeroArgFP, 420 [(set RFP32:$dst, (X86fild addr:$src, i32))]>; 421 def ILD_Fp64m32: FpIf32<(outs RFP32:$dst), (ins i64mem:$src), ZeroArgFP, 422 [(set RFP32:$dst, (X86fild addr:$src, i64))]>; 423 def ILD_Fp16m64: FpIf64<(outs RFP64:$dst), (ins i16mem:$src), ZeroArgFP, 424 [(set RFP64:$dst, (X86fild addr:$src, i16))]>; 425 def ILD_Fp32m64: FpIf64<(outs RFP64:$dst), (ins i32mem:$src), ZeroArgFP, 426 [(set RFP64:$dst, (X86fild addr:$src, i32))]>; 427 def ILD_Fp64m64: FpIf64<(outs RFP64:$dst), (ins i64mem:$src), ZeroArgFP, 428 [(set RFP64:$dst, (X86fild addr:$src, i64))]>; 429 def ILD_Fp16m80: FpI_<(outs RFP80:$dst), (ins i16mem:$src), ZeroArgFP, 430 [(set RFP80:$dst, (X86fild addr:$src, i16))]>; 431 def ILD_Fp32m80: FpI_<(outs RFP80:$dst), (ins i32mem:$src), ZeroArgFP, 432 [(set RFP80:$dst, (X86fild addr:$src, i32))]>; 433 def ILD_Fp64m80: FpI_<(outs RFP80:$dst), (ins i64mem:$src), ZeroArgFP, 434 [(set RFP80:$dst, (X86fild addr:$src, i64))]>; 435 436 def ST_Fp32m : FpIf32<(outs), (ins f32mem:$op, RFP32:$src), OneArgFP, 437 [(store RFP32:$src, addr:$op)]>; 438 def ST_Fp64m32 : FpIf64<(outs), (ins f32mem:$op, RFP64:$src), OneArgFP, 439 [(truncstoref32 RFP64:$src, addr:$op)]>; 440 def ST_Fp64m : FpIf64<(outs), (ins f64mem:$op, RFP64:$src), OneArgFP, 441 [(store RFP64:$src, addr:$op)]>; 442 def ST_Fp80m32 : FpI_<(outs), (ins f32mem:$op, RFP80:$src), OneArgFP, 443 [(truncstoref32 RFP80:$src, addr:$op)]>; 444 def ST_Fp80m64 : FpI_<(outs), (ins f64mem:$op, RFP80:$src), OneArgFP, 445 [(truncstoref64 RFP80:$src, addr:$op)]>; 446 // FST does not support 80-bit memory target; FSTP must be used. 447 448 let mayStore = 1, hasSideEffects = 0 in { 449 def ST_FpP32m : FpIf32<(outs), (ins f32mem:$op, RFP32:$src), OneArgFP, []>; 450 def ST_FpP64m32 : FpIf64<(outs), (ins f32mem:$op, RFP64:$src), OneArgFP, []>; 451 def ST_FpP64m : FpIf64<(outs), (ins f64mem:$op, RFP64:$src), OneArgFP, []>; 452 def ST_FpP80m32 : FpI_<(outs), (ins f32mem:$op, RFP80:$src), OneArgFP, []>; 453 def ST_FpP80m64 : FpI_<(outs), (ins f64mem:$op, RFP80:$src), OneArgFP, []>; 454 } 455 def ST_FpP80m : FpI_<(outs), (ins f80mem:$op, RFP80:$src), OneArgFP, 456 [(store RFP80:$src, addr:$op)]>; 457 let mayStore = 1, hasSideEffects = 0 in { 458 def IST_Fp16m32 : FpIf32<(outs), (ins i16mem:$op, RFP32:$src), OneArgFP, []>; 459 def IST_Fp32m32 : FpIf32<(outs), (ins i32mem:$op, RFP32:$src), OneArgFP, []>; 460 def IST_Fp64m32 : FpIf32<(outs), (ins i64mem:$op, RFP32:$src), OneArgFP, []>; 461 def IST_Fp16m64 : FpIf64<(outs), (ins i16mem:$op, RFP64:$src), OneArgFP, []>; 462 def IST_Fp32m64 : FpIf64<(outs), (ins i32mem:$op, RFP64:$src), OneArgFP, []>; 463 def IST_Fp64m64 : FpIf64<(outs), (ins i64mem:$op, RFP64:$src), OneArgFP, []>; 464 def IST_Fp16m80 : FpI_<(outs), (ins i16mem:$op, RFP80:$src), OneArgFP, []>; 465 def IST_Fp32m80 : FpI_<(outs), (ins i32mem:$op, RFP80:$src), OneArgFP, []>; 466 def IST_Fp64m80 : FpI_<(outs), (ins i64mem:$op, RFP80:$src), OneArgFP, []>; 467 } 468 469 let mayLoad = 1, SchedRW = [WriteLoad] in { 470 def LD_F32m : FPI<0xD9, MRM0m, (outs), (ins f32mem:$src), "fld{s}\t$src", 471 IIC_FLD>; 472 def LD_F64m : FPI<0xDD, MRM0m, (outs), (ins f64mem:$src), "fld{l}\t$src", 473 IIC_FLD>; 474 def LD_F80m : FPI<0xDB, MRM5m, (outs), (ins f80mem:$src), "fld{t}\t$src", 475 IIC_FLD80>; 476 def ILD_F16m : FPI<0xDF, MRM0m, (outs), (ins i16mem:$src), "fild{s}\t$src", 477 IIC_FILD>; 478 def ILD_F32m : FPI<0xDB, MRM0m, (outs), (ins i32mem:$src), "fild{l}\t$src", 479 IIC_FILD>; 480 def ILD_F64m : FPI<0xDF, MRM5m, (outs), (ins i64mem:$src), "fild{ll}\t$src", 481 IIC_FILD>; 482 } 483 let mayStore = 1, SchedRW = [WriteStore] in { 484 def ST_F32m : FPI<0xD9, MRM2m, (outs), (ins f32mem:$dst), "fst{s}\t$dst", 485 IIC_FST>; 486 def ST_F64m : FPI<0xDD, MRM2m, (outs), (ins f64mem:$dst), "fst{l}\t$dst", 487 IIC_FST>; 488 def ST_FP32m : FPI<0xD9, MRM3m, (outs), (ins f32mem:$dst), "fstp{s}\t$dst", 489 IIC_FST>; 490 def ST_FP64m : FPI<0xDD, MRM3m, (outs), (ins f64mem:$dst), "fstp{l}\t$dst", 491 IIC_FST>; 492 def ST_FP80m : FPI<0xDB, MRM7m, (outs), (ins f80mem:$dst), "fstp{t}\t$dst", 493 IIC_FST80>; 494 def IST_F16m : FPI<0xDF, MRM2m, (outs), (ins i16mem:$dst), "fist{s}\t$dst", 495 IIC_FIST>; 496 def IST_F32m : FPI<0xDB, MRM2m, (outs), (ins i32mem:$dst), "fist{l}\t$dst", 497 IIC_FIST>; 498 def IST_FP16m : FPI<0xDF, MRM3m, (outs), (ins i16mem:$dst), "fistp{s}\t$dst", 499 IIC_FIST>; 500 def IST_FP32m : FPI<0xDB, MRM3m, (outs), (ins i32mem:$dst), "fistp{l}\t$dst", 501 IIC_FIST>; 502 def IST_FP64m : FPI<0xDF, MRM7m, (outs), (ins i64mem:$dst), "fistp{ll}\t$dst", 503 IIC_FIST>; 504 } 505 506 // FISTTP requires SSE3 even though it's a FPStack op. 507 let Predicates = [HasSSE3] in { 508 def ISTT_Fp16m32 : FpI_<(outs), (ins i16mem:$op, RFP32:$src), OneArgFP, 509 [(X86fp_to_i16mem RFP32:$src, addr:$op)]>; 510 def ISTT_Fp32m32 : FpI_<(outs), (ins i32mem:$op, RFP32:$src), OneArgFP, 511 [(X86fp_to_i32mem RFP32:$src, addr:$op)]>; 512 def ISTT_Fp64m32 : FpI_<(outs), (ins i64mem:$op, RFP32:$src), OneArgFP, 513 [(X86fp_to_i64mem RFP32:$src, addr:$op)]>; 514 def ISTT_Fp16m64 : FpI_<(outs), (ins i16mem:$op, RFP64:$src), OneArgFP, 515 [(X86fp_to_i16mem RFP64:$src, addr:$op)]>; 516 def ISTT_Fp32m64 : FpI_<(outs), (ins i32mem:$op, RFP64:$src), OneArgFP, 517 [(X86fp_to_i32mem RFP64:$src, addr:$op)]>; 518 def ISTT_Fp64m64 : FpI_<(outs), (ins i64mem:$op, RFP64:$src), OneArgFP, 519 [(X86fp_to_i64mem RFP64:$src, addr:$op)]>; 520 def ISTT_Fp16m80 : FpI_<(outs), (ins i16mem:$op, RFP80:$src), OneArgFP, 521 [(X86fp_to_i16mem RFP80:$src, addr:$op)]>; 522 def ISTT_Fp32m80 : FpI_<(outs), (ins i32mem:$op, RFP80:$src), OneArgFP, 523 [(X86fp_to_i32mem RFP80:$src, addr:$op)]>; 524 def ISTT_Fp64m80 : FpI_<(outs), (ins i64mem:$op, RFP80:$src), OneArgFP, 525 [(X86fp_to_i64mem RFP80:$src, addr:$op)]>; 526 } // Predicates = [HasSSE3] 527 528 let mayStore = 1, SchedRW = [WriteStore] in { 529 def ISTT_FP16m : FPI<0xDF, MRM1m, (outs), (ins i16mem:$dst), "fisttp{s}\t$dst", 530 IIC_FST>; 531 def ISTT_FP32m : FPI<0xDB, MRM1m, (outs), (ins i32mem:$dst), "fisttp{l}\t$dst", 532 IIC_FST>; 533 def ISTT_FP64m : FPI<0xDD, MRM1m, (outs), (ins i64mem:$dst), 534 "fisttp{ll}\t$dst", IIC_FST>; 535 } 536 537 // FP Stack manipulation instructions. 538 let SchedRW = [WriteMove] in { 539 def LD_Frr : FPI<0xD9, MRM0r, (outs), (ins RST:$op), "fld\t$op", IIC_FLD>; 540 def ST_Frr : FPI<0xDD, MRM2r, (outs), (ins RST:$op), "fst\t$op", IIC_FST>; 541 def ST_FPrr : FPI<0xDD, MRM3r, (outs), (ins RST:$op), "fstp\t$op", IIC_FST>; 542 def XCH_F : FPI<0xD9, MRM1r, (outs), (ins RST:$op), "fxch\t$op", IIC_FXCH>; 543 } 544 545 // Floating point constant loads. 546 let isReMaterializable = 1 in { 547 def LD_Fp032 : FpIf32<(outs RFP32:$dst), (ins), ZeroArgFP, 548 [(set RFP32:$dst, fpimm0)]>; 549 def LD_Fp132 : FpIf32<(outs RFP32:$dst), (ins), ZeroArgFP, 550 [(set RFP32:$dst, fpimm1)]>; 551 def LD_Fp064 : FpIf64<(outs RFP64:$dst), (ins), ZeroArgFP, 552 [(set RFP64:$dst, fpimm0)]>; 553 def LD_Fp164 : FpIf64<(outs RFP64:$dst), (ins), ZeroArgFP, 554 [(set RFP64:$dst, fpimm1)]>; 555 def LD_Fp080 : FpI_<(outs RFP80:$dst), (ins), ZeroArgFP, 556 [(set RFP80:$dst, fpimm0)]>; 557 def LD_Fp180 : FpI_<(outs RFP80:$dst), (ins), ZeroArgFP, 558 [(set RFP80:$dst, fpimm1)]>; 559 } 560 561 let SchedRW = [WriteZero] in { 562 def LD_F0 : FPI<0xD9, MRM_EE, (outs), (ins), "fldz", IIC_FLDZ>; 563 def LD_F1 : FPI<0xD9, MRM_E8, (outs), (ins), "fld1", IIC_FIST>; 564 } 565 566 // Floating point compares. 567 let SchedRW = [WriteFAdd] in { 568 def UCOM_Fpr32 : FpIf32<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP, 569 [(set FPSW, (trunc (X86cmp RFP32:$lhs, RFP32:$rhs)))]>; 570 def UCOM_Fpr64 : FpIf64<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP, 571 [(set FPSW, (trunc (X86cmp RFP64:$lhs, RFP64:$rhs)))]>; 572 def UCOM_Fpr80 : FpI_ <(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, 573 [(set FPSW, (trunc (X86cmp RFP80:$lhs, RFP80:$rhs)))]>; 574 } // SchedRW 575 } // Defs = [FPSW] 576 577 let SchedRW = [WriteFAdd] in { 578 // CC = ST(0) cmp ST(i) 579 let Defs = [EFLAGS, FPSW] in { 580 def UCOM_FpIr32: FpIf32<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP, 581 [(set EFLAGS, (X86cmp RFP32:$lhs, RFP32:$rhs))]>; 582 def UCOM_FpIr64: FpIf64<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP, 583 [(set EFLAGS, (X86cmp RFP64:$lhs, RFP64:$rhs))]>; 584 def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, 585 [(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>; 586 } 587 588 let Defs = [FPSW], Uses = [ST0] in { 589 def UCOM_Fr : FPI<0xDD, MRM4r, // FPSW = cmp ST(0) with ST(i) 590 (outs), (ins RST:$reg), "fucom\t$reg", IIC_FUCOM>; 591 def UCOM_FPr : FPI<0xDD, MRM5r, // FPSW = cmp ST(0) with ST(i), pop 592 (outs), (ins RST:$reg), "fucomp\t$reg", IIC_FUCOM>; 593 def UCOM_FPPr : FPI<0xDA, MRM_E9, // cmp ST(0) with ST(1), pop, pop 594 (outs), (ins), "fucompp", IIC_FUCOM>; 595 } 596 597 let Defs = [EFLAGS, FPSW], Uses = [ST0] in { 598 def UCOM_FIr : FPI<0xDB, MRM5r, // CC = cmp ST(0) with ST(i) 599 (outs), (ins RST:$reg), "fucomi\t$reg", IIC_FUCOMI>; 600 def UCOM_FIPr : FPI<0xDF, MRM5r, // CC = cmp ST(0) with ST(i), pop 601 (outs), (ins RST:$reg), "fucompi\t$reg", IIC_FUCOMI>; 602 } 603 604 let Defs = [EFLAGS, FPSW] in { 605 def COM_FIr : FPI<0xDB, MRM6r, (outs), (ins RST:$reg), 606 "fcomi\t$reg", IIC_FCOMI>; 607 def COM_FIPr : FPI<0xDF, MRM6r, (outs), (ins RST:$reg), 608 "fcompi\t$reg", IIC_FCOMI>; 609 } 610 } // SchedRW 611 612 // Floating point flag ops. 613 let SchedRW = [WriteALU] in { 614 let Defs = [AX], Uses = [FPSW] in 615 def FNSTSW16r : I<0xDF, MRM_E0, // AX = fp flags 616 (outs), (ins), "fnstsw\t{%ax|ax}", 617 [(set AX, (X86fp_stsw FPSW))], IIC_FNSTSW>; 618 619 def FNSTCW16m : I<0xD9, MRM7m, // [mem16] = X87 control world 620 (outs), (ins i16mem:$dst), "fnstcw\t$dst", 621 [(X86fp_cwd_get16 addr:$dst)], IIC_FNSTCW>; 622 } // SchedRW 623 let mayLoad = 1 in 624 def FLDCW16m : I<0xD9, MRM5m, // X87 control world = [mem16] 625 (outs), (ins i16mem:$dst), "fldcw\t$dst", [], IIC_FLDCW>, 626 Sched<[WriteLoad]>; 627 628 // FPU control instructions 629 let SchedRW = [WriteMicrocoded] in { 630 let Defs = [FPSW] in 631 def FNINIT : I<0xDB, MRM_E3, (outs), (ins), "fninit", [], IIC_FNINIT>; 632 def FFREE : FPI<0xDD, MRM0r, (outs), (ins RST:$reg), 633 "ffree\t$reg", IIC_FFREE>; 634 // Clear exceptions 635 636 let Defs = [FPSW] in 637 def FNCLEX : I<0xDB, MRM_E2, (outs), (ins), "fnclex", [], IIC_FNCLEX>; 638 } // SchedRW 639 640 // Operandless floating-point instructions for the disassembler. 641 let SchedRW = [WriteMicrocoded] in { 642 def WAIT : I<0x9B, RawFrm, (outs), (ins), "wait", [], IIC_WAIT>; 643 644 def FNOP : I<0xD9, MRM_D0, (outs), (ins), "fnop", [], IIC_FNOP>; 645 def FXAM : I<0xD9, MRM_E5, (outs), (ins), "fxam", [], IIC_FXAM>; 646 def FLDL2T : I<0xD9, MRM_E9, (outs), (ins), "fldl2t", [], IIC_FLDL>; 647 def FLDL2E : I<0xD9, MRM_EA, (outs), (ins), "fldl2e", [], IIC_FLDL>; 648 def FLDPI : I<0xD9, MRM_EB, (outs), (ins), "fldpi", [], IIC_FLDL>; 649 def FLDLG2 : I<0xD9, MRM_EC, (outs), (ins), "fldlg2", [], IIC_FLDL>; 650 def FLDLN2 : I<0xD9, MRM_ED, (outs), (ins), "fldln2", [], IIC_FLDL>; 651 def F2XM1 : I<0xD9, MRM_F0, (outs), (ins), "f2xm1", [], IIC_F2XM1>; 652 def FYL2X : I<0xD9, MRM_F1, (outs), (ins), "fyl2x", [], IIC_FYL2X>; 653 def FPTAN : I<0xD9, MRM_F2, (outs), (ins), "fptan", [], IIC_FPTAN>; 654 def FPATAN : I<0xD9, MRM_F3, (outs), (ins), "fpatan", [], IIC_FPATAN>; 655 def FXTRACT : I<0xD9, MRM_F4, (outs), (ins), "fxtract", [], IIC_FXTRACT>; 656 def FPREM1 : I<0xD9, MRM_F5, (outs), (ins), "fprem1", [], IIC_FPREM1>; 657 def FDECSTP : I<0xD9, MRM_F6, (outs), (ins), "fdecstp", [], IIC_FPSTP>; 658 def FINCSTP : I<0xD9, MRM_F7, (outs), (ins), "fincstp", [], IIC_FPSTP>; 659 def FPREM : I<0xD9, MRM_F8, (outs), (ins), "fprem", [], IIC_FPREM>; 660 def FYL2XP1 : I<0xD9, MRM_F9, (outs), (ins), "fyl2xp1", [], IIC_FYL2XP1>; 661 def FSINCOS : I<0xD9, MRM_FB, (outs), (ins), "fsincos", [], IIC_FSINCOS>; 662 def FRNDINT : I<0xD9, MRM_FC, (outs), (ins), "frndint", [], IIC_FRNDINT>; 663 def FSCALE : I<0xD9, MRM_FD, (outs), (ins), "fscale", [], IIC_FSCALE>; 664 def FCOMPP : I<0xDE, MRM_D9, (outs), (ins), "fcompp", [], IIC_FCOMPP>; 665 666 let Predicates = [HasFXSR] in { 667 def FXSAVE : I<0xAE, MRM0m, (outs), (ins opaque512mem:$dst), 668 "fxsave\t$dst", [(int_x86_fxsave addr:$dst)], IIC_FXSAVE>, TB; 669 def FXSAVE64 : RI<0xAE, MRM0m, (outs), (ins opaque512mem:$dst), 670 "fxsave64\t$dst", [(int_x86_fxsave64 addr:$dst)], 671 IIC_FXSAVE>, TB, Requires<[In64BitMode]>; 672 def FXRSTOR : I<0xAE, MRM1m, (outs), (ins opaque512mem:$src), 673 "fxrstor\t$src", [(int_x86_fxrstor addr:$src)], IIC_FXRSTOR>, TB; 674 def FXRSTOR64 : RI<0xAE, MRM1m, (outs), (ins opaque512mem:$src), 675 "fxrstor64\t$src", [(int_x86_fxrstor64 addr:$src)], 676 IIC_FXRSTOR>, TB, Requires<[In64BitMode]>; 677 } // Predicates = [FeatureFXSR] 678 } // SchedRW 679 680 //===----------------------------------------------------------------------===// 681 // Non-Instruction Patterns 682 //===----------------------------------------------------------------------===// 683 684 // Required for RET of f32 / f64 / f80 values. 685 def : Pat<(X86fld addr:$src, f32), (LD_Fp32m addr:$src)>; 686 def : Pat<(X86fld addr:$src, f64), (LD_Fp64m addr:$src)>; 687 def : Pat<(X86fld addr:$src, f80), (LD_Fp80m addr:$src)>; 688 689 // Required for CALL which return f32 / f64 / f80 values. 690 def : Pat<(X86fst RFP32:$src, addr:$op, f32), (ST_Fp32m addr:$op, RFP32:$src)>; 691 def : Pat<(X86fst RFP64:$src, addr:$op, f32), (ST_Fp64m32 addr:$op, 692 RFP64:$src)>; 693 def : Pat<(X86fst RFP64:$src, addr:$op, f64), (ST_Fp64m addr:$op, RFP64:$src)>; 694 def : Pat<(X86fst RFP80:$src, addr:$op, f32), (ST_Fp80m32 addr:$op, 695 RFP80:$src)>; 696 def : Pat<(X86fst RFP80:$src, addr:$op, f64), (ST_Fp80m64 addr:$op, 697 RFP80:$src)>; 698 def : Pat<(X86fst RFP80:$src, addr:$op, f80), (ST_FpP80m addr:$op, 699 RFP80:$src)>; 700 701 // Floating point constant -0.0 and -1.0 702 def : Pat<(f32 fpimmneg0), (CHS_Fp32 (LD_Fp032))>, Requires<[FPStackf32]>; 703 def : Pat<(f32 fpimmneg1), (CHS_Fp32 (LD_Fp132))>, Requires<[FPStackf32]>; 704 def : Pat<(f64 fpimmneg0), (CHS_Fp64 (LD_Fp064))>, Requires<[FPStackf64]>; 705 def : Pat<(f64 fpimmneg1), (CHS_Fp64 (LD_Fp164))>, Requires<[FPStackf64]>; 706 def : Pat<(f80 fpimmneg0), (CHS_Fp80 (LD_Fp080))>; 707 def : Pat<(f80 fpimmneg1), (CHS_Fp80 (LD_Fp180))>; 708 709 // Used to conv. i64 to f64 since there isn't a SSE version. 710 def : Pat<(X86fildflag addr:$src, i64), (ILD_Fp64m64 addr:$src)>; 711 712 // FP extensions map onto simple pseudo-value conversions if they are to/from 713 // the FP stack. 714 def : Pat<(f64 (fextend RFP32:$src)), (COPY_TO_REGCLASS RFP32:$src, RFP64)>, 715 Requires<[FPStackf32]>; 716 def : Pat<(f80 (fextend RFP32:$src)), (COPY_TO_REGCLASS RFP32:$src, RFP80)>, 717 Requires<[FPStackf32]>; 718 def : Pat<(f80 (fextend RFP64:$src)), (COPY_TO_REGCLASS RFP64:$src, RFP80)>, 719 Requires<[FPStackf64]>; 720 721 // FP truncations map onto simple pseudo-value conversions if they are to/from 722 // the FP stack. We have validated that only value-preserving truncations make 723 // it through isel. 724 def : Pat<(f32 (fround RFP64:$src)), (COPY_TO_REGCLASS RFP64:$src, RFP32)>, 725 Requires<[FPStackf32]>; 726 def : Pat<(f32 (fround RFP80:$src)), (COPY_TO_REGCLASS RFP80:$src, RFP32)>, 727 Requires<[FPStackf32]>; 728 def : Pat<(f64 (fround RFP80:$src)), (COPY_TO_REGCLASS RFP80:$src, RFP64)>, 729 Requires<[FPStackf64]>; 730
