1 # Instructions that are available for the current ISA but should be rejected by 2 # the assembler (e.g. invalid set of operands or operand's restrictions not met). 3 4 # RUN: not llvm-mc %s -triple=mips64-unknown-linux -mcpu=mips64r6 2>%t1 5 # RUN: FileCheck %s < %t1 6 7 .text 8 local_label: 9 .set noreorder 10 .set noat 11 align $4, $2, $3, -1 # CHECK: :[[@LINE]]:29: error: expected 2-bit unsigned immediate 12 align $4, $2, $3, 4 # CHECK: :[[@LINE]]:29: error: expected 2-bit unsigned immediate 13 jalr.hb $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different 14 jalr.hb $31, $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different 15 ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 16 break -1 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate 17 break 1024 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate 18 break -1, 5 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate 19 break 1024, 5 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate 20 break 7, -1 # CHECK: :[[@LINE]]:18: error: expected 10-bit unsigned immediate 21 break 7, 1024 # CHECK: :[[@LINE]]:18: error: expected 10-bit unsigned immediate 22 break 1024, 1024 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate 23 lh $33, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 24 lhe $34, 8($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 25 lhu $35, 8($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 26 lhue $36, 8($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 27 lh $2, 8($34) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset 28 lhe $4, 8($33) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset 29 lhu $4, 8($35) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset 30 lhue $4, 8($37) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset 31 lh $2, -65536($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset 32 lh $2, 65536($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset 33 lhe $4, -512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset 34 lhe $4, 512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset 35 lhu $4, -65536($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset 36 lhu $4, 65536($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset 37 lhue $4, -512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset 38 lhue $4, 512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset 39 // FIXME: Following tests are temporarily disabled, until "PredicateControl not in hierarchy" problem is resolved 40 bltl $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 41 bltul $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 42 blel $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 43 bleul $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 44 bgel $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 45 bgeul $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 46 bgtl $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 47 bgtul $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 48 beqc $0, $2, local_label # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction 49 bnec $0, $2, local_label # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction 50 bgec $2, $2, local_label # CHECK: :[[@LINE]]:{{[0-9]+}}: error: registers must be different 51 bltc $2, $2, local_label # CHECK: :[[@LINE]]:{{[0-9]+}}: error: registers must be different 52 bgeuc $2, $2, local_label # CHECK: :[[@LINE]]:{{[0-9]+}}: error: registers must be different 53 bltuc $2, $2, local_label # CHECK: :[[@LINE]]:{{[0-9]+}}: error: registers must be different 54 beqc $2, $2, local_label # CHECK: :[[@LINE]]:{{[0-9]+}}: error: registers must be different 55 bnec $2, $2, local_label # CHECK: :[[@LINE]]:{{[0-9]+}}: error: registers must be different 56 blezc $0, local_label # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction 57 bgezc $0, local_label # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction 58 bgtzc $0, local_label # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction 59 bltzc $0, local_label # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction 60 beqzc $0, local_label # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction 61 bnezc $0, local_label # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction 62 cache -1, 255($7) # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate 63 cache 32, 255($7) # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate 64 dalign $4, $2, $3, -1 # CHECK: :[[@LINE]]:29: error: expected 3-bit unsigned immediate 65 dalign $4, $2, $3, 8 # CHECK: :[[@LINE]]:29: error: expected 3-bit unsigned immediate 66 dlsa $2, $3, $4, 0 # CHECK: :[[@LINE]]:29: error: expected immediate in range 1 .. 4 67 dlsa $2, $3, $4, 5 # CHECK: :[[@LINE]]:29: error: expected immediate in range 1 .. 4 68 drotr32 $2, $3, -1 # CHECK: :[[@LINE]]:25: error: expected 5-bit unsigned immediate 69 drotr32 $2, $3, 32 # CHECK: :[[@LINE]]:25: error: expected 5-bit unsigned immediate 70 jalr.hb $31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different 71 jalr.hb $31, $31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different 72 lsa $2, $3, $4, 0 # CHECK: :[[@LINE]]:29: error: expected immediate in range 1 .. 4 73 lsa $2, $3, $4, 5 # CHECK: :[[@LINE]]:29: error: expected immediate in range 1 .. 4 74 pref -1, 255($7) # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate 75 pref 32, 255($7) # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate 76 dmtc0 $4, $3, -1 # CHECK: :[[@LINE]]:24: error: expected 3-bit unsigned immediate 77 dmtc0 $4, $3, 8 # CHECK: :[[@LINE]]:24: error: expected 3-bit unsigned immediate 78 dmfc0 $4, $3, -1 # CHECK: :[[@LINE]]:24: error: expected 3-bit unsigned immediate 79 dmfc0 $4, $3, 8 # CHECK: :[[@LINE]]:24: error: expected 3-bit unsigned immediate 80 ld $2, 65536($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset 81 ld $2, -65536($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset 82 ld $32, 65536($32) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 83 lld $2, -65536($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset 84 lld $2, 65536($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset 85 sd $2, -65536($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset 86 lld $32, 4096($32) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 87 sd $2, 65536($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset 88 sd $32, 65536($32) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 89 dsrl $2, $4, 64 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 6-bit unsigned immediate 90 dsrl $2, $4, -2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 6-bit unsigned immediate 91 dsrl $32, $32, 32 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 92 dsrl32 $2, $4, 32 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 5-bit unsigned immediate 93 dsrl32 $32, $32, 32 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 94 dsrlv $2, $4, 2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 95 dsrlv $32, $32, $32 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 96 lb $32, 8($5) # CHECK: :[[@LINE]]:12: error: invalid operand for instruction 97 lb $4, -32769($5) # CHECK: :[[@LINE]]:16: error: expected memory with 16-bit signed offset 98 lb $4, 32768($5) # CHECK: :[[@LINE]]:16: error: expected memory with 16-bit signed offset 99 lb $4, 8($32) # CHECK: :[[@LINE]]:16: error: expected memory with 16-bit signed offset 100 lbu $32, 8($5) # CHECK: :[[@LINE]]:13: error: invalid operand for instruction 101 lbu $4, -32769($5) # CHECK: :[[@LINE]]:17: error: expected memory with 16-bit signed offset 102 lbu $4, 32768($5) # CHECK: :[[@LINE]]:17: error: expected memory with 16-bit signed offset 103 lbu $4, 8($32) # CHECK: :[[@LINE]]:17: error: expected memory with 16-bit signed offset 104 ldc1 $f32, 300($10) # CHECK: :[[@LINE]]:14: error: invalid operand for instruction 105 ldc1 $f7, -32769($10) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset 106 ldc1 $f7, 32768($10) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset 107 ldc1 $f7, 300($32) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset 108 sdc1 $f32, 64($10) # CHECK: :[[@LINE]]:14: error: invalid operand for instruction 109 sdc1 $f7, -32769($10) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset 110 sdc1 $f7, 32768($10) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset 111 sdc1 $f7, 64($32) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset 112 lwc1 $f32, 32($5) # CHECK: :[[@LINE]]:14: error: invalid operand for instruction 113 lwc1 $f2, -32769($5) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset 114 lwc1 $f2, 32768($5) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset 115 lwc1 $f2, 32($32) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset 116 swc1 $f32, 369($13) # CHECK: :[[@LINE]]:14: error: invalid operand for instruction 117 swc1 $f6, -32769($13) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset 118 swc1 $f6, 32768($13) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset 119 swc1 $f6, 369($32) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset 120 ldc2 $32, 1023($12) # CHECK: :[[@LINE]]:14: error: invalid operand for instruction 121 ldc2 $11, -1025($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 122 ldc2 $11, 1024($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 123 sdc2 $32, 8($16) # CHECK: :[[@LINE]]:14: error: invalid operand for instruction 124 sdc2 $11, -1025($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 125 sdc2 $11, 1024($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 126 lwc2 $32, 16($4) # CHECK: :[[@LINE]]:14: error: invalid operand for instruction 127 lwc2 $11, -1025($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 128 lwc2 $11, 1024($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 129 swc2 $32, 777($17) # CHECK: :[[@LINE]]:14: error: invalid operand for instruction 130 swc2 $11, -1025($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 131 swc2 $11, 1024($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 132
