1 /* 2 * Copyright 2010 Jerome Glisse <glisse (at) freedesktop.org> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 #include "r600_asm.h" 24 #include "r700_sq.h" 25 26 void r700_bytecode_cf_vtx_build(uint32_t *bytecode, const struct r600_bytecode_cf *cf) 27 { 28 unsigned count = (cf->ndw / 4) - 1; 29 *bytecode++ = S_SQ_CF_WORD0_ADDR(cf->addr >> 1); 30 *bytecode++ = S_SQ_CF_WORD1_CF_INST(r600_isa_cf_opcode(ISA_CC_R700, cf->op)) | 31 S_SQ_CF_WORD1_BARRIER(1) | 32 S_SQ_CF_WORD1_COUNT(count) | 33 S_SQ_CF_WORD1_COUNT_3(count >> 3); 34 } 35 36 int r700_bytecode_alu_build(struct r600_bytecode *bc, struct r600_bytecode_alu *alu, unsigned id) 37 { 38 bc->bytecode[id++] = S_SQ_ALU_WORD0_SRC0_SEL(alu->src[0].sel) | 39 S_SQ_ALU_WORD0_SRC0_REL(alu->src[0].rel) | 40 S_SQ_ALU_WORD0_SRC0_CHAN(alu->src[0].chan) | 41 S_SQ_ALU_WORD0_SRC0_NEG(alu->src[0].neg) | 42 S_SQ_ALU_WORD0_SRC1_SEL(alu->src[1].sel) | 43 S_SQ_ALU_WORD0_SRC1_REL(alu->src[1].rel) | 44 S_SQ_ALU_WORD0_SRC1_CHAN(alu->src[1].chan) | 45 S_SQ_ALU_WORD0_SRC1_NEG(alu->src[1].neg) | 46 S_SQ_ALU_WORD0_PRED_SEL(alu->pred_sel) | 47 S_SQ_ALU_WORD0_LAST(alu->last); 48 49 /* don't replace gpr by pv or ps for destination register */ 50 if (alu->is_op3) { 51 assert(!alu->src[0].abs && !alu->src[1].abs && !alu->src[2].abs); 52 bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) | 53 S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) | 54 S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) | 55 S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) | 56 S_SQ_ALU_WORD1_OP3_SRC2_SEL(alu->src[2].sel) | 57 S_SQ_ALU_WORD1_OP3_SRC2_REL(alu->src[2].rel) | 58 S_SQ_ALU_WORD1_OP3_SRC2_CHAN(alu->src[2].chan) | 59 S_SQ_ALU_WORD1_OP3_SRC2_NEG(alu->src[2].neg) | 60 S_SQ_ALU_WORD1_OP3_ALU_INST(r600_isa_alu_opcode(bc->isa->hw_class, alu->op)) | 61 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle); 62 } else { 63 bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) | 64 S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) | 65 S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) | 66 S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) | 67 S_SQ_ALU_WORD1_OP2_SRC0_ABS(alu->src[0].abs) | 68 S_SQ_ALU_WORD1_OP2_SRC1_ABS(alu->src[1].abs) | 69 S_SQ_ALU_WORD1_OP2_WRITE_MASK(alu->dst.write) | 70 S_SQ_ALU_WORD1_OP2_OMOD(alu->omod) | 71 S_SQ_ALU_WORD1_OP2_ALU_INST(r600_isa_alu_opcode(bc->isa->hw_class, alu->op)) | 72 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle) | 73 S_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(alu->execute_mask) | 74 S_SQ_ALU_WORD1_OP2_UPDATE_PRED(alu->update_pred); 75 } 76 return 0; 77 } 78 79 void r700_bytecode_alu_read(struct r600_bytecode *bc, 80 struct r600_bytecode_alu *alu, uint32_t word0, uint32_t word1) 81 { 82 /* WORD0 */ 83 alu->src[0].sel = G_SQ_ALU_WORD0_SRC0_SEL(word0); 84 alu->src[0].rel = G_SQ_ALU_WORD0_SRC0_REL(word0); 85 alu->src[0].chan = G_SQ_ALU_WORD0_SRC0_CHAN(word0); 86 alu->src[0].neg = G_SQ_ALU_WORD0_SRC0_NEG(word0); 87 alu->src[1].sel = G_SQ_ALU_WORD0_SRC1_SEL(word0); 88 alu->src[1].rel = G_SQ_ALU_WORD0_SRC1_REL(word0); 89 alu->src[1].chan = G_SQ_ALU_WORD0_SRC1_CHAN(word0); 90 alu->src[1].neg = G_SQ_ALU_WORD0_SRC1_NEG(word0); 91 alu->index_mode = G_SQ_ALU_WORD0_INDEX_MODE(word0); 92 alu->pred_sel = G_SQ_ALU_WORD0_PRED_SEL(word0); 93 alu->last = G_SQ_ALU_WORD0_LAST(word0); 94 95 /* WORD1 */ 96 alu->bank_swizzle = G_SQ_ALU_WORD1_BANK_SWIZZLE(word1); 97 if (alu->bank_swizzle) 98 alu->bank_swizzle_force = alu->bank_swizzle; 99 alu->dst.sel = G_SQ_ALU_WORD1_DST_GPR(word1); 100 alu->dst.rel = G_SQ_ALU_WORD1_DST_REL(word1); 101 alu->dst.chan = G_SQ_ALU_WORD1_DST_CHAN(word1); 102 alu->dst.clamp = G_SQ_ALU_WORD1_CLAMP(word1); 103 if (G_SQ_ALU_WORD1_ENCODING(word1)) /*ALU_DWORD1_OP3*/ 104 { 105 alu->is_op3 = 1; 106 alu->src[2].sel = G_SQ_ALU_WORD1_OP3_SRC2_SEL(word1); 107 alu->src[2].rel = G_SQ_ALU_WORD1_OP3_SRC2_REL(word1); 108 alu->src[2].chan = G_SQ_ALU_WORD1_OP3_SRC2_CHAN(word1); 109 alu->src[2].neg = G_SQ_ALU_WORD1_OP3_SRC2_NEG(word1); 110 alu->op = r600_isa_alu_by_opcode(bc->isa, 111 G_SQ_ALU_WORD1_OP3_ALU_INST(word1), 1); 112 } 113 else /*ALU_DWORD1_OP2*/ 114 { 115 alu->src[0].abs = G_SQ_ALU_WORD1_OP2_SRC0_ABS(word1); 116 alu->src[1].abs = G_SQ_ALU_WORD1_OP2_SRC1_ABS(word1); 117 alu->op = r600_isa_alu_by_opcode(bc->isa, 118 G_SQ_ALU_WORD1_OP2_ALU_INST(word1), 0); 119 alu->omod = G_SQ_ALU_WORD1_OP2_OMOD(word1); 120 alu->dst.write = G_SQ_ALU_WORD1_OP2_WRITE_MASK(word1); 121 alu->update_pred = G_SQ_ALU_WORD1_OP2_UPDATE_PRED(word1); 122 alu->execute_mask = 123 G_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(word1); 124 } 125 } 126
