1 /* 2 * Copyright 2011 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24 #include <stdbool.h> 25 #include "brw_context.h" 26 #include "brw_state.h" 27 #include "brw_defines.h" 28 #include "brw_util.h" 29 #include "brw_wm.h" 30 #include "program/program.h" 31 #include "program/prog_parameter.h" 32 #include "program/prog_statevars.h" 33 #include "main/framebuffer.h" 34 #include "intel_batchbuffer.h" 35 36 static void 37 upload_wm_state(struct brw_context *brw) 38 { 39 struct gl_context *ctx = &brw->ctx; 40 /* BRW_NEW_FS_PROG_DATA */ 41 const struct brw_wm_prog_data *prog_data = 42 brw_wm_prog_data(brw->wm.base.prog_data); 43 bool writes_depth = prog_data->computed_depth_mode != BRW_PSCDEPTH_OFF; 44 uint32_t dw1, dw2; 45 46 /* _NEW_BUFFERS */ 47 const bool multisampled_fbo = _mesa_geometric_samples(ctx->DrawBuffer) > 1; 48 49 dw1 = dw2 = 0; 50 dw1 |= GEN7_WM_STATISTICS_ENABLE; 51 dw1 |= GEN7_WM_LINE_AA_WIDTH_1_0; 52 dw1 |= GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5; 53 54 /* _NEW_LINE */ 55 if (ctx->Line.StippleFlag) 56 dw1 |= GEN7_WM_LINE_STIPPLE_ENABLE; 57 58 /* _NEW_POLYGON */ 59 if (ctx->Polygon.StippleFlag) 60 dw1 |= GEN7_WM_POLYGON_STIPPLE_ENABLE; 61 62 if (prog_data->uses_src_depth) 63 dw1 |= GEN7_WM_USES_SOURCE_DEPTH; 64 65 if (prog_data->uses_src_w) 66 dw1 |= GEN7_WM_USES_SOURCE_W; 67 68 dw1 |= prog_data->computed_depth_mode << GEN7_WM_COMPUTED_DEPTH_MODE_SHIFT; 69 dw1 |= prog_data->barycentric_interp_modes << 70 GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT; 71 72 /* _NEW_COLOR, _NEW_MULTISAMPLE _NEW_BUFFERS */ 73 /* Enable if the pixel shader kernel generates and outputs oMask. 74 */ 75 if (prog_data->uses_kill || 76 _mesa_is_alpha_test_enabled(ctx) || 77 _mesa_is_alpha_to_coverage_enabled(ctx) || 78 prog_data->uses_omask) { 79 dw1 |= GEN7_WM_KILL_ENABLE; 80 } 81 82 /* _NEW_BUFFERS | _NEW_COLOR */ 83 if (brw_color_buffer_write_enabled(brw) || writes_depth || 84 prog_data->has_side_effects || dw1 & GEN7_WM_KILL_ENABLE) { 85 dw1 |= GEN7_WM_DISPATCH_ENABLE; 86 } 87 if (multisampled_fbo) { 88 /* _NEW_MULTISAMPLE */ 89 if (ctx->Multisample.Enabled) 90 dw1 |= GEN7_WM_MSRAST_ON_PATTERN; 91 else 92 dw1 |= GEN7_WM_MSRAST_OFF_PIXEL; 93 94 if (prog_data->persample_dispatch) 95 dw2 |= GEN7_WM_MSDISPMODE_PERSAMPLE; 96 else 97 dw2 |= GEN7_WM_MSDISPMODE_PERPIXEL; 98 } else { 99 dw1 |= GEN7_WM_MSRAST_OFF_PIXEL; 100 dw2 |= GEN7_WM_MSDISPMODE_PERSAMPLE; 101 } 102 103 if (prog_data->uses_sample_mask) { 104 dw1 |= GEN7_WM_USES_INPUT_COVERAGE_MASK; 105 } 106 107 /* BRW_NEW_FS_PROG_DATA */ 108 if (prog_data->early_fragment_tests) 109 dw1 |= GEN7_WM_EARLY_DS_CONTROL_PREPS; 110 else if (prog_data->has_side_effects) 111 dw1 |= GEN7_WM_EARLY_DS_CONTROL_PSEXEC; 112 113 /* The "UAV access enable" bits are unnecessary on HSW because they only 114 * seem to have an effect on the HW-assisted coherency mechanism which we 115 * don't need, and the rasterization-related UAV_ONLY flag and the 116 * DISPATCH_ENABLE bit can be set independently from it. 117 * C.f. gen8_upload_ps_extra(). 118 * 119 * BRW_NEW_FRAGMENT_PROGRAM | BRW_NEW_FS_PROG_DATA | _NEW_BUFFERS | _NEW_COLOR 120 */ 121 if (brw->is_haswell && 122 !(brw_color_buffer_write_enabled(brw) || writes_depth) && 123 prog_data->has_side_effects) 124 dw2 |= HSW_WM_UAV_ONLY; 125 126 BEGIN_BATCH(3); 127 OUT_BATCH(_3DSTATE_WM << 16 | (3 - 2)); 128 OUT_BATCH(dw1); 129 OUT_BATCH(dw2); 130 ADVANCE_BATCH(); 131 } 132 133 const struct brw_tracked_state gen7_wm_state = { 134 .dirty = { 135 .mesa = _NEW_BUFFERS | 136 _NEW_COLOR | 137 _NEW_LINE | 138 _NEW_MULTISAMPLE | 139 _NEW_POLYGON, 140 .brw = BRW_NEW_BATCH | 141 BRW_NEW_BLORP | 142 BRW_NEW_FS_PROG_DATA, 143 }, 144 .emit = upload_wm_state, 145 }; 146 147 static void 148 gen7_upload_ps_state(struct brw_context *brw, 149 const struct brw_stage_state *stage_state, 150 const struct brw_wm_prog_data *prog_data, 151 bool enable_dual_src_blend, unsigned sample_mask, 152 unsigned fast_clear_op) 153 { 154 const struct gen_device_info *devinfo = &brw->screen->devinfo; 155 uint32_t dw2, dw4, dw5, ksp0, ksp2; 156 const int max_threads_shift = brw->is_haswell ? 157 HSW_PS_MAX_THREADS_SHIFT : IVB_PS_MAX_THREADS_SHIFT; 158 159 dw2 = dw4 = dw5 = ksp2 = 0; 160 161 const unsigned sampler_count = 162 DIV_ROUND_UP(CLAMP(stage_state->sampler_count, 0, 16), 4); 163 dw2 |= SET_FIELD(sampler_count, GEN7_PS_SAMPLER_COUNT); 164 165 dw2 |= ((prog_data->base.binding_table.size_bytes / 4) << 166 GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT); 167 168 if (prog_data->base.use_alt_mode) 169 dw2 |= GEN7_PS_FLOATING_POINT_MODE_ALT; 170 171 /* Haswell requires the sample mask to be set in this packet as well as 172 * in 3DSTATE_SAMPLE_MASK; the values should match. */ 173 /* _NEW_BUFFERS, _NEW_MULTISAMPLE */ 174 if (brw->is_haswell) 175 dw4 |= SET_FIELD(sample_mask, HSW_PS_SAMPLE_MASK); 176 177 dw4 |= (devinfo->max_wm_threads - 1) << max_threads_shift; 178 179 if (prog_data->base.nr_params > 0) 180 dw4 |= GEN7_PS_PUSH_CONSTANT_ENABLE; 181 182 /* From the IVB PRM, volume 2 part 1, page 287: 183 * "This bit is inserted in the PS payload header and made available to 184 * the DataPort (either via the message header or via header bypass) to 185 * indicate that oMask data (one or two phases) is included in Render 186 * Target Write messages. If present, the oMask data is used to mask off 187 * samples." 188 */ 189 if (prog_data->uses_omask) 190 dw4 |= GEN7_PS_OMASK_TO_RENDER_TARGET; 191 192 /* From the IVB PRM, volume 2 part 1, page 287: 193 * "If the PS kernel does not need the Position XY Offsets to 194 * compute a Position Value, then this field should be programmed 195 * to POSOFFSET_NONE." 196 * "SW Recommendation: If the PS kernel needs the Position Offsets 197 * to compute a Position XY value, this field should match Position 198 * ZW Interpolation Mode to ensure a consistent position.xyzw 199 * computation." 200 * We only require XY sample offsets. So, this recommendation doesn't 201 * look useful at the moment. We might need this in future. 202 */ 203 if (prog_data->uses_pos_offset) 204 dw4 |= GEN7_PS_POSOFFSET_SAMPLE; 205 else 206 dw4 |= GEN7_PS_POSOFFSET_NONE; 207 208 /* The hardware wedges if you have this bit set but don't turn on any dual 209 * source blend factors. 210 */ 211 if (enable_dual_src_blend) 212 dw4 |= GEN7_PS_DUAL_SOURCE_BLEND_ENABLE; 213 214 /* BRW_NEW_FS_PROG_DATA */ 215 if (prog_data->num_varying_inputs != 0) 216 dw4 |= GEN7_PS_ATTRIBUTE_ENABLE; 217 218 dw4 |= fast_clear_op; 219 220 if (prog_data->dispatch_16) 221 dw4 |= GEN7_PS_16_DISPATCH_ENABLE; 222 223 if (prog_data->dispatch_8) 224 dw4 |= GEN7_PS_8_DISPATCH_ENABLE; 225 226 dw5 |= prog_data->base.dispatch_grf_start_reg << 227 GEN7_PS_DISPATCH_START_GRF_SHIFT_0; 228 dw5 |= prog_data->dispatch_grf_start_reg_2 << 229 GEN7_PS_DISPATCH_START_GRF_SHIFT_2; 230 231 ksp0 = stage_state->prog_offset; 232 ksp2 = stage_state->prog_offset + prog_data->prog_offset_2; 233 234 BEGIN_BATCH(8); 235 OUT_BATCH(_3DSTATE_PS << 16 | (8 - 2)); 236 OUT_BATCH(ksp0); 237 OUT_BATCH(dw2); 238 if (prog_data->base.total_scratch) { 239 OUT_RELOC(brw->wm.base.scratch_bo, 240 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 241 ffs(stage_state->per_thread_scratch) - 11); 242 } else { 243 OUT_BATCH(0); 244 } 245 OUT_BATCH(dw4); 246 OUT_BATCH(dw5); 247 OUT_BATCH(0); /* kernel 1 pointer */ 248 OUT_BATCH(ksp2); 249 ADVANCE_BATCH(); 250 } 251 252 static void 253 upload_ps_state(struct brw_context *brw) 254 { 255 /* BRW_NEW_FS_PROG_DATA */ 256 const struct brw_wm_prog_data *prog_data = 257 brw_wm_prog_data(brw->wm.base.prog_data); 258 const struct gl_context *ctx = &brw->ctx; 259 /* BRW_NEW_FS_PROG_DATA | _NEW_COLOR */ 260 const bool enable_dual_src_blend = prog_data->dual_src_blend && 261 (ctx->Color.BlendEnabled & 1) && 262 ctx->Color.Blend[0]._UsesDualSrc; 263 /* _NEW_BUFFERS, _NEW_MULTISAMPLE */ 264 const unsigned sample_mask = 265 brw->is_haswell ? gen6_determine_sample_mask(brw) : 0; 266 267 gen7_upload_ps_state(brw, &brw->wm.base, prog_data, 268 enable_dual_src_blend, sample_mask, 269 brw->wm.fast_clear_op); 270 } 271 272 const struct brw_tracked_state gen7_ps_state = { 273 .dirty = { 274 .mesa = _NEW_BUFFERS | 275 _NEW_COLOR | 276 _NEW_MULTISAMPLE, 277 .brw = BRW_NEW_BATCH | 278 BRW_NEW_BLORP | 279 BRW_NEW_FS_PROG_DATA, 280 }, 281 .emit = upload_ps_state, 282 }; 283
