1 /* 2 * Copyright 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24 #include <stdbool.h> 25 #include "program/program.h" 26 #include "brw_state.h" 27 #include "brw_defines.h" 28 #include "brw_wm.h" 29 #include "intel_batchbuffer.h" 30 31 void 32 gen8_upload_ps_extra(struct brw_context *brw, 33 const struct brw_wm_prog_data *prog_data) 34 { 35 struct gl_context *ctx = &brw->ctx; 36 uint32_t dw1 = 0; 37 38 dw1 |= GEN8_PSX_PIXEL_SHADER_VALID; 39 dw1 |= prog_data->computed_depth_mode << GEN8_PSX_COMPUTED_DEPTH_MODE_SHIFT; 40 41 if (prog_data->uses_kill) 42 dw1 |= GEN8_PSX_KILL_ENABLE; 43 44 if (prog_data->num_varying_inputs != 0) 45 dw1 |= GEN8_PSX_ATTRIBUTE_ENABLE; 46 47 if (prog_data->uses_src_depth) 48 dw1 |= GEN8_PSX_USES_SOURCE_DEPTH; 49 50 if (prog_data->uses_src_w) 51 dw1 |= GEN8_PSX_USES_SOURCE_W; 52 53 if (prog_data->persample_dispatch) 54 dw1 |= GEN8_PSX_SHADER_IS_PER_SAMPLE; 55 56 /* _NEW_MULTISAMPLE | BRW_NEW_CONSERVATIVE_RASTERIZATION */ 57 if (prog_data->uses_sample_mask) { 58 if (brw->gen >= 9) { 59 if (prog_data->post_depth_coverage) 60 dw1 |= BRW_PCICMS_DEPTH << GEN9_PSX_SHADER_NORMAL_COVERAGE_MASK_SHIFT; 61 else if (prog_data->inner_coverage && ctx->IntelConservativeRasterization) 62 dw1 |= BRW_PSICMS_INNER << GEN9_PSX_SHADER_NORMAL_COVERAGE_MASK_SHIFT; 63 else 64 dw1 |= BRW_PSICMS_NORMAL << GEN9_PSX_SHADER_NORMAL_COVERAGE_MASK_SHIFT; 65 } 66 else { 67 dw1 |= GEN8_PSX_SHADER_USES_INPUT_COVERAGE_MASK; 68 } 69 } 70 71 if (prog_data->uses_omask) 72 dw1 |= GEN8_PSX_OMASK_TO_RENDER_TARGET; 73 74 if (brw->gen >= 9 && prog_data->pulls_bary) 75 dw1 |= GEN9_PSX_SHADER_PULLS_BARY; 76 77 /* The stricter cross-primitive coherency guarantees that the hardware 78 * gives us with the "Accesses UAV" bit set for at least one shader stage 79 * and the "UAV coherency required" bit set on the 3DPRIMITIVE command are 80 * redundant within the current image, atomic counter and SSBO GL APIs, 81 * which all have very loose ordering and coherency requirements and 82 * generally rely on the application to insert explicit barriers when a 83 * shader invocation is expected to see the memory writes performed by the 84 * invocations of some previous primitive. Regardless of the value of "UAV 85 * coherency required", the "Accesses UAV" bits will implicitly cause an in 86 * most cases useless DC flush when the lowermost stage with the bit set 87 * finishes execution. 88 * 89 * It would be nice to disable it, but in some cases we can't because on 90 * Gen8+ it also has an influence on rasterization via the PS UAV-only 91 * signal (which could be set independently from the coherency mechanism in 92 * the 3DSTATE_WM command on Gen7), and because in some cases it will 93 * determine whether the hardware skips execution of the fragment shader or 94 * not via the ThreadDispatchEnable signal. However if we know that 95 * GEN8_PS_BLEND_HAS_WRITEABLE_RT is going to be set and 96 * GEN8_PSX_PIXEL_SHADER_NO_RT_WRITE is not set it shouldn't make any 97 * difference so we may just disable it here. 98 * 99 * Gen8 hardware tries to compute ThreadDispatchEnable for us but doesn't 100 * take into account KillPixels when no depth or stencil writes are enabled. 101 * In order for occlusion queries to work correctly with no attachments, we 102 * need to force-enable here. 103 * 104 * BRW_NEW_FS_PROG_DATA | BRW_NEW_FRAGMENT_PROGRAM | _NEW_BUFFERS | _NEW_COLOR 105 */ 106 if ((prog_data->has_side_effects || prog_data->uses_kill) && 107 !brw_color_buffer_write_enabled(brw)) 108 dw1 |= GEN8_PSX_SHADER_HAS_UAV; 109 110 if (prog_data->computed_stencil) { 111 assert(brw->gen >= 9); 112 dw1 |= GEN9_PSX_SHADER_COMPUTES_STENCIL; 113 } 114 115 BEGIN_BATCH(2); 116 OUT_BATCH(_3DSTATE_PS_EXTRA << 16 | (2 - 2)); 117 OUT_BATCH(dw1); 118 ADVANCE_BATCH(); 119 } 120 121 static void 122 upload_ps_extra(struct brw_context *brw) 123 { 124 /* BRW_NEW_FS_PROG_DATA */ 125 gen8_upload_ps_extra(brw, brw_wm_prog_data(brw->wm.base.prog_data)); 126 } 127 128 const struct brw_tracked_state gen8_ps_extra = { 129 .dirty = { 130 .mesa = _NEW_BUFFERS | _NEW_COLOR, 131 .brw = BRW_NEW_BLORP | 132 BRW_NEW_CONTEXT | 133 BRW_NEW_FRAGMENT_PROGRAM | 134 BRW_NEW_FS_PROG_DATA | 135 BRW_NEW_CONSERVATIVE_RASTERIZATION, 136 }, 137 .emit = upload_ps_extra, 138 }; 139 140 static void 141 upload_wm_state(struct brw_context *brw) 142 { 143 struct gl_context *ctx = &brw->ctx; 144 uint32_t dw1 = 0; 145 146 /* BRW_NEW_FS_PROG_DATA */ 147 const struct brw_wm_prog_data *wm_prog_data = 148 brw_wm_prog_data(brw->wm.base.prog_data); 149 150 dw1 |= GEN7_WM_STATISTICS_ENABLE; 151 dw1 |= GEN7_WM_LINE_AA_WIDTH_1_0; 152 dw1 |= GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5; 153 dw1 |= GEN7_WM_POINT_RASTRULE_UPPER_RIGHT; 154 155 /* _NEW_LINE */ 156 if (ctx->Line.StippleFlag) 157 dw1 |= GEN7_WM_LINE_STIPPLE_ENABLE; 158 159 /* _NEW_POLYGON */ 160 if (ctx->Polygon.StippleFlag) 161 dw1 |= GEN7_WM_POLYGON_STIPPLE_ENABLE; 162 163 dw1 |= wm_prog_data->barycentric_interp_modes << 164 GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT; 165 166 /* BRW_NEW_FS_PROG_DATA */ 167 if (wm_prog_data->early_fragment_tests) 168 dw1 |= GEN7_WM_EARLY_DS_CONTROL_PREPS; 169 else if (wm_prog_data->has_side_effects) 170 dw1 |= GEN7_WM_EARLY_DS_CONTROL_PSEXEC; 171 172 BEGIN_BATCH(2); 173 OUT_BATCH(_3DSTATE_WM << 16 | (2 - 2)); 174 OUT_BATCH(dw1); 175 ADVANCE_BATCH(); 176 } 177 178 const struct brw_tracked_state gen8_wm_state = { 179 .dirty = { 180 .mesa = _NEW_LINE | 181 _NEW_POLYGON, 182 .brw = BRW_NEW_BLORP | 183 BRW_NEW_CONTEXT | 184 BRW_NEW_FS_PROG_DATA, 185 }, 186 .emit = upload_wm_state, 187 }; 188 189 void 190 gen8_upload_ps_state(struct brw_context *brw, 191 const struct brw_stage_state *stage_state, 192 const struct brw_wm_prog_data *prog_data, 193 uint32_t fast_clear_op) 194 { 195 uint32_t dw3 = 0, dw6 = 0, dw7 = 0, ksp0, ksp2 = 0; 196 197 /* Initialize the execution mask with VMask. Otherwise, derivatives are 198 * incorrect for subspans where some of the pixels are unlit. We believe 199 * the bit just didn't take effect in previous generations. 200 */ 201 dw3 |= GEN7_PS_VECTOR_MASK_ENABLE; 202 203 const unsigned sampler_count = 204 DIV_ROUND_UP(CLAMP(stage_state->sampler_count, 0, 16), 4); 205 dw3 |= SET_FIELD(sampler_count, GEN7_PS_SAMPLER_COUNT); 206 207 /* BRW_NEW_FS_PROG_DATA */ 208 dw3 |= 209 ((prog_data->base.binding_table.size_bytes / 4) << 210 GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT); 211 212 if (prog_data->base.use_alt_mode) 213 dw3 |= GEN7_PS_FLOATING_POINT_MODE_ALT; 214 215 /* 3DSTATE_PS expects the number of threads per PSD, which is always 64; 216 * it implicitly scales for different GT levels (which have some # of PSDs). 217 * 218 * In Gen8 the format is U8-2 whereas in Gen9 it is U8-1. 219 */ 220 if (brw->gen >= 9) 221 dw6 |= (64 - 1) << HSW_PS_MAX_THREADS_SHIFT; 222 else 223 dw6 |= (64 - 2) << HSW_PS_MAX_THREADS_SHIFT; 224 225 if (prog_data->base.nr_params > 0) 226 dw6 |= GEN7_PS_PUSH_CONSTANT_ENABLE; 227 228 /* From the documentation for this packet: 229 * "If the PS kernel does not need the Position XY Offsets to 230 * compute a Position Value, then this field should be programmed 231 * to POSOFFSET_NONE." 232 * 233 * "SW Recommendation: If the PS kernel needs the Position Offsets 234 * to compute a Position XY value, this field should match Position 235 * ZW Interpolation Mode to ensure a consistent position.xyzw 236 * computation." 237 * 238 * We only require XY sample offsets. So, this recommendation doesn't 239 * look useful at the moment. We might need this in future. 240 */ 241 if (prog_data->uses_pos_offset) 242 dw6 |= GEN7_PS_POSOFFSET_SAMPLE; 243 else 244 dw6 |= GEN7_PS_POSOFFSET_NONE; 245 246 dw6 |= fast_clear_op; 247 248 if (prog_data->dispatch_8) 249 dw6 |= GEN7_PS_8_DISPATCH_ENABLE; 250 251 if (prog_data->dispatch_16) 252 dw6 |= GEN7_PS_16_DISPATCH_ENABLE; 253 254 dw7 |= prog_data->base.dispatch_grf_start_reg << 255 GEN7_PS_DISPATCH_START_GRF_SHIFT_0; 256 dw7 |= prog_data->dispatch_grf_start_reg_2 << 257 GEN7_PS_DISPATCH_START_GRF_SHIFT_2; 258 259 ksp0 = stage_state->prog_offset; 260 ksp2 = stage_state->prog_offset + prog_data->prog_offset_2; 261 262 BEGIN_BATCH(12); 263 OUT_BATCH(_3DSTATE_PS << 16 | (12 - 2)); 264 OUT_BATCH(ksp0); 265 OUT_BATCH(0); 266 OUT_BATCH(dw3); 267 if (prog_data->base.total_scratch) { 268 OUT_RELOC64(stage_state->scratch_bo, 269 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 270 ffs(stage_state->per_thread_scratch) - 11); 271 } else { 272 OUT_BATCH(0); 273 OUT_BATCH(0); 274 } 275 OUT_BATCH(dw6); 276 OUT_BATCH(dw7); 277 OUT_BATCH(0); /* kernel 1 pointer */ 278 OUT_BATCH(0); 279 OUT_BATCH(ksp2); 280 OUT_BATCH(0); 281 ADVANCE_BATCH(); 282 } 283 284 static void 285 upload_ps_state(struct brw_context *brw) 286 { 287 /* BRW_NEW_FS_PROG_DATA */ 288 const struct brw_wm_prog_data *prog_data = 289 brw_wm_prog_data(brw->wm.base.prog_data); 290 gen8_upload_ps_state(brw, &brw->wm.base, prog_data, brw->wm.fast_clear_op); 291 } 292 293 const struct brw_tracked_state gen8_ps_state = { 294 .dirty = { 295 .mesa = _NEW_MULTISAMPLE, 296 .brw = BRW_NEW_BATCH | 297 BRW_NEW_BLORP | 298 BRW_NEW_FS_PROG_DATA, 299 }, 300 .emit = upload_ps_state, 301 }; 302
