1 //===-- X86AsmBackend.cpp - X86 Assembler Backend -------------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "llvm/MC/MCAsmBackend.h" 11 #include "MCTargetDesc/X86BaseInfo.h" 12 #include "MCTargetDesc/X86FixupKinds.h" 13 #include "llvm/ADT/Twine.h" 14 #include "llvm/MC/MCAssembler.h" 15 #include "llvm/MC/MCELFObjectWriter.h" 16 #include "llvm/MC/MCExpr.h" 17 #include "llvm/MC/MCFixupKindInfo.h" 18 #include "llvm/MC/MCMachObjectWriter.h" 19 #include "llvm/MC/MCObjectWriter.h" 20 #include "llvm/MC/MCSectionCOFF.h" 21 #include "llvm/MC/MCSectionELF.h" 22 #include "llvm/MC/MCSectionMachO.h" 23 #include "llvm/Object/MachOFormat.h" 24 #include "llvm/Support/CommandLine.h" 25 #include "llvm/Support/ELF.h" 26 #include "llvm/Support/ErrorHandling.h" 27 #include "llvm/Support/TargetRegistry.h" 28 #include "llvm/Support/raw_ostream.h" 29 using namespace llvm; 30 31 // Option to allow disabling arithmetic relaxation to workaround PR9807, which 32 // is useful when running bitwise comparison experiments on Darwin. We should be 33 // able to remove this once PR9807 is resolved. 34 static cl::opt<bool> 35 MCDisableArithRelaxation("mc-x86-disable-arith-relaxation", 36 cl::desc("Disable relaxation of arithmetic instruction for X86")); 37 38 static unsigned getFixupKindLog2Size(unsigned Kind) { 39 switch (Kind) { 40 default: assert(0 && "invalid fixup kind!"); 41 case FK_PCRel_1: 42 case FK_Data_1: return 0; 43 case FK_PCRel_2: 44 case FK_Data_2: return 1; 45 case FK_PCRel_4: 46 case X86::reloc_riprel_4byte: 47 case X86::reloc_riprel_4byte_movq_load: 48 case X86::reloc_signed_4byte: 49 case X86::reloc_global_offset_table: 50 case FK_Data_4: return 2; 51 case FK_PCRel_8: 52 case FK_Data_8: return 3; 53 } 54 } 55 56 namespace { 57 58 class X86ELFObjectWriter : public MCELFObjectTargetWriter { 59 public: 60 X86ELFObjectWriter(bool is64Bit, Triple::OSType OSType, uint16_t EMachine, 61 bool HasRelocationAddend) 62 : MCELFObjectTargetWriter(is64Bit, OSType, EMachine, HasRelocationAddend) {} 63 }; 64 65 class X86AsmBackend : public MCAsmBackend { 66 public: 67 X86AsmBackend(const Target &T) 68 : MCAsmBackend() {} 69 70 unsigned getNumFixupKinds() const { 71 return X86::NumTargetFixupKinds; 72 } 73 74 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const { 75 const static MCFixupKindInfo Infos[X86::NumTargetFixupKinds] = { 76 { "reloc_riprel_4byte", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel }, 77 { "reloc_riprel_4byte_movq_load", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel}, 78 { "reloc_signed_4byte", 0, 4 * 8, 0}, 79 { "reloc_global_offset_table", 0, 4 * 8, 0} 80 }; 81 82 if (Kind < FirstTargetFixupKind) 83 return MCAsmBackend::getFixupKindInfo(Kind); 84 85 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() && 86 "Invalid kind!"); 87 return Infos[Kind - FirstTargetFixupKind]; 88 } 89 90 void ApplyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize, 91 uint64_t Value) const { 92 unsigned Size = 1 << getFixupKindLog2Size(Fixup.getKind()); 93 94 assert(Fixup.getOffset() + Size <= DataSize && 95 "Invalid fixup offset!"); 96 97 // Check that uppper bits are either all zeros or all ones. 98 // Specifically ignore overflow/underflow as long as the leakage is 99 // limited to the lower bits. This is to remain compatible with 100 // other assemblers. 101 assert(isIntN(Size * 8 + 1, Value) && 102 "Value does not fit in the Fixup field"); 103 104 for (unsigned i = 0; i != Size; ++i) 105 Data[Fixup.getOffset() + i] = uint8_t(Value >> (i * 8)); 106 } 107 108 bool MayNeedRelaxation(const MCInst &Inst) const; 109 110 void RelaxInstruction(const MCInst &Inst, MCInst &Res) const; 111 112 bool WriteNopData(uint64_t Count, MCObjectWriter *OW) const; 113 }; 114 } // end anonymous namespace 115 116 static unsigned getRelaxedOpcodeBranch(unsigned Op) { 117 switch (Op) { 118 default: 119 return Op; 120 121 case X86::JAE_1: return X86::JAE_4; 122 case X86::JA_1: return X86::JA_4; 123 case X86::JBE_1: return X86::JBE_4; 124 case X86::JB_1: return X86::JB_4; 125 case X86::JE_1: return X86::JE_4; 126 case X86::JGE_1: return X86::JGE_4; 127 case X86::JG_1: return X86::JG_4; 128 case X86::JLE_1: return X86::JLE_4; 129 case X86::JL_1: return X86::JL_4; 130 case X86::JMP_1: return X86::JMP_4; 131 case X86::JNE_1: return X86::JNE_4; 132 case X86::JNO_1: return X86::JNO_4; 133 case X86::JNP_1: return X86::JNP_4; 134 case X86::JNS_1: return X86::JNS_4; 135 case X86::JO_1: return X86::JO_4; 136 case X86::JP_1: return X86::JP_4; 137 case X86::JS_1: return X86::JS_4; 138 } 139 } 140 141 static unsigned getRelaxedOpcodeArith(unsigned Op) { 142 switch (Op) { 143 default: 144 return Op; 145 146 // IMUL 147 case X86::IMUL16rri8: return X86::IMUL16rri; 148 case X86::IMUL16rmi8: return X86::IMUL16rmi; 149 case X86::IMUL32rri8: return X86::IMUL32rri; 150 case X86::IMUL32rmi8: return X86::IMUL32rmi; 151 case X86::IMUL64rri8: return X86::IMUL64rri32; 152 case X86::IMUL64rmi8: return X86::IMUL64rmi32; 153 154 // AND 155 case X86::AND16ri8: return X86::AND16ri; 156 case X86::AND16mi8: return X86::AND16mi; 157 case X86::AND32ri8: return X86::AND32ri; 158 case X86::AND32mi8: return X86::AND32mi; 159 case X86::AND64ri8: return X86::AND64ri32; 160 case X86::AND64mi8: return X86::AND64mi32; 161 162 // OR 163 case X86::OR16ri8: return X86::OR16ri; 164 case X86::OR16mi8: return X86::OR16mi; 165 case X86::OR32ri8: return X86::OR32ri; 166 case X86::OR32mi8: return X86::OR32mi; 167 case X86::OR64ri8: return X86::OR64ri32; 168 case X86::OR64mi8: return X86::OR64mi32; 169 170 // XOR 171 case X86::XOR16ri8: return X86::XOR16ri; 172 case X86::XOR16mi8: return X86::XOR16mi; 173 case X86::XOR32ri8: return X86::XOR32ri; 174 case X86::XOR32mi8: return X86::XOR32mi; 175 case X86::XOR64ri8: return X86::XOR64ri32; 176 case X86::XOR64mi8: return X86::XOR64mi32; 177 178 // ADD 179 case X86::ADD16ri8: return X86::ADD16ri; 180 case X86::ADD16mi8: return X86::ADD16mi; 181 case X86::ADD32ri8: return X86::ADD32ri; 182 case X86::ADD32mi8: return X86::ADD32mi; 183 case X86::ADD64ri8: return X86::ADD64ri32; 184 case X86::ADD64mi8: return X86::ADD64mi32; 185 186 // SUB 187 case X86::SUB16ri8: return X86::SUB16ri; 188 case X86::SUB16mi8: return X86::SUB16mi; 189 case X86::SUB32ri8: return X86::SUB32ri; 190 case X86::SUB32mi8: return X86::SUB32mi; 191 case X86::SUB64ri8: return X86::SUB64ri32; 192 case X86::SUB64mi8: return X86::SUB64mi32; 193 194 // CMP 195 case X86::CMP16ri8: return X86::CMP16ri; 196 case X86::CMP16mi8: return X86::CMP16mi; 197 case X86::CMP32ri8: return X86::CMP32ri; 198 case X86::CMP32mi8: return X86::CMP32mi; 199 case X86::CMP64ri8: return X86::CMP64ri32; 200 case X86::CMP64mi8: return X86::CMP64mi32; 201 202 // PUSH 203 case X86::PUSHi8: return X86::PUSHi32; 204 case X86::PUSHi16: return X86::PUSHi32; 205 case X86::PUSH64i8: return X86::PUSH64i32; 206 case X86::PUSH64i16: return X86::PUSH64i32; 207 } 208 } 209 210 static unsigned getRelaxedOpcode(unsigned Op) { 211 unsigned R = getRelaxedOpcodeArith(Op); 212 if (R != Op) 213 return R; 214 return getRelaxedOpcodeBranch(Op); 215 } 216 217 bool X86AsmBackend::MayNeedRelaxation(const MCInst &Inst) const { 218 // Branches can always be relaxed. 219 if (getRelaxedOpcodeBranch(Inst.getOpcode()) != Inst.getOpcode()) 220 return true; 221 222 if (MCDisableArithRelaxation) 223 return false; 224 225 // Check if this instruction is ever relaxable. 226 if (getRelaxedOpcodeArith(Inst.getOpcode()) == Inst.getOpcode()) 227 return false; 228 229 230 // Check if it has an expression and is not RIP relative. 231 bool hasExp = false; 232 bool hasRIP = false; 233 for (unsigned i = 0; i < Inst.getNumOperands(); ++i) { 234 const MCOperand &Op = Inst.getOperand(i); 235 if (Op.isExpr()) 236 hasExp = true; 237 238 if (Op.isReg() && Op.getReg() == X86::RIP) 239 hasRIP = true; 240 } 241 242 // FIXME: Why exactly do we need the !hasRIP? Is it just a limitation on 243 // how we do relaxations? 244 return hasExp && !hasRIP; 245 } 246 247 // FIXME: Can tblgen help at all here to verify there aren't other instructions 248 // we can relax? 249 void X86AsmBackend::RelaxInstruction(const MCInst &Inst, MCInst &Res) const { 250 // The only relaxations X86 does is from a 1byte pcrel to a 4byte pcrel. 251 unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode()); 252 253 if (RelaxedOp == Inst.getOpcode()) { 254 SmallString<256> Tmp; 255 raw_svector_ostream OS(Tmp); 256 Inst.dump_pretty(OS); 257 OS << "\n"; 258 report_fatal_error("unexpected instruction to relax: " + OS.str()); 259 } 260 261 Res = Inst; 262 Res.setOpcode(RelaxedOp); 263 } 264 265 /// WriteNopData - Write optimal nops to the output file for the \arg Count 266 /// bytes. This returns the number of bytes written. It may return 0 if 267 /// the \arg Count is more than the maximum optimal nops. 268 bool X86AsmBackend::WriteNopData(uint64_t Count, MCObjectWriter *OW) const { 269 static const uint8_t Nops[10][10] = { 270 // nop 271 {0x90}, 272 // xchg %ax,%ax 273 {0x66, 0x90}, 274 // nopl (%[re]ax) 275 {0x0f, 0x1f, 0x00}, 276 // nopl 0(%[re]ax) 277 {0x0f, 0x1f, 0x40, 0x00}, 278 // nopl 0(%[re]ax,%[re]ax,1) 279 {0x0f, 0x1f, 0x44, 0x00, 0x00}, 280 // nopw 0(%[re]ax,%[re]ax,1) 281 {0x66, 0x0f, 0x1f, 0x44, 0x00, 0x00}, 282 // nopl 0L(%[re]ax) 283 {0x0f, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x00}, 284 // nopl 0L(%[re]ax,%[re]ax,1) 285 {0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00}, 286 // nopw 0L(%[re]ax,%[re]ax,1) 287 {0x66, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00}, 288 // nopw %cs:0L(%[re]ax,%[re]ax,1) 289 {0x66, 0x2e, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00}, 290 }; 291 292 // Write an optimal sequence for the first 15 bytes. 293 const uint64_t OptimalCount = (Count < 16) ? Count : 15; 294 const uint64_t Prefixes = OptimalCount <= 10 ? 0 : OptimalCount - 10; 295 for (uint64_t i = 0, e = Prefixes; i != e; i++) 296 OW->Write8(0x66); 297 const uint64_t Rest = OptimalCount - Prefixes; 298 for (uint64_t i = 0, e = Rest; i != e; i++) 299 OW->Write8(Nops[Rest - 1][i]); 300 301 // Finish with single byte nops. 302 for (uint64_t i = OptimalCount, e = Count; i != e; ++i) 303 OW->Write8(0x90); 304 305 return true; 306 } 307 308 /* *** */ 309 310 namespace { 311 class ELFX86AsmBackend : public X86AsmBackend { 312 public: 313 Triple::OSType OSType; 314 ELFX86AsmBackend(const Target &T, Triple::OSType _OSType) 315 : X86AsmBackend(T), OSType(_OSType) { 316 HasReliableSymbolDifference = true; 317 } 318 319 virtual bool doesSectionRequireSymbols(const MCSection &Section) const { 320 const MCSectionELF &ES = static_cast<const MCSectionELF&>(Section); 321 return ES.getFlags() & ELF::SHF_MERGE; 322 } 323 }; 324 325 class ELFX86_32AsmBackend : public ELFX86AsmBackend { 326 public: 327 ELFX86_32AsmBackend(const Target &T, Triple::OSType OSType) 328 : ELFX86AsmBackend(T, OSType) {} 329 330 MCObjectWriter *createObjectWriter(raw_ostream &OS) const { 331 return createELFObjectWriter(createELFObjectTargetWriter(), 332 OS, /*IsLittleEndian*/ true); 333 } 334 335 MCELFObjectTargetWriter *createELFObjectTargetWriter() const { 336 return new X86ELFObjectWriter(false, OSType, ELF::EM_386, false); 337 } 338 }; 339 340 class ELFX86_64AsmBackend : public ELFX86AsmBackend { 341 public: 342 ELFX86_64AsmBackend(const Target &T, Triple::OSType OSType) 343 : ELFX86AsmBackend(T, OSType) {} 344 345 MCObjectWriter *createObjectWriter(raw_ostream &OS) const { 346 return createELFObjectWriter(createELFObjectTargetWriter(), 347 OS, /*IsLittleEndian*/ true); 348 } 349 350 MCELFObjectTargetWriter *createELFObjectTargetWriter() const { 351 return new X86ELFObjectWriter(true, OSType, ELF::EM_X86_64, true); 352 } 353 }; 354 355 class WindowsX86AsmBackend : public X86AsmBackend { 356 bool Is64Bit; 357 358 public: 359 WindowsX86AsmBackend(const Target &T, bool is64Bit) 360 : X86AsmBackend(T) 361 , Is64Bit(is64Bit) { 362 } 363 364 MCObjectWriter *createObjectWriter(raw_ostream &OS) const { 365 return createWinCOFFObjectWriter(OS, Is64Bit); 366 } 367 }; 368 369 class DarwinX86AsmBackend : public X86AsmBackend { 370 public: 371 DarwinX86AsmBackend(const Target &T) 372 : X86AsmBackend(T) { } 373 }; 374 375 class DarwinX86_32AsmBackend : public DarwinX86AsmBackend { 376 public: 377 DarwinX86_32AsmBackend(const Target &T) 378 : DarwinX86AsmBackend(T) {} 379 380 MCObjectWriter *createObjectWriter(raw_ostream &OS) const { 381 return createX86MachObjectWriter(OS, /*Is64Bit=*/false, 382 object::mach::CTM_i386, 383 object::mach::CSX86_ALL); 384 } 385 }; 386 387 class DarwinX86_64AsmBackend : public DarwinX86AsmBackend { 388 public: 389 DarwinX86_64AsmBackend(const Target &T) 390 : DarwinX86AsmBackend(T) { 391 HasReliableSymbolDifference = true; 392 } 393 394 MCObjectWriter *createObjectWriter(raw_ostream &OS) const { 395 return createX86MachObjectWriter(OS, /*Is64Bit=*/true, 396 object::mach::CTM_x86_64, 397 object::mach::CSX86_ALL); 398 } 399 400 virtual bool doesSectionRequireSymbols(const MCSection &Section) const { 401 // Temporary labels in the string literals sections require symbols. The 402 // issue is that the x86_64 relocation format does not allow symbol + 403 // offset, and so the linker does not have enough information to resolve the 404 // access to the appropriate atom unless an external relocation is used. For 405 // non-cstring sections, we expect the compiler to use a non-temporary label 406 // for anything that could have an addend pointing outside the symbol. 407 // 408 // See <rdar://problem/4765733>. 409 const MCSectionMachO &SMO = static_cast<const MCSectionMachO&>(Section); 410 return SMO.getType() == MCSectionMachO::S_CSTRING_LITERALS; 411 } 412 413 virtual bool isSectionAtomizable(const MCSection &Section) const { 414 const MCSectionMachO &SMO = static_cast<const MCSectionMachO&>(Section); 415 // Fixed sized data sections are uniqued, they cannot be diced into atoms. 416 switch (SMO.getType()) { 417 default: 418 return true; 419 420 case MCSectionMachO::S_4BYTE_LITERALS: 421 case MCSectionMachO::S_8BYTE_LITERALS: 422 case MCSectionMachO::S_16BYTE_LITERALS: 423 case MCSectionMachO::S_LITERAL_POINTERS: 424 case MCSectionMachO::S_NON_LAZY_SYMBOL_POINTERS: 425 case MCSectionMachO::S_LAZY_SYMBOL_POINTERS: 426 case MCSectionMachO::S_MOD_INIT_FUNC_POINTERS: 427 case MCSectionMachO::S_MOD_TERM_FUNC_POINTERS: 428 case MCSectionMachO::S_INTERPOSING: 429 return false; 430 } 431 } 432 }; 433 434 } // end anonymous namespace 435 436 MCAsmBackend *llvm::createX86_32AsmBackend(const Target &T, StringRef TT) { 437 Triple TheTriple(TT); 438 439 if (TheTriple.isOSDarwin() || TheTriple.getEnvironment() == Triple::MachO) 440 return new DarwinX86_32AsmBackend(T); 441 442 if (TheTriple.isOSWindows()) 443 return new WindowsX86AsmBackend(T, false); 444 445 return new ELFX86_32AsmBackend(T, TheTriple.getOS()); 446 } 447 448 MCAsmBackend *llvm::createX86_64AsmBackend(const Target &T, StringRef TT) { 449 Triple TheTriple(TT); 450 451 if (TheTriple.isOSDarwin() || TheTriple.getEnvironment() == Triple::MachO) 452 return new DarwinX86_64AsmBackend(T); 453 454 if (TheTriple.isOSWindows()) 455 return new WindowsX86AsmBackend(T, true); 456 457 return new ELFX86_64AsmBackend(T, TheTriple.getOS()); 458 } 459
