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      1 @ RUN: not llvm-mc -triple=thumbv6-apple-darwin < %s 2> %t
      2 @ RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
      3 @ RUN: not llvm-mc -triple=thumbv5-apple-darwin < %s 2> %t
      4 @ RUN: FileCheck --check-prefix=CHECK-ERRORS-V5 < %t %s
      5 
      6 @ Check for various assembly diagnostic messages on invalid input.
      7 
      8 @ ADD instruction w/o 'S' suffix.
      9         add r1, r2, r3
     10 @ CHECK-ERRORS: error: invalid instruction
     11 @ CHECK-ERRORS:         add r1, r2, r3
     12 @ CHECK-ERRORS:         ^
     13 
     14 @ Instructions which require v6+ for both registers to be low regs.
     15         add r2, r3
     16         mov r2, r3
     17 @ CHECK-ERRORS: error: instruction variant requires Thumb2
     18 @ CHECK-ERRORS:         add r2, r3
     19 @ CHECK-ERRORS:         ^
     20 @ CHECK-ERRORS-V5: error: instruction variant requires ARMv6 or later
     21 @ CHECK-ERRORS-V5:         mov r2, r3
     22 @ CHECK-ERRORS-V5:         ^
     23 
     24 
     25 @ Out of range immediates for ASR instruction.
     26         asrs r2, r3, #33
     27         asrs r2, r3, #0
     28 @ CHECK-ERRORS: error: invalid operand for instruction
     29 @ CHECK-ERRORS:         asrs r2, r3, #33
     30 @ CHECK-ERRORS:                      ^
     31 @ CHECK-ERRORS: error: invalid operand for instruction
     32 @ CHECK-ERRORS:         asrs r2, r3, #0
     33 @ CHECK-ERRORS:                      ^
     34 
     35 @ Out of range immediates for BKPT instruction.
     36         bkpt #256
     37         bkpt #-1
     38 error: invalid operand for instruction
     39         bkpt #256
     40              ^
     41 error: invalid operand for instruction
     42         bkpt #-1
     43              ^
     44 
     45 @ Invalid writeback and register lists for LDM
     46         ldm r2!, {r5, r8}
     47         ldm r2, {r5, r7}
     48         ldm r2!, {r2, r3, r4}
     49 @ CHECK-ERRORS: error: registers must be in range r0-r7
     50 @ CHECK-ERRORS:         ldm r2!, {r5, r8}
     51 @ CHECK-ERRORS:                  ^
     52 @ CHECK-ERRORS: error: writeback operator '!' expected
     53 @ CHECK-ERRORS:         ldm r2, {r5, r7}
     54 @ CHECK-ERRORS:             ^
     55 @ CHECK-ERRORS: error: writeback operator '!' not allowed when base register in register list
     56 @ CHECK-ERRORS:         ldm r2!, {r2, r3, r4}
     57 @ CHECK-ERRORS:               ^
     58 
     59 
     60 @ Invalid writeback and register lists for PUSH/POP
     61         pop {r1, r2, r10}
     62         push {r8, r9}
     63 @ CHECK-ERRORS: error: registers must be in range r0-r7 or pc
     64 @ CHECK-ERRORS:         pop {r1, r2, r10}
     65 @ CHECK-ERRORS:             ^
     66 @ CHECK-ERRORS: error: registers must be in range r0-r7 or lr
     67 @ CHECK-ERRORS:         push {r8, r9}
     68 @ CHECK-ERRORS:              ^
     69 
     70 
     71 @ Invalid writeback and register lists for STM
     72         stm r1, {r2, r6}
     73         stm r1!, {r2, r9}
     74 @ CHECK-ERRORS: error: instruction requires a CPU feature not currently enabled
     75 @ CHECK-ERRORS:         stm r1, {r2, r6}
     76 @ CHECK-ERRORS:         ^
     77 @ CHECK-ERRORS: error: registers must be in range r0-r7
     78 @ CHECK-ERRORS:         stm r1!, {r2, r9}
     79 @ CHECK-ERRORS:                  ^
     80 
     81 @ Out of range immediates for LSL instruction.
     82         lsls r4, r5, #-1
     83         lsls r4, r5, #32
     84 @ CHECK-ERRORS: error: invalid operand for instruction
     85 @ CHECK-ERRORS:         lsls r4, r5, #-1
     86 @ CHECK-ERRORS:                      ^
     87 @ CHECK-ERRORS: error: invalid operand for instruction
     88 @ CHECK-ERRORS:         lsls r4, r5, #32
     89 @ CHECK-ERRORS:                      ^
     90 
     91 @ Mismatched source/destination operands for MUL instruction.
     92         muls r1, r2, r3
     93 @ CHECK-ERRORS: error: destination register must match source register
     94 @ CHECK-ERRORS:         muls r1, r2, r3
     95 @ CHECK-ERRORS:              ^
     96 
     97 
     98 @ Out of range immediates for STR instruction.
     99         str r2, [r7, #-1]
    100         str r5, [r1, #3]
    101         str r3, [r7, #128]
    102 @ CHECK-ERRORS: error: instruction requires a CPU feature not currently enabled
    103 @ CHECK-ERRORS:         str r2, [r7, #-1]
    104 @ CHECK-ERRORS:         ^
    105 @ CHECK-ERRORS: error: instruction requires a CPU feature not currently enabled
    106 @ CHECK-ERRORS:         str r5, [r1, #3]
    107 @ CHECK-ERRORS:         ^
    108 @ CHECK-ERRORS: error: instruction requires a CPU feature not currently enabled
    109 @ CHECK-ERRORS:         str r3, [r7, #128]
    110 @ CHECK-ERRORS:         ^
    111 
    112 @ Out of range immediate for SVC instruction.
    113         svc #-1
    114         svc #256
    115 @ CHECK-ERRORS: error: invalid operand for instruction
    116 @ CHECK-ERRORS:         svc #-1
    117 @ CHECK-ERRORS:             ^
    118 @ CHECK-ERRORS: error: instruction requires a CPU feature not currently enabled
    119 @ CHECK-ERRORS:         svc #256
    120 @ CHECK-ERRORS:         ^
    121 
    122 
    123 @ Out of range immediate for ADD SP instructions
    124         add sp, #-1
    125         add sp, #3
    126         add sp, sp, #512
    127         add r2, sp, #1024
    128 @ CHECK-ERRORS: error: invalid operand for instruction
    129 @ CHECK-ERRORS:         add sp, #-1
    130 @ CHECK-ERRORS:                 ^
    131 @ CHECK-ERRORS: error: invalid operand for instruction
    132 @ CHECK-ERRORS:         add sp, #3
    133 @ CHECK-ERRORS:                 ^
    134 @ CHECK-ERRORS: error: instruction requires a CPU feature not currently enabled
    135 @ CHECK-ERRORS:         add sp, sp, #512
    136 @ CHECK-ERRORS:                     ^
    137 @ CHECK-ERRORS: error: instruction requires a CPU feature not currently enabled
    138 @ CHECK-ERRORS:         add r2, sp, #1024
    139 @ CHECK-ERRORS:         ^
    140