1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef __UAPI_MSMB_ISP__ 20 #define __UAPI_MSMB_ISP__ 21 #include <linux/videodev2.h> 22 #include <media/msmb_camera.h> 23 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 24 #define MAX_PLANES_PER_STREAM 3 25 #define MAX_NUM_STREAM 7 26 #define ISP_VERSION_48 48 27 #define ISP_VERSION_47 47 28 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 29 #define ISP_VERSION_46 46 30 #define ISP_VERSION_44 44 31 #define ISP_VERSION_40 40 32 #define ISP_VERSION_32 32 33 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 34 #define ISP_NATIVE_BUF_BIT (0x10000 << 0) 35 #define ISP0_BIT (0x10000 << 1) 36 #define ISP1_BIT (0x10000 << 2) 37 #define ISP_META_CHANNEL_BIT (0x10000 << 3) 38 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 39 #define ISP_SCRATCH_BUF_BIT (0x10000 << 4) 40 #define ISP_OFFLINE_STATS_BIT (0x10000 << 5) 41 #define ISP_SVHDR_IN_BIT (0x10000 << 6) 42 #define ISP_SVHDR_OUT_BIT (0x10000 << 7) 43 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 44 #define ISP_STATS_STREAM_BIT 0x80000000 45 #define VFE_HW_LIMIT 1 46 struct msm_vfe_cfg_cmd_list; 47 enum ISP_START_PIXEL_PATTERN { 48 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 49 ISP_BAYER_RGRGRG, 50 ISP_BAYER_GRGRGR, 51 ISP_BAYER_BGBGBG, 52 ISP_BAYER_GBGBGB, 53 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 54 ISP_YUV_YCbYCr, 55 ISP_YUV_YCrYCb, 56 ISP_YUV_CbYCrY, 57 ISP_YUV_CrYCbY, 58 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 59 ISP_PIX_PATTERN_MAX 60 }; 61 enum msm_vfe_plane_fmt { 62 Y_PLANE, 63 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 64 CB_PLANE, 65 CR_PLANE, 66 CRCB_PLANE, 67 CBCR_PLANE, 68 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 69 VFE_PLANE_FMT_MAX 70 }; 71 enum msm_vfe_input_src { 72 VFE_PIX_0, 73 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 74 VFE_RAW_0, 75 VFE_RAW_1, 76 VFE_RAW_2, 77 VFE_SRC_MAX, 78 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 79 }; 80 enum msm_vfe_axi_stream_src { 81 PIX_ENCODER, 82 PIX_VIEWFINDER, 83 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 84 PIX_VIDEO, 85 CAMIF_RAW, 86 IDEAL_RAW, 87 RDI_INTF_0, 88 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 89 RDI_INTF_1, 90 RDI_INTF_2, 91 VFE_AXI_SRC_MAX 92 }; 93 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 94 enum msm_vfe_frame_skip_pattern { 95 NO_SKIP, 96 EVERY_2FRAME, 97 EVERY_3FRAME, 98 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 99 EVERY_4FRAME, 100 EVERY_5FRAME, 101 EVERY_6FRAME, 102 EVERY_7FRAME, 103 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 104 EVERY_8FRAME, 105 EVERY_16FRAME, 106 EVERY_32FRAME, 107 SKIP_ALL, 108 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 109 SKIP_RANGE, 110 MAX_SKIP, 111 }; 112 #define MSM_VFE_STREAM_STOP_PERIOD 15 113 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 114 enum msm_isp_stats_type { 115 MSM_ISP_STATS_AEC, 116 MSM_ISP_STATS_AF, 117 MSM_ISP_STATS_AWB, 118 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 119 MSM_ISP_STATS_RS, 120 MSM_ISP_STATS_CS, 121 MSM_ISP_STATS_IHIST, 122 MSM_ISP_STATS_SKIN, 123 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 124 MSM_ISP_STATS_BG, 125 MSM_ISP_STATS_BF, 126 MSM_ISP_STATS_BE, 127 MSM_ISP_STATS_BHIST, 128 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 129 MSM_ISP_STATS_BF_SCALE, 130 MSM_ISP_STATS_HDR_BE, 131 MSM_ISP_STATS_HDR_BHIST, 132 MSM_ISP_STATS_AEC_BG, 133 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 134 MSM_ISP_STATS_MAX 135 }; 136 struct msm_isp_sw_framskip { 137 uint32_t stats_type_mask; 138 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 139 uint32_t stream_src_mask; 140 enum msm_vfe_frame_skip_pattern skip_mode; 141 uint32_t min_frame_id; 142 uint32_t max_frame_id; 143 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 144 }; 145 enum msm_vfe_testgen_color_pattern { 146 COLOR_BAR_8_COLOR, 147 UNICOLOR_WHITE, 148 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 149 UNICOLOR_YELLOW, 150 UNICOLOR_CYAN, 151 UNICOLOR_GREEN, 152 UNICOLOR_MAGENTA, 153 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 154 UNICOLOR_RED, 155 UNICOLOR_BLUE, 156 UNICOLOR_BLACK, 157 MAX_COLOR, 158 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 159 }; 160 enum msm_vfe_camif_input { 161 CAMIF_DISABLED, 162 CAMIF_PAD_REG_INPUT, 163 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 164 CAMIF_MIDDI_INPUT, 165 CAMIF_MIPI_INPUT, 166 }; 167 struct msm_vfe_fetch_engine_cfg { 168 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 169 uint32_t input_format; 170 uint32_t buf_width; 171 uint32_t buf_height; 172 uint32_t fetch_width; 173 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 174 uint32_t fetch_height; 175 uint32_t x_offset; 176 uint32_t y_offset; 177 uint32_t buf_stride; 178 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 179 }; 180 enum msm_vfe_camif_output_format { 181 CAMIF_QCOM_RAW, 182 CAMIF_MIPI_RAW, 183 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 184 CAMIF_PLAIN_8, 185 CAMIF_PLAIN_16, 186 CAMIF_MAX_FORMAT, 187 }; 188 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 189 struct msm_vfe_camif_subsample_cfg { 190 uint32_t irq_subsample_period; 191 uint32_t irq_subsample_pattern; 192 uint32_t sof_counter_step; 193 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 194 uint32_t pixel_skip; 195 uint32_t line_skip; 196 uint32_t first_line; 197 uint32_t last_line; 198 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 199 uint32_t first_pixel; 200 uint32_t last_pixel; 201 enum msm_vfe_camif_output_format output_format; 202 }; 203 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 204 struct msm_vfe_camif_cfg { 205 uint32_t lines_per_frame; 206 uint32_t pixels_per_line; 207 uint32_t first_pixel; 208 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 209 uint32_t last_pixel; 210 uint32_t first_line; 211 uint32_t last_line; 212 uint32_t epoch_line0; 213 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 214 uint32_t epoch_line1; 215 uint32_t is_split; 216 enum msm_vfe_camif_input camif_input; 217 struct msm_vfe_camif_subsample_cfg subsample_cfg; 218 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 219 }; 220 struct msm_vfe_testgen_cfg { 221 uint32_t lines_per_frame; 222 uint32_t pixels_per_line; 223 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 224 uint32_t v_blank; 225 uint32_t h_blank; 226 enum ISP_START_PIXEL_PATTERN pixel_bayer_pattern; 227 uint32_t rotate_period; 228 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 229 enum msm_vfe_testgen_color_pattern color_bar_pattern; 230 uint32_t burst_num_frame; 231 }; 232 enum msm_vfe_inputmux { 233 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 234 CAMIF, 235 TESTGEN, 236 EXTERNAL_READ, 237 }; 238 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 239 enum msm_vfe_stats_composite_group { 240 STATS_COMPOSITE_GRP_NONE, 241 STATS_COMPOSITE_GRP_1, 242 STATS_COMPOSITE_GRP_2, 243 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 244 STATS_COMPOSITE_GRP_MAX, 245 }; 246 enum msm_vfe_hvx_streaming_cmd { 247 HVX_DISABLE, 248 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 249 HVX_ONE_WAY, 250 HVX_ROUND_TRIP 251 }; 252 struct msm_vfe_pix_cfg { 253 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 254 struct msm_vfe_camif_cfg camif_cfg; 255 struct msm_vfe_testgen_cfg testgen_cfg; 256 struct msm_vfe_fetch_engine_cfg fetch_engine_cfg; 257 enum msm_vfe_inputmux input_mux; 258 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 259 enum ISP_START_PIXEL_PATTERN pixel_pattern; 260 uint32_t input_format; 261 enum msm_vfe_hvx_streaming_cmd hvx_cmd; 262 uint32_t is_split; 263 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 264 }; 265 struct msm_vfe_rdi_cfg { 266 uint8_t cid; 267 uint8_t frame_based; 268 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 269 }; 270 struct msm_vfe_input_cfg { 271 union { 272 struct msm_vfe_pix_cfg pix_cfg; 273 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 274 struct msm_vfe_rdi_cfg rdi_cfg; 275 } d; 276 enum msm_vfe_input_src input_src; 277 uint32_t input_pix_clk; 278 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 279 }; 280 struct msm_vfe_fetch_eng_start { 281 uint32_t session_id; 282 uint32_t stream_id; 283 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 284 uint32_t buf_idx; 285 uint8_t offline_mode; 286 uint32_t fd; 287 uint32_t buf_addr; 288 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 289 uint32_t frame_id; 290 }; 291 enum msm_vfe_fetch_eng_pass { 292 OFFLINE_FIRST_PASS, 293 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 294 OFFLINE_SECOND_PASS, 295 OFFLINE_MAX_PASS, 296 }; 297 struct msm_vfe_fetch_eng_multi_pass_start { 298 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 299 uint32_t session_id; 300 uint32_t stream_id; 301 uint32_t buf_idx; 302 uint8_t offline_mode; 303 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 304 uint32_t fd; 305 uint32_t buf_addr; 306 uint32_t frame_id; 307 uint32_t output_buf_idx; 308 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 309 uint32_t input_buf_offset; 310 enum msm_vfe_fetch_eng_pass offline_pass; 311 uint32_t output_stream_id; 312 }; 313 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 314 struct msm_vfe_axi_plane_cfg { 315 uint32_t output_width; 316 uint32_t output_height; 317 uint32_t output_stride; 318 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 319 uint32_t output_scan_lines; 320 uint32_t output_plane_format; 321 uint32_t plane_addr_offset; 322 uint8_t csid_src; 323 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 324 uint8_t rdi_cid; 325 }; 326 enum msm_stream_rdi_input_type { 327 MSM_CAMERA_RDI_MIN, 328 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 329 MSM_CAMERA_RDI_PDAF, 330 MSM_CAMERA_RDI_MAX, 331 }; 332 struct msm_vfe_axi_stream_request_cmd { 333 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 334 uint32_t session_id; 335 uint32_t stream_id; 336 uint32_t vt_enable; 337 uint32_t output_format; 338 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 339 enum msm_vfe_axi_stream_src stream_src; 340 struct msm_vfe_axi_plane_cfg plane_cfg[MAX_PLANES_PER_STREAM]; 341 uint32_t burst_count; 342 uint32_t hfr_mode; 343 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 344 uint8_t frame_base; 345 uint32_t init_frame_drop; 346 enum msm_vfe_frame_skip_pattern frame_skip_pattern; 347 uint8_t buf_divert; 348 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 349 uint32_t axi_stream_handle; 350 uint32_t controllable_output; 351 uint32_t burst_len; 352 enum msm_stream_rdi_input_type rdi_input_type; 353 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 354 }; 355 struct msm_vfe_axi_stream_release_cmd { 356 uint32_t stream_handle; 357 }; 358 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 359 enum msm_vfe_axi_stream_cmd { 360 STOP_STREAM, 361 START_STREAM, 362 STOP_IMMEDIATELY, 363 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 364 }; 365 struct msm_vfe_axi_stream_cfg_cmd { 366 uint8_t num_streams; 367 uint32_t stream_handle[VFE_AXI_SRC_MAX]; 368 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 369 enum msm_vfe_axi_stream_cmd cmd; 370 uint8_t sync_frame_id_src; 371 }; 372 enum msm_vfe_axi_stream_update_type { 373 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 374 ENABLE_STREAM_BUF_DIVERT, 375 DISABLE_STREAM_BUF_DIVERT, 376 UPDATE_STREAM_FRAMEDROP_PATTERN, 377 UPDATE_STREAM_STATS_FRAMEDROP_PATTERN, 378 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 379 UPDATE_STREAM_AXI_CONFIG, 380 UPDATE_STREAM_REQUEST_FRAMES, 381 UPDATE_STREAM_ADD_BUFQ, 382 UPDATE_STREAM_REMOVE_BUFQ, 383 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 384 UPDATE_STREAM_SW_FRAME_DROP, 385 UPDATE_STREAM_REQUEST_FRAMES_VER2, 386 UPDATE_STREAM_OFFLINE_AXI_CONFIG, 387 }; 388 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 389 #define UPDATE_STREAM_REQUEST_FRAMES_VER2 UPDATE_STREAM_REQUEST_FRAMES_VER2 390 enum msm_vfe_iommu_type { 391 IOMMU_ATTACH, 392 IOMMU_DETACH, 393 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 394 }; 395 enum msm_vfe_buff_queue_id { 396 VFE_BUF_QUEUE_DEFAULT, 397 VFE_BUF_QUEUE_SHARED, 398 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 399 VFE_BUF_QUEUE_MAX, 400 }; 401 struct msm_vfe_axi_stream_cfg_update_info { 402 uint32_t stream_handle; 403 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 404 uint32_t output_format; 405 uint32_t user_stream_id; 406 uint32_t frame_id; 407 enum msm_vfe_frame_skip_pattern skip_pattern; 408 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 409 struct msm_vfe_axi_plane_cfg plane_cfg[MAX_PLANES_PER_STREAM]; 410 struct msm_isp_sw_framskip sw_skip_info; 411 }; 412 struct msm_vfe_axi_stream_cfg_update_info_req_frm { 413 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 414 uint32_t stream_handle; 415 uint32_t user_stream_id; 416 uint32_t frame_id; 417 uint32_t buf_index; 418 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 419 }; 420 struct msm_vfe_axi_halt_cmd { 421 uint32_t stop_camif; 422 uint32_t overflow_detected; 423 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 424 uint32_t blocking_halt; 425 }; 426 struct msm_vfe_axi_reset_cmd { 427 uint32_t blocking; 428 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 429 uint32_t frame_id; 430 }; 431 struct msm_vfe_axi_restart_cmd { 432 uint32_t enable_camif; 433 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 434 }; 435 struct msm_vfe_axi_stream_update_cmd { 436 uint32_t num_streams; 437 enum msm_vfe_axi_stream_update_type update_type; 438 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 439 union { 440 struct msm_vfe_axi_stream_cfg_update_info update_info[MSM_ISP_STATS_MAX]; 441 struct msm_vfe_axi_stream_cfg_update_info_req_frm req_frm_ver2; 442 }; 443 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 444 }; 445 struct msm_vfe_smmu_attach_cmd { 446 uint32_t security_mode; 447 uint32_t iommu_attach_mode; 448 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 449 }; 450 struct msm_vfe_stats_stream_request_cmd { 451 uint32_t session_id; 452 uint32_t stream_id; 453 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 454 enum msm_isp_stats_type stats_type; 455 uint32_t composite_flag; 456 uint32_t framedrop_pattern; 457 uint32_t init_frame_drop; 458 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 459 uint32_t irq_subsample_pattern; 460 uint32_t buffer_offset; 461 uint32_t stream_handle; 462 }; 463 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 464 struct msm_vfe_stats_stream_release_cmd { 465 uint32_t stream_handle; 466 }; 467 struct msm_vfe_stats_stream_cfg_cmd { 468 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 469 uint8_t num_streams; 470 uint32_t stream_handle[MSM_ISP_STATS_MAX]; 471 uint8_t enable; 472 uint32_t stats_burst_len; 473 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 474 }; 475 enum msm_vfe_reg_cfg_type { 476 VFE_WRITE, 477 VFE_WRITE_MB, 478 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 479 VFE_READ, 480 VFE_CFG_MASK, 481 VFE_WRITE_DMI_16BIT, 482 VFE_WRITE_DMI_32BIT, 483 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 484 VFE_WRITE_DMI_64BIT, 485 VFE_READ_DMI_16BIT, 486 VFE_READ_DMI_32BIT, 487 VFE_READ_DMI_64BIT, 488 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 489 GET_MAX_CLK_RATE, 490 GET_CLK_RATES, 491 GET_ISP_ID, 492 VFE_HW_UPDATE_LOCK, 493 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 494 VFE_HW_UPDATE_UNLOCK, 495 SET_WM_UB_SIZE, 496 SET_UB_POLICY, 497 GET_VFE_HW_LIMIT, 498 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 499 }; 500 struct msm_vfe_cfg_cmd2 { 501 uint16_t num_cfg; 502 uint16_t cmd_len; 503 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 504 void * cfg_data; 505 void * cfg_cmd; 506 }; 507 struct msm_vfe_cfg_cmd_list { 508 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 509 struct msm_vfe_cfg_cmd2 cfg_cmd; 510 struct msm_vfe_cfg_cmd_list * next; 511 uint32_t next_size; 512 }; 513 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 514 struct msm_vfe_reg_rw_info { 515 uint32_t reg_offset; 516 uint32_t cmd_data_offset; 517 uint32_t len; 518 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 519 }; 520 struct msm_vfe_reg_mask_info { 521 uint32_t reg_offset; 522 uint32_t mask; 523 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 524 uint32_t val; 525 }; 526 struct msm_vfe_reg_dmi_info { 527 uint32_t hi_tbl_offset; 528 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 529 uint32_t lo_tbl_offset; 530 uint32_t len; 531 }; 532 struct msm_vfe_reg_cfg_cmd { 533 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 534 union { 535 struct msm_vfe_reg_rw_info rw_info; 536 struct msm_vfe_reg_mask_info mask_info; 537 struct msm_vfe_reg_dmi_info dmi_info; 538 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 539 } u; 540 enum msm_vfe_reg_cfg_type cmd_type; 541 }; 542 enum vfe_sd_type { 543 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 544 VFE_SD_0 = 0, 545 VFE_SD_1, 546 VFE_SD_COMMON, 547 VFE_SD_MAX, 548 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 549 }; 550 #define MS_NUM_SLAVE_MAX 1 551 enum msm_vfe_dual_hw_type { 552 DUAL_NONE = 0, 553 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 554 DUAL_HW_VFE_SPLIT = 1, 555 DUAL_HW_MASTER_SLAVE = 2, 556 }; 557 enum msm_vfe_dual_hw_ms_type { 558 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 559 MS_TYPE_NONE, 560 MS_TYPE_MASTER, 561 MS_TYPE_SLAVE, 562 }; 563 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 564 struct msm_isp_set_dual_hw_ms_cmd { 565 uint8_t num_src; 566 enum msm_vfe_dual_hw_ms_type dual_hw_ms_type; 567 enum msm_vfe_input_src primary_intf; 568 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 569 enum msm_vfe_input_src input_src[VFE_SRC_MAX]; 570 uint32_t sof_delta_threshold; 571 }; 572 enum msm_isp_buf_type { 573 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 574 ISP_PRIVATE_BUF, 575 ISP_SHARE_BUF, 576 MAX_ISP_BUF_TYPE, 577 }; 578 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 579 struct msm_isp_unmap_buf_req { 580 uint32_t fd; 581 }; 582 struct msm_isp_buf_request { 583 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 584 uint32_t session_id; 585 uint32_t stream_id; 586 uint8_t num_buf; 587 uint32_t handle; 588 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 589 enum msm_isp_buf_type buf_type; 590 }; 591 struct msm_isp_buf_request_ver2 { 592 uint32_t session_id; 593 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 594 uint32_t stream_id; 595 uint8_t num_buf; 596 uint32_t handle; 597 enum msm_isp_buf_type buf_type; 598 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 599 enum smmu_attach_mode security_mode; 600 uint32_t reserved[4]; 601 }; 602 struct msm_isp_qbuf_plane { 603 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 604 uint32_t addr; 605 uint32_t offset; 606 uint32_t length; 607 }; 608 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 609 struct msm_isp_qbuf_buffer { 610 struct msm_isp_qbuf_plane planes[MAX_PLANES_PER_STREAM]; 611 uint32_t num_planes; 612 }; 613 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 614 struct msm_isp_qbuf_info { 615 uint32_t handle; 616 int32_t buf_idx; 617 struct msm_isp_qbuf_buffer buffer; 618 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 619 uint32_t dirty_buf; 620 }; 621 struct msm_isp_clk_rates { 622 uint32_t svs_rate; 623 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 624 uint32_t nominal_rate; 625 uint32_t high_rate; 626 }; 627 struct msm_vfe_axi_src_state { 628 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 629 enum msm_vfe_input_src input_src; 630 uint32_t src_active; 631 uint32_t src_frame_id; 632 }; 633 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 634 enum msm_isp_event_mask_index { 635 ISP_EVENT_MASK_INDEX_STATS_NOTIFY = 0, 636 ISP_EVENT_MASK_INDEX_ERROR = 1, 637 ISP_EVENT_MASK_INDEX_IOMMU_P_FAULT = 2, 638 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 639 ISP_EVENT_MASK_INDEX_STREAM_UPDATE_DONE = 3, 640 ISP_EVENT_MASK_INDEX_REG_UPDATE = 4, 641 ISP_EVENT_MASK_INDEX_SOF = 5, 642 ISP_EVENT_MASK_INDEX_BUF_DIVERT = 6, 643 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 644 ISP_EVENT_MASK_INDEX_COMP_STATS_NOTIFY = 7, 645 ISP_EVENT_MASK_INDEX_MASK_FE_READ_DONE = 8, 646 ISP_EVENT_MASK_INDEX_BUF_DONE = 9, 647 ISP_EVENT_MASK_INDEX_REG_UPDATE_MISSING = 10, 648 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 649 ISP_EVENT_MASK_INDEX_PING_PONG_MISMATCH = 11, 650 ISP_EVENT_MASK_INDEX_BUF_FATAL_ERROR = 12, 651 }; 652 #define ISP_EVENT_SUBS_MASK_NONE 0 653 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 654 #define ISP_EVENT_SUBS_MASK_STATS_NOTIFY (1 << ISP_EVENT_MASK_INDEX_STATS_NOTIFY) 655 #define ISP_EVENT_SUBS_MASK_ERROR (1 << ISP_EVENT_MASK_INDEX_ERROR) 656 #define ISP_EVENT_SUBS_MASK_IOMMU_P_FAULT (1 << ISP_EVENT_MASK_INDEX_IOMMU_P_FAULT) 657 #define ISP_EVENT_SUBS_MASK_STREAM_UPDATE_DONE (1 << ISP_EVENT_MASK_INDEX_STREAM_UPDATE_DONE) 658 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 659 #define ISP_EVENT_SUBS_MASK_REG_UPDATE (1 << ISP_EVENT_MASK_INDEX_REG_UPDATE) 660 #define ISP_EVENT_SUBS_MASK_SOF (1 << ISP_EVENT_MASK_INDEX_SOF) 661 #define ISP_EVENT_SUBS_MASK_BUF_DIVERT (1 << ISP_EVENT_MASK_INDEX_BUF_DIVERT) 662 #define ISP_EVENT_SUBS_MASK_COMP_STATS_NOTIFY (1 << ISP_EVENT_MASK_INDEX_COMP_STATS_NOTIFY) 663 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 664 #define ISP_EVENT_SUBS_MASK_FE_READ_DONE (1 << ISP_EVENT_MASK_INDEX_MASK_FE_READ_DONE) 665 #define ISP_EVENT_SUBS_MASK_BUF_DONE (1 << ISP_EVENT_MASK_INDEX_BUF_DONE) 666 #define ISP_EVENT_SUBS_MASK_REG_UPDATE_MISSING (1 << ISP_EVENT_MASK_INDEX_REG_UPDATE_MISSING) 667 #define ISP_EVENT_SUBS_MASK_PING_PONG_MISMATCH (1 << ISP_EVENT_MASK_INDEX_PING_PONG_MISMATCH) 668 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 669 #define ISP_EVENT_SUBS_MASK_BUF_FATAL_ERROR (1 << ISP_EVENT_MASK_INDEX_BUF_FATAL_ERROR) 670 enum msm_isp_event_idx { 671 ISP_REG_UPDATE = 0, 672 ISP_EPOCH_0 = 1, 673 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 674 ISP_EPOCH_1 = 2, 675 ISP_START_ACK = 3, 676 ISP_STOP_ACK = 4, 677 ISP_IRQ_VIOLATION = 5, 678 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 679 ISP_STATS_OVERFLOW = 6, 680 ISP_BUF_DONE = 7, 681 ISP_FE_RD_DONE = 8, 682 ISP_IOMMU_P_FAULT = 9, 683 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 684 ISP_ERROR = 10, 685 ISP_HW_FATAL_ERROR = 11, 686 ISP_PING_PONG_MISMATCH = 12, 687 ISP_REG_UPDATE_MISSING = 13, 688 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 689 ISP_BUF_FATAL_ERROR = 14, 690 ISP_EVENT_MAX = 15 691 }; 692 #define ISP_EVENT_OFFSET 8 693 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 694 #define ISP_EVENT_BASE (V4L2_EVENT_PRIVATE_START) 695 #define ISP_BUF_EVENT_BASE (ISP_EVENT_BASE + (1 << ISP_EVENT_OFFSET)) 696 #define ISP_STATS_EVENT_BASE (ISP_EVENT_BASE + (2 << ISP_EVENT_OFFSET)) 697 #define ISP_CAMIF_EVENT_BASE (ISP_EVENT_BASE + (3 << ISP_EVENT_OFFSET)) 698 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 699 #define ISP_STREAM_EVENT_BASE (ISP_EVENT_BASE + (4 << ISP_EVENT_OFFSET)) 700 #define ISP_EVENT_REG_UPDATE (ISP_EVENT_BASE + ISP_REG_UPDATE) 701 #define ISP_EVENT_EPOCH_0 (ISP_EVENT_BASE + ISP_EPOCH_0) 702 #define ISP_EVENT_EPOCH_1 (ISP_EVENT_BASE + ISP_EPOCH_1) 703 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 704 #define ISP_EVENT_START_ACK (ISP_EVENT_BASE + ISP_START_ACK) 705 #define ISP_EVENT_STOP_ACK (ISP_EVENT_BASE + ISP_STOP_ACK) 706 #define ISP_EVENT_IRQ_VIOLATION (ISP_EVENT_BASE + ISP_IRQ_VIOLATION) 707 #define ISP_EVENT_STATS_OVERFLOW (ISP_EVENT_BASE + ISP_STATS_OVERFLOW) 708 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 709 #define ISP_EVENT_ERROR (ISP_EVENT_BASE + ISP_ERROR) 710 #define ISP_EVENT_SOF (ISP_CAMIF_EVENT_BASE) 711 #define ISP_EVENT_EOF (ISP_CAMIF_EVENT_BASE + 1) 712 #define ISP_EVENT_BUF_DONE (ISP_EVENT_BASE + ISP_BUF_DONE) 713 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 714 #define ISP_EVENT_BUF_DIVERT (ISP_BUF_EVENT_BASE) 715 #define ISP_EVENT_STATS_NOTIFY (ISP_STATS_EVENT_BASE) 716 #define ISP_EVENT_COMP_STATS_NOTIFY (ISP_EVENT_STATS_NOTIFY + MSM_ISP_STATS_MAX) 717 #define ISP_EVENT_FE_READ_DONE (ISP_EVENT_BASE + ISP_FE_RD_DONE) 718 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 719 #define ISP_EVENT_IOMMU_P_FAULT (ISP_EVENT_BASE + ISP_IOMMU_P_FAULT) 720 #define ISP_EVENT_HW_FATAL_ERROR (ISP_EVENT_BASE + ISP_HW_FATAL_ERROR) 721 #define ISP_EVENT_PING_PONG_MISMATCH (ISP_EVENT_BASE + ISP_PING_PONG_MISMATCH) 722 #define ISP_EVENT_REG_UPDATE_MISSING (ISP_EVENT_BASE + ISP_REG_UPDATE_MISSING) 723 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 724 #define ISP_EVENT_BUF_FATAL_ERROR (ISP_EVENT_BASE + ISP_BUF_FATAL_ERROR) 725 #define ISP_EVENT_STREAM_UPDATE_DONE (ISP_STREAM_EVENT_BASE) 726 struct msm_isp_buf_event { 727 uint32_t session_id; 728 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 729 uint32_t stream_id; 730 uint32_t handle; 731 uint32_t output_format; 732 int8_t buf_idx; 733 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 734 }; 735 struct msm_isp_fetch_eng_event { 736 uint32_t session_id; 737 uint32_t stream_id; 738 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 739 uint32_t handle; 740 uint32_t fd; 741 int8_t buf_idx; 742 int8_t offline_mode; 743 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 744 }; 745 struct msm_isp_stats_event { 746 uint32_t stats_mask; 747 uint8_t stats_buf_idxs[MSM_ISP_STATS_MAX]; 748 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 749 uint8_t pd_stats_idx; 750 }; 751 struct msm_isp_stream_ack { 752 uint32_t session_id; 753 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 754 uint32_t stream_id; 755 uint32_t handle; 756 }; 757 enum msm_vfe_error_type { 758 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 759 ISP_ERROR_NONE, 760 ISP_ERROR_CAMIF, 761 ISP_ERROR_BUS_OVERFLOW, 762 ISP_ERROR_RETURN_EMPTY_BUFFER, 763 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 764 ISP_ERROR_FRAME_ID_MISMATCH, 765 ISP_ERROR_MAX, 766 }; 767 struct msm_isp_error_info { 768 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 769 enum msm_vfe_error_type err_type; 770 uint32_t session_id; 771 uint32_t stream_id; 772 uint32_t stream_id_mask; 773 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 774 }; 775 struct msm_isp_ms_delta_info { 776 uint8_t num_delta_info; 777 uint32_t delta[MS_NUM_SLAVE_MAX]; 778 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 779 }; 780 struct msm_isp_output_info { 781 uint8_t regs_not_updated; 782 uint16_t output_err_mask; 783 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 784 uint8_t stream_framedrop_mask; 785 uint16_t stats_framedrop_mask; 786 }; 787 struct msm_isp_sof_info { 788 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 789 uint8_t regs_not_updated; 790 uint16_t reg_update_fail_mask; 791 uint32_t stream_get_buf_fail_mask; 792 uint16_t stats_get_buf_fail_mask; 793 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 794 struct msm_isp_ms_delta_info ms_delta_info; 795 uint16_t axi_updating_mask; 796 uint32_t reg_update_fail_mask_ext; 797 }; 798 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 799 #define AXI_UPDATING_MASK 1 800 #define REG_UPDATE_FAIL_MASK_EXT 1 801 struct msm_isp_event_data { 802 struct timeval timestamp; 803 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 804 struct timeval mono_timestamp; 805 uint32_t frame_id; 806 union { 807 struct msm_isp_stats_event stats; 808 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 809 struct msm_isp_buf_event buf_done; 810 struct msm_isp_fetch_eng_event fetch_done; 811 struct msm_isp_error_info error_info; 812 struct msm_isp_output_info output_info; 813 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 814 struct msm_isp_sof_info sof_info; 815 } u; 816 }; 817 enum msm_vfe_ahb_clk_vote { 818 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 819 MSM_ISP_CAMERA_AHB_SVS_VOTE = 1, 820 MSM_ISP_CAMERA_AHB_TURBO_VOTE = 2, 821 MSM_ISP_CAMERA_AHB_NOMINAL_VOTE = 3, 822 MSM_ISP_CAMERA_AHB_SUSPEND_VOTE = 4, 823 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 824 }; 825 struct msm_isp_ahb_clk_cfg { 826 uint32_t vote; 827 uint32_t reserved[2]; 828 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 829 }; 830 enum msm_vfe_dual_cam_sync_mode { 831 MSM_ISP_DUAL_CAM_ASYNC, 832 MSM_ISP_DUAL_CAM_SYNC, 833 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 834 }; 835 struct msm_isp_dual_hw_master_slave_sync { 836 uint32_t sync_mode; 837 uint32_t reserved[2]; 838 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 839 }; 840 struct msm_vfe_dual_lpm_mode { 841 enum msm_vfe_axi_stream_src stream_src[VFE_AXI_SRC_MAX]; 842 uint32_t num_src; 843 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 844 uint32_t lpm_mode; 845 }; 846 #define V4L2_PIX_FMT_QBGGR8 v4l2_fourcc('Q', 'B', 'G', '8') 847 #define V4L2_PIX_FMT_QGBRG8 v4l2_fourcc('Q', 'G', 'B', '8') 848 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 849 #define V4L2_PIX_FMT_QGRBG8 v4l2_fourcc('Q', 'G', 'R', '8') 850 #define V4L2_PIX_FMT_QRGGB8 v4l2_fourcc('Q', 'R', 'G', '8') 851 #define V4L2_PIX_FMT_QBGGR10 v4l2_fourcc('Q', 'B', 'G', '0') 852 #define V4L2_PIX_FMT_QGBRG10 v4l2_fourcc('Q', 'G', 'B', '0') 853 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 854 #define V4L2_PIX_FMT_QGRBG10 v4l2_fourcc('Q', 'G', 'R', '0') 855 #define V4L2_PIX_FMT_QRGGB10 v4l2_fourcc('Q', 'R', 'G', '0') 856 #define V4L2_PIX_FMT_QBGGR12 v4l2_fourcc('Q', 'B', 'G', '2') 857 #define V4L2_PIX_FMT_QGBRG12 v4l2_fourcc('Q', 'G', 'B', '2') 858 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 859 #define V4L2_PIX_FMT_QGRBG12 v4l2_fourcc('Q', 'G', 'R', '2') 860 #define V4L2_PIX_FMT_QRGGB12 v4l2_fourcc('Q', 'R', 'G', '2') 861 #define V4L2_PIX_FMT_QBGGR14 v4l2_fourcc('Q', 'B', 'G', '4') 862 #define V4L2_PIX_FMT_QGBRG14 v4l2_fourcc('Q', 'G', 'B', '4') 863 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 864 #define V4L2_PIX_FMT_QGRBG14 v4l2_fourcc('Q', 'G', 'R', '4') 865 #define V4L2_PIX_FMT_QRGGB14 v4l2_fourcc('Q', 'R', 'G', '4') 866 #define V4L2_PIX_FMT_P16BGGR10 v4l2_fourcc('P', 'B', 'G', '0') 867 #define V4L2_PIX_FMT_P16GBRG10 v4l2_fourcc('P', 'G', 'B', '0') 868 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 869 #define V4L2_PIX_FMT_P16GRBG10 v4l2_fourcc('P', 'G', 'R', '0') 870 #define V4L2_PIX_FMT_P16RGGB10 v4l2_fourcc('P', 'R', 'G', '0') 871 #define V4L2_PIX_FMT_NV14 v4l2_fourcc('N', 'V', '1', '4') 872 #define V4L2_PIX_FMT_NV41 v4l2_fourcc('N', 'V', '4', '1') 873 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 874 #define V4L2_PIX_FMT_META v4l2_fourcc('Q', 'M', 'E', 'T') 875 #define V4L2_PIX_FMT_META10 v4l2_fourcc('Q', 'M', '1', '0') 876 #define V4L2_PIX_FMT_SBGGR14 v4l2_fourcc('B', 'G', '1', '4') 877 #define V4L2_PIX_FMT_SGBRG14 v4l2_fourcc('G', 'B', '1', '4') 878 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 879 #define V4L2_PIX_FMT_SGRBG14 v4l2_fourcc('B', 'A', '1', '4') 880 #define V4L2_PIX_FMT_SRGGB14 v4l2_fourcc('R', 'G', '1', '4') 881 enum msm_isp_ioctl_cmd_code { 882 MSM_VFE_REG_CFG = BASE_VIDIOC_PRIVATE, 883 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 884 MSM_ISP_REQUEST_BUF, 885 MSM_ISP_ENQUEUE_BUF, 886 MSM_ISP_RELEASE_BUF, 887 MSM_ISP_REQUEST_STREAM, 888 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 889 MSM_ISP_CFG_STREAM, 890 MSM_ISP_RELEASE_STREAM, 891 MSM_ISP_INPUT_CFG, 892 MSM_ISP_SET_SRC_STATE, 893 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 894 MSM_ISP_REQUEST_STATS_STREAM, 895 MSM_ISP_CFG_STATS_STREAM, 896 MSM_ISP_RELEASE_STATS_STREAM, 897 MSM_ISP_REG_UPDATE_CMD, 898 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 899 MSM_ISP_UPDATE_STREAM, 900 MSM_VFE_REG_LIST_CFG, 901 MSM_ISP_SMMU_ATTACH, 902 MSM_ISP_UPDATE_STATS_STREAM, 903 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 904 MSM_ISP_AXI_HALT, 905 MSM_ISP_AXI_RESET, 906 MSM_ISP_AXI_RESTART, 907 MSM_ISP_FETCH_ENG_START, 908 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 909 MSM_ISP_DEQUEUE_BUF, 910 MSM_ISP_SET_DUAL_HW_MASTER_SLAVE, 911 MSM_ISP_MAP_BUF_START_FE, 912 MSM_ISP_UNMAP_BUF, 913 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 914 MSM_ISP_AHB_CLK_CFG, 915 MSM_ISP_DUAL_HW_MASTER_SLAVE_SYNC, 916 MSM_ISP_FETCH_ENG_MULTI_PASS_START, 917 MSM_ISP_MAP_BUF_START_MULTI_PASS_FE, 918 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 919 MSM_ISP_REQUEST_BUF_VER2, 920 MSM_ISP_DUAL_HW_LPM_MODE, 921 }; 922 #define VIDIOC_MSM_VFE_REG_CFG _IOWR('V', MSM_VFE_REG_CFG, struct msm_vfe_cfg_cmd2) 923 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 924 #define VIDIOC_MSM_ISP_REQUEST_BUF _IOWR('V', MSM_ISP_REQUEST_BUF, struct msm_isp_buf_request) 925 #define VIDIOC_MSM_ISP_ENQUEUE_BUF _IOWR('V', MSM_ISP_ENQUEUE_BUF, struct msm_isp_qbuf_info) 926 #define VIDIOC_MSM_ISP_RELEASE_BUF _IOWR('V', MSM_ISP_RELEASE_BUF, struct msm_isp_buf_request) 927 #define VIDIOC_MSM_ISP_REQUEST_STREAM _IOWR('V', MSM_ISP_REQUEST_STREAM, struct msm_vfe_axi_stream_request_cmd) 928 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 929 #define VIDIOC_MSM_ISP_CFG_STREAM _IOWR('V', MSM_ISP_CFG_STREAM, struct msm_vfe_axi_stream_cfg_cmd) 930 #define VIDIOC_MSM_ISP_RELEASE_STREAM _IOWR('V', MSM_ISP_RELEASE_STREAM, struct msm_vfe_axi_stream_release_cmd) 931 #define VIDIOC_MSM_ISP_INPUT_CFG _IOWR('V', MSM_ISP_INPUT_CFG, struct msm_vfe_input_cfg) 932 #define VIDIOC_MSM_ISP_SET_SRC_STATE _IOWR('V', MSM_ISP_SET_SRC_STATE, struct msm_vfe_axi_src_state) 933 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 934 #define VIDIOC_MSM_ISP_REQUEST_STATS_STREAM _IOWR('V', MSM_ISP_REQUEST_STATS_STREAM, struct msm_vfe_stats_stream_request_cmd) 935 #define VIDIOC_MSM_ISP_CFG_STATS_STREAM _IOWR('V', MSM_ISP_CFG_STATS_STREAM, struct msm_vfe_stats_stream_cfg_cmd) 936 #define VIDIOC_MSM_ISP_RELEASE_STATS_STREAM _IOWR('V', MSM_ISP_RELEASE_STATS_STREAM, struct msm_vfe_stats_stream_release_cmd) 937 #define VIDIOC_MSM_ISP_REG_UPDATE_CMD _IOWR('V', MSM_ISP_REG_UPDATE_CMD, enum msm_vfe_input_src) 938 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 939 #define VIDIOC_MSM_ISP_UPDATE_STREAM _IOWR('V', MSM_ISP_UPDATE_STREAM, struct msm_vfe_axi_stream_update_cmd) 940 #define VIDIOC_MSM_VFE_REG_LIST_CFG _IOWR('V', MSM_VFE_REG_LIST_CFG, struct msm_vfe_cfg_cmd_list) 941 #define VIDIOC_MSM_ISP_SMMU_ATTACH _IOWR('V', MSM_ISP_SMMU_ATTACH, struct msm_vfe_smmu_attach_cmd) 942 #define VIDIOC_MSM_ISP_UPDATE_STATS_STREAM _IOWR('V', MSM_ISP_UPDATE_STATS_STREAM, struct msm_vfe_axi_stream_update_cmd) 943 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 944 #define VIDIOC_MSM_ISP_AXI_HALT _IOWR('V', MSM_ISP_AXI_HALT, struct msm_vfe_axi_halt_cmd) 945 #define VIDIOC_MSM_ISP_AXI_RESET _IOWR('V', MSM_ISP_AXI_RESET, struct msm_vfe_axi_reset_cmd) 946 #define VIDIOC_MSM_ISP_AXI_RESTART _IOWR('V', MSM_ISP_AXI_RESTART, struct msm_vfe_axi_restart_cmd) 947 #define VIDIOC_MSM_ISP_FETCH_ENG_START _IOWR('V', MSM_ISP_FETCH_ENG_START, struct msm_vfe_fetch_eng_start) 948 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 949 #define VIDIOC_MSM_ISP_DEQUEUE_BUF _IOWR('V', MSM_ISP_DEQUEUE_BUF, struct msm_isp_qbuf_info) 950 #define VIDIOC_MSM_ISP_SET_DUAL_HW_MASTER_SLAVE _IOWR('V', MSM_ISP_SET_DUAL_HW_MASTER_SLAVE, struct msm_isp_set_dual_hw_ms_cmd) 951 #define VIDIOC_MSM_ISP_MAP_BUF_START_FE _IOWR('V', MSM_ISP_MAP_BUF_START_FE, struct msm_vfe_fetch_eng_start) 952 #define VIDIOC_MSM_ISP_UNMAP_BUF _IOWR('V', MSM_ISP_UNMAP_BUF, struct msm_isp_unmap_buf_req) 953 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 954 #define VIDIOC_MSM_ISP_AHB_CLK_CFG _IOWR('V', MSM_ISP_AHB_CLK_CFG, struct msm_isp_ahb_clk_cfg) 955 #define VIDIOC_MSM_ISP_DUAL_HW_MASTER_SLAVE_SYNC _IOWR('V', MSM_ISP_DUAL_HW_MASTER_SLAVE_SYNC, struct msm_isp_dual_hw_master_slave_sync) 956 #define VIDIOC_MSM_ISP_FETCH_ENG_MULTI_PASS_START _IOWR('V', MSM_ISP_FETCH_ENG_MULTI_PASS_START, struct msm_vfe_fetch_eng_multi_pass_start) 957 #define VIDIOC_MSM_ISP_MAP_BUF_START_MULTI_PASS_FE _IOWR('V', MSM_ISP_MAP_BUF_START_MULTI_PASS_FE, struct msm_vfe_fetch_eng_multi_pass_start) 958 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 959 #define VIDIOC_MSM_ISP_REQUEST_BUF_VER2 _IOWR('V', MSM_ISP_REQUEST_BUF_VER2, struct msm_isp_buf_request_ver2) 960 #define VIDIOC_MSM_ISP_DUAL_HW_LPM_MODE _IOWR('V', MSM_ISP_DUAL_HW_LPM_MODE, struct msm_vfe_dual_lpm_mode) 961 #endif 962 963
