1 //==-- llvm/CodeGen/GlobalISel/InstructionSelector.h -------------*- C++ -*-==// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 /// \file This file declares the API for the instruction selector. 11 /// This class is responsible for selecting machine instructions. 12 /// It's implemented by the target. It's used by the InstructionSelect pass. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #ifndef LLVM_CODEGEN_GLOBALISEL_INSTRUCTIONSELECTOR_H 17 #define LLVM_CODEGEN_GLOBALISEL_INSTRUCTIONSELECTOR_H 18 19 #include "llvm/ADT/Optional.h" 20 #include <cstdint> 21 22 namespace llvm { 23 class MachineInstr; 24 class MachineOperand; 25 class MachineRegisterInfo; 26 class RegisterBankInfo; 27 class TargetInstrInfo; 28 class TargetRegisterInfo; 29 30 /// Provides the logic to select generic machine instructions. 31 class InstructionSelector { 32 public: 33 virtual ~InstructionSelector() {} 34 35 /// Select the (possibly generic) instruction \p I to only use target-specific 36 /// opcodes. It is OK to insert multiple instructions, but they cannot be 37 /// generic pre-isel instructions. 38 /// 39 /// \returns whether selection succeeded. 40 /// \pre I.getParent() && I.getParent()->getParent() 41 /// \post 42 /// if returns true: 43 /// for I in all mutated/inserted instructions: 44 /// !isPreISelGenericOpcode(I.getOpcode()) 45 /// 46 virtual bool select(MachineInstr &I) const = 0; 47 48 protected: 49 InstructionSelector(); 50 51 /// Mutate the newly-selected instruction \p I to constrain its (possibly 52 /// generic) virtual register operands to the instruction's register class. 53 /// This could involve inserting COPYs before (for uses) or after (for defs). 54 /// This requires the number of operands to match the instruction description. 55 /// \returns whether operand regclass constraining succeeded. 56 /// 57 // FIXME: Not all instructions have the same number of operands. We should 58 // probably expose a constrain helper per operand and let the target selector 59 // constrain individual registers, like fast-isel. 60 bool constrainSelectedInstRegOperands(MachineInstr &I, 61 const TargetInstrInfo &TII, 62 const TargetRegisterInfo &TRI, 63 const RegisterBankInfo &RBI) const; 64 65 Optional<int64_t> getConstantVRegVal(unsigned VReg, 66 const MachineRegisterInfo &MRI) const; 67 68 bool isOperandImmEqual(const MachineOperand &MO, int64_t Value, 69 const MachineRegisterInfo &MRI) const; 70 71 bool isObviouslySafeToFold(MachineInstr &MI) const; 72 }; 73 74 } // End namespace llvm. 75 76 #endif 77
