1 @ LDC group relocation tests. 2 3 .text 4 5 @ LDC/LDCL/LDC2/LDC2L/STC/STCL/STC2/STC2L 6 7 .macro ldctest load store 8 9 \load 0, c0, [r0, #:pc_g0:(f + 0x214)] 10 \load 0, c0, [r0, #:pc_g1:(f + 0x214)] 11 \load 0, c0, [r0, #:pc_g2:(f + 0x214)] 12 13 \load 0, c0, [r0, #:sb_g0:(f + 0x214)] 14 \load 0, c0, [r0, #:sb_g1:(f + 0x214)] 15 \load 0, c0, [r0, #:sb_g2:(f + 0x214)] 16 17 \store 0, c0, [r0, #:pc_g0:(f + 0x214)] 18 \store 0, c0, [r0, #:pc_g1:(f + 0x214)] 19 \store 0, c0, [r0, #:pc_g2:(f + 0x214)] 20 21 \store 0, c0, [r0, #:sb_g0:(f + 0x214)] 22 \store 0, c0, [r0, #:sb_g1:(f + 0x214)] 23 \store 0, c0, [r0, #:sb_g2:(f + 0x214)] 24 25 \load 0, c0, [r0, #:pc_g0:(f - 0x214)] 26 \load 0, c0, [r0, #:pc_g1:(f - 0x214)] 27 \load 0, c0, [r0, #:pc_g2:(f - 0x214)] 28 29 \load 0, c0, [r0, #:sb_g0:(f - 0x214)] 30 \load 0, c0, [r0, #:sb_g1:(f - 0x214)] 31 \load 0, c0, [r0, #:sb_g2:(f - 0x214)] 32 33 \store 0, c0, [r0, #:pc_g0:(f - 0x214)] 34 \store 0, c0, [r0, #:pc_g1:(f - 0x214)] 35 \store 0, c0, [r0, #:pc_g2:(f - 0x214)] 36 37 \store 0, c0, [r0, #:sb_g0:(f - 0x214)] 38 \store 0, c0, [r0, #:sb_g1:(f - 0x214)] 39 \store 0, c0, [r0, #:sb_g2:(f - 0x214)] 40 41 .endm 42 43 ldctest ldc stc 44 ldctest ldcl stcl 45 ldctest ldc2 stc2 46 ldctest ldc2l stc2l 47 48 @ LDFS/STFS/LDFD/STFD/LDFE/STFE/LDFP/STFP 49 50 .fpu fpa 51 52 .macro fpa_test load store 53 54 \load f0, [r0, #:pc_g0:(f + 0x214)] 55 \load f0, [r0, #:pc_g1:(f + 0x214)] 56 \load f0, [r0, #:pc_g2:(f + 0x214)] 57 58 \load f0, [r0, #:sb_g0:(f + 0x214)] 59 \load f0, [r0, #:sb_g1:(f + 0x214)] 60 \load f0, [r0, #:sb_g2:(f + 0x214)] 61 62 \store f0, [r0, #:pc_g0:(f + 0x214)] 63 \store f0, [r0, #:pc_g1:(f + 0x214)] 64 \store f0, [r0, #:pc_g2:(f + 0x214)] 65 66 \store f0, [r0, #:sb_g0:(f + 0x214)] 67 \store f0, [r0, #:sb_g1:(f + 0x214)] 68 \store f0, [r0, #:sb_g2:(f + 0x214)] 69 70 \load f0, [r0, #:pc_g0:(f - 0x214)] 71 \load f0, [r0, #:pc_g1:(f - 0x214)] 72 \load f0, [r0, #:pc_g2:(f - 0x214)] 73 74 \load f0, [r0, #:sb_g0:(f - 0x214)] 75 \load f0, [r0, #:sb_g1:(f - 0x214)] 76 \load f0, [r0, #:sb_g2:(f - 0x214)] 77 78 \store f0, [r0, #:pc_g0:(f - 0x214)] 79 \store f0, [r0, #:pc_g1:(f - 0x214)] 80 \store f0, [r0, #:pc_g2:(f - 0x214)] 81 82 \store f0, [r0, #:sb_g0:(f - 0x214)] 83 \store f0, [r0, #:sb_g1:(f - 0x214)] 84 \store f0, [r0, #:sb_g2:(f - 0x214)] 85 86 .endm 87 88 fpa_test ldfs stfs 89 fpa_test ldfd stfd 90 fpa_test ldfe stfe 91 fpa_test ldfp stfp 92 93 @ FLDS/FSTS 94 95 .fpu vfp 96 97 .macro vfp_test load store reg 98 99 \load \reg, [r0, #:pc_g0:(f + 0x214)] 100 \load \reg, [r0, #:pc_g1:(f + 0x214)] 101 \load \reg, [r0, #:pc_g2:(f + 0x214)] 102 103 \load \reg, [r0, #:sb_g0:(f + 0x214)] 104 \load \reg, [r0, #:sb_g1:(f + 0x214)] 105 \load \reg, [r0, #:sb_g2:(f + 0x214)] 106 107 \store \reg, [r0, #:pc_g0:(f + 0x214)] 108 \store \reg, [r0, #:pc_g1:(f + 0x214)] 109 \store \reg, [r0, #:pc_g2:(f + 0x214)] 110 111 \store \reg, [r0, #:sb_g0:(f + 0x214)] 112 \store \reg, [r0, #:sb_g1:(f + 0x214)] 113 \store \reg, [r0, #:sb_g2:(f + 0x214)] 114 115 \load \reg, [r0, #:pc_g0:(f - 0x214)] 116 \load \reg, [r0, #:pc_g1:(f - 0x214)] 117 \load \reg, [r0, #:pc_g2:(f - 0x214)] 118 119 \load \reg, [r0, #:sb_g0:(f - 0x214)] 120 \load \reg, [r0, #:sb_g1:(f - 0x214)] 121 \load \reg, [r0, #:sb_g2:(f - 0x214)] 122 123 \store \reg, [r0, #:pc_g0:(f - 0x214)] 124 \store \reg, [r0, #:pc_g1:(f - 0x214)] 125 \store \reg, [r0, #:pc_g2:(f - 0x214)] 126 127 \store \reg, [r0, #:sb_g0:(f - 0x214)] 128 \store \reg, [r0, #:sb_g1:(f - 0x214)] 129 \store \reg, [r0, #:sb_g2:(f - 0x214)] 130 131 .endm 132 133 vfp_test flds fsts s0 134 135 @ FLDD/FSTD 136 137 vfp_test fldd fstd d0 138 139 @ VLDR/VSTR 140 141 vfp_test vldr vstr d0 142 143 @ CFLDRS/CFLDRD/CFLDR32/CFLDR64/CFSTRS/CFSTRD/CFSTR32/CFSTR64 144 145 .cpu ep9312 146 147 vfp_test cfldrs cfstrs mvf0 148 vfp_test cfldrd cfstrd mvd0 149 vfp_test cfldr32 cfstr32 mvfx0 150 vfp_test cfldr64 cfstr64 mvdx0 151 152
