1 /* i370-opc.c -- Instruction 370 (ESA/390) architecture opcode list 2 Copyright (C) 1994-2016 Free Software Foundation, Inc. 3 PowerPC version written by Ian Lance Taylor, Cygnus Support 4 Rewritten for i370 ESA/390 support by Linas Vepstas <linas (at) linas.org> 1998, 1999 5 6 This file is part of the GNU opcodes library. 7 8 This library is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3, or (at your option) 11 any later version. 12 13 It is distributed in the hope that it will be useful, but WITHOUT 14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 16 License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this file; see the file COPYING. If not, write to the Free 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 21 02110-1301, USA. */ 22 23 #include "sysdep.h" 24 #include <stdio.h> 25 #include "opcode/i370.h" 26 27 /* This file holds the i370 opcode table. The opcode table 28 includes almost all of the extended instruction mnemonics. This 29 permits the disassembler to use them, and simplifies the assembler 30 logic, at the cost of increasing the table size. The table is 31 strictly constant data, so the compiler should be able to put it in 32 the .text section. 33 34 This file also holds the operand table. All knowledge about 35 inserting operands into instructions and vice-versa is kept in this 36 file. */ 37 38 /* The functions used to insert and extract complicated operands. */ 40 41 static i370_insn_t 42 insert_ss_b2 (i370_insn_t insn, long value, 43 const char **errmsg ATTRIBUTE_UNUSED) 44 { 45 insn.i[1] |= (value & 0xf) << 28; 46 return insn; 47 } 48 49 static i370_insn_t 50 insert_ss_d2 (i370_insn_t insn, long value, 51 const char **errmsg ATTRIBUTE_UNUSED) 52 { 53 insn.i[1] |= (value & 0xfff) << 16; 54 return insn; 55 } 56 57 static i370_insn_t 58 insert_rxf_r3 (i370_insn_t insn, long value, 59 const char **errmsg ATTRIBUTE_UNUSED) 60 { 61 insn.i[1] |= (value & 0xf) << 28; 62 return insn; 63 } 64 65 static long 66 extract_ss_b2 (i370_insn_t insn, int *invalid ATTRIBUTE_UNUSED) 67 { 68 return (insn.i[1] >>28) & 0xf; 69 } 70 71 static long 72 extract_ss_d2 (i370_insn_t insn, int *invalid ATTRIBUTE_UNUSED) 73 { 74 return (insn.i[1] >>16) & 0xfff; 75 } 76 77 static long 78 extract_rxf_r3 (i370_insn_t insn, int *invalid ATTRIBUTE_UNUSED) 79 { 80 return (insn.i[1] >>28) & 0xf; 81 } 82 83 /* The operands table. 85 The fields are bits, shift, insert, extract, flags, name. 86 The types: 87 I370_OPERAND_GPR register, must name a register, must be present 88 I370_OPERAND_RELATIVE displacement or legnth field, must be present 89 I370_OPERAND_BASE base register; if present, must name a register 90 if absent, should take value of zero 91 I370_OPERAND_INDEX index register; if present, must name a register 92 if absent, should take value of zero 93 I370_OPERAND_OPTIONAL other optional operand (usuall reg?). */ 94 95 const struct i370_operand i370_operands[] = 96 { 97 /* The zero index is used to indicate the end of the list of 98 operands. */ 99 #define UNUSED 0 100 { 0, 0, 0, 0, 0, "unused" }, 101 102 /* The R1 register field in an RR form instruction. */ 103 #define RR_R1 (UNUSED + 1) 104 #define RR_R1_MASK (0xf << 4) 105 { 4, 4, 0, 0, I370_OPERAND_GPR, "RR R1" }, 106 107 /* The R2 register field in an RR form instruction. */ 108 #define RR_R2 (RR_R1 + 1) 109 #define RR_R2_MASK (0xf) 110 { 4, 0, 0, 0, I370_OPERAND_GPR, "RR R2" }, 111 112 /* The I field in an RR form SVC-style instruction. */ 113 #define RR_I (RR_R2 + 1) 114 #define RR_I_MASK (0xff) 115 { 8, 0, 0, 0, I370_OPERAND_RELATIVE, "RR I (svc)" }, 116 117 /* The R1 register field in an RRE form instruction. */ 118 #define RRE_R1 (RR_I + 1) 119 #define RRE_R1_MASK (0xf << 4) 120 { 4, 4, 0, 0, I370_OPERAND_GPR, "RRE R1" }, 121 122 /* The R2 register field in an RRE form instruction. */ 123 #define RRE_R2 (RRE_R1 + 1) 124 #define RRE_R2_MASK (0xf) 125 { 4, 0, 0, 0, I370_OPERAND_GPR, "RRE R2" }, 126 127 /* The R1 register field in an RRF form instruction. */ 128 #define RRF_R1 (RRE_R2 + 1) 129 #define RRF_R1_MASK (0xf << 4) 130 { 4, 4, 0, 0, I370_OPERAND_GPR, "RRF R1" }, 131 132 /* The R2 register field in an RRF form instruction. */ 133 #define RRF_R2 (RRF_R1 + 1) 134 #define RRF_R2_MASK (0xf) 135 { 4, 0, 0, 0, I370_OPERAND_GPR, "RRF R2" }, 136 137 /* The R3 register field in an RRF form instruction. */ 138 #define RRF_R3 (RRF_R2 + 1) 139 #define RRF_R3_MASK (0xf << 12) 140 { 4, 12, 0, 0, I370_OPERAND_GPR, "RRF R3" }, 141 142 /* The R1 register field in an RX or RS form instruction. */ 143 #define RX_R1 (RRF_R3 + 1) 144 #define RX_R1_MASK (0xf << 20) 145 { 4, 20, 0, 0, I370_OPERAND_GPR, "RX R1" }, 146 147 /* The X2 index field in an RX form instruction. */ 148 #define RX_X2 (RX_R1 + 1) 149 #define RX_X2_MASK (0xf << 16) 150 { 4, 16, 0, 0, I370_OPERAND_GPR | I370_OPERAND_INDEX, "RX X2"}, 151 152 /* The B2 base field in an RX form instruction. */ 153 #define RX_B2 (RX_X2 + 1) 154 #define RX_B2_MASK (0xf << 12) 155 { 4, 12, 0, 0, I370_OPERAND_GPR | I370_OPERAND_BASE, "RX B2"}, 156 157 /* The D2 displacement field in an RX form instruction. */ 158 #define RX_D2 (RX_B2 + 1) 159 #define RX_D2_MASK (0xfff) 160 { 12, 0, 0, 0, I370_OPERAND_RELATIVE, "RX D2"}, 161 162 /* The R3 register field in an RXF form instruction. */ 163 #define RXF_R3 (RX_D2 + 1) 164 #define RXF_R3_MASK (0xf << 12) 165 { 4, 12, insert_rxf_r3, extract_rxf_r3, I370_OPERAND_GPR, "RXF R3" }, 166 167 /* The D2 displacement field in an RS form instruction. */ 168 #define RS_D2 (RXF_R3 + 1) 169 #define RS_D2_MASK (0xfff) 170 { 12, 0, 0, 0, I370_OPERAND_RELATIVE, "RS D2"}, 171 172 /* The R3 register field in an RS form instruction. */ 173 #define RS_R3 (RS_D2 + 1) 174 #define RS_R3_MASK (0xf << 16) 175 { 4, 16, 0, 0, I370_OPERAND_GPR, "RS R3" }, 176 177 /* The B2 base field in an RS form instruction. */ 178 #define RS_B2 (RS_R3 + 1) 179 #define RS_B2_MASK (0xf << 12) 180 { 4, 12, 0, 0, I370_OPERAND_GPR | I370_OPERAND_BASE | I370_OPERAND_SBASE, "RS B2"}, 181 182 /* The optional B2 base field in an RS form instruction. */ 183 /* Note that this field will almost always be absent */ 184 #define RS_B2_OPT (RS_B2 + 1) 185 #define RS_B2_OPT_MASK (0xf << 12) 186 { 4, 12, 0, 0, I370_OPERAND_GPR | I370_OPERAND_OPTIONAL, "RS B2 OPT"}, 187 188 /* The R1 register field in an RSI form instruction. */ 189 #define RSI_R1 (RS_B2_OPT + 1) 190 #define RSI_R1_MASK (0xf << 20) 191 { 4, 20, 0, 0, I370_OPERAND_GPR, "RSI R1" }, 192 193 /* The R3 register field in an RSI form instruction. */ 194 #define RSI_R3 (RSI_R1 + 1) 195 #define RSI_R3_MASK (0xf << 16) 196 { 4, 16, 0, 0, I370_OPERAND_GPR, "RSI R3" }, 197 198 /* The I2 immediate field in an RSI form instruction. */ 199 #define RSI_I2 (RSI_R3 + 1) 200 #define RSI_I2_MASK (0xffff) 201 { 16, 0, 0, 0, I370_OPERAND_RELATIVE, "RSI I2" }, 202 203 /* The R1 register field in an RI form instruction. */ 204 #define RI_R1 (RSI_I2 + 1) 205 #define RI_R1_MASK (0xf << 20) 206 { 4, 20, 0, 0, I370_OPERAND_GPR, "RI R1" }, 207 208 /* The I2 immediate field in an RI form instruction. */ 209 #define RI_I2 (RI_R1 + 1) 210 #define RI_I2_MASK (0xffff) 211 { 16, 0, 0, 0, I370_OPERAND_RELATIVE, "RI I2" }, 212 213 /* The I2 index field in an SI form instruction. */ 214 #define SI_I2 (RI_I2 + 1) 215 #define SI_I2_MASK (0xff << 16) 216 { 8, 16, 0, 0, I370_OPERAND_RELATIVE, "SI I2"}, 217 218 /* The B1 base register field in an SI form instruction. */ 219 #define SI_B1 (SI_I2 + 1) 220 #define SI_B1_MASK (0xf << 12) 221 { 4, 12, 0, 0, I370_OPERAND_GPR, "SI B1" }, 222 223 /* The D1 displacement field in an SI form instruction. */ 224 #define SI_D1 (SI_B1 + 1) 225 #define SI_D1_MASK (0xfff) 226 { 12, 0, 0, 0, I370_OPERAND_RELATIVE, "SI D1" }, 227 228 /* The B2 base register field in an S form instruction. */ 229 #define S_B2 (SI_D1 + 1) 230 #define S_B2_MASK (0xf << 12) 231 { 4, 12, 0, 0, I370_OPERAND_GPR | I370_OPERAND_BASE | I370_OPERAND_SBASE, "S B2" }, 232 233 /* The D2 displacement field in an S form instruction. */ 234 #define S_D2 (S_B2 + 1) 235 #define S_D2_MASK (0xfff) 236 { 12, 0, 0, 0, I370_OPERAND_RELATIVE, "S D2" }, 237 238 /* The L length field in an SS form instruction. */ 239 #define SS_L (S_D2 + 1) 240 #define SS_L_MASK (0xffff<<16) 241 { 8, 16, 0, 0, I370_OPERAND_RELATIVE | I370_OPERAND_LENGTH, "SS L" }, 242 243 /* The B1 base register field in an SS form instruction. */ 244 #define SS_B1 (SS_L + 1) 245 #define SS_B1_MASK (0xf << 12) 246 { 4, 12, 0, 0, I370_OPERAND_GPR, "SS B1" }, 247 248 /* The D1 displacement field in an SS form instruction. */ 249 #define SS_D1 (SS_B1 + 1) 250 #define SS_D1_MASK (0xfff) 251 { 12, 0, 0, 0, I370_OPERAND_RELATIVE, "SS D1" }, 252 253 /* The B2 base register field in an SS form instruction. */ 254 #define SS_B2 (SS_D1 + 1) 255 #define SS_B2_MASK (0xf << 12) 256 { 4, 12, insert_ss_b2, extract_ss_b2, I370_OPERAND_GPR | I370_OPERAND_BASE | I370_OPERAND_SBASE, "SS B2" }, 257 258 /* The D2 displacement field in an SS form instruction. */ 259 #define SS_D2 (SS_B2 + 1) 260 #define SS_D2_MASK (0xfff) 261 { 12, 0, insert_ss_d2, extract_ss_d2, I370_OPERAND_RELATIVE, "SS D2" }, 262 263 }; 264 265 266 /* Macros used to form opcodes. */ 268 269 /* The short-instruction opcode. */ 270 #define OPS(x) ((((unsigned short) (x)) & 0xff) << 8) 271 #define OPS_MASK OPS (0xff) 272 273 /* the extended instruction opcode */ 274 #define XOPS(x) ((((unsigned short) (x)) & 0xff) << 24) 275 #define XOPS_MASK XOPS (0xff) 276 277 /* the S instruction opcode */ 278 #define SOPS(x) ((((unsigned short) (x)) & 0xffff) << 16) 279 #define SOPS_MASK SOPS (0xffff) 280 281 /* the E instruction opcode */ 282 #define EOPS(x) (((unsigned short) (x)) & 0xffff) 283 #define EOPS_MASK EOPS (0xffff) 284 285 /* the RI instruction opcode */ 286 #define ROPS(x) (((((unsigned short) (x)) & 0xff0) << 20) | \ 287 ((((unsigned short) (x)) & 0x00f) << 16)) 288 #define ROPS_MASK ROPS (0xfff) 289 290 291 /* An E form instruction. */ 293 #define E(op) (EOPS (op)) 294 #define E_MASK E (0xffff) 295 296 /* An RR form instruction. */ 297 #define RR(op, r1, r2) \ 298 (OPS (op) | ((((unsigned short) (r1)) & 0xf) << 4) | \ 299 ((((unsigned short) (r2)) & 0xf) )) 300 301 #define RR_MASK RR (0xff, 0x0, 0x0) 302 303 /* An SVC-style instruction. */ 304 #define SVC(op, i) \ 305 (OPS (op) | (((unsigned short) (i)) & 0xff)) 306 307 #define SVC_MASK SVC (0xff, 0x0) 308 309 /* An RRE form instruction. */ 310 #define RRE(op, r1, r2) \ 311 (SOPS (op) | ((((unsigned short) (r1)) & 0xf) << 4) | \ 312 ((((unsigned short) (r2)) & 0xf) )) 313 314 #define RRE_MASK RRE (0xffff, 0x0, 0x0) 315 316 /* An RRF form instruction. */ 317 #define RRF(op, r3, r1, r2) \ 318 (SOPS (op) | ((((unsigned short) (r3)) & 0xf) << 12) | \ 319 ((((unsigned short) (r1)) & 0xf) << 4) | \ 320 ((((unsigned short) (r2)) & 0xf) )) 321 322 #define RRF_MASK RRF (0xffff, 0x0, 0x0, 0x0) 323 324 /* An RX form instruction. */ 325 #define RX(op, r1, x2, b2, d2) \ 326 (XOPS(op) | ((((unsigned short) (r1)) & 0xf) << 20) | \ 327 ((((unsigned short) (x2)) & 0xf) << 16) | \ 328 ((((unsigned short) (b2)) & 0xf) << 12) | \ 329 ((((unsigned short) (d2)) & 0xfff))) 330 331 #define RX_MASK RX (0xff, 0x0, 0x0, 0x0, 0x0) 332 333 /* An RXE form instruction high word. */ 334 #define RXEH(op, r1, x2, b2, d2) \ 335 (XOPS(op) | ((((unsigned short) (r1)) & 0xf) << 20) | \ 336 ((((unsigned short) (x2)) & 0xf) << 16) | \ 337 ((((unsigned short) (b2)) & 0xf) << 12) | \ 338 ((((unsigned short) (d2)) & 0xfff))) 339 340 #define RXEH_MASK RXEH (0xff, 0, 0, 0, 0) 341 342 /* An RXE form instruction low word. */ 343 #define RXEL(op) \ 344 ((((unsigned short) (op)) & 0xff) << 16 ) 345 346 #define RXEL_MASK RXEL (0xff) 347 348 /* An RXF form instruction high word. */ 349 #define RXFH(op, r1, x2, b2, d2) \ 350 (XOPS(op) | ((((unsigned short) (r1)) & 0xf) << 20) | \ 351 ((((unsigned short) (x2)) & 0xf) << 16) | \ 352 ((((unsigned short) (b2)) & 0xf) << 12) | \ 353 ((((unsigned short) (d2)) & 0xfff))) 354 355 #define RXFH_MASK RXFH (0xff, 0, 0, 0, 0) 356 357 /* An RXF form instruction low word. */ 358 #define RXFL(op, r3) \ 359 (((((unsigned short) (r3)) & 0xf) << 28 ) | \ 360 ((((unsigned short) (op)) & 0xff) << 16 )) 361 362 #define RXFL_MASK RXFL (0xff, 0) 363 364 /* An RS form instruction. */ 365 #define RS(op, r1, b3, b2, d2) \ 366 (XOPS(op) | ((((unsigned short) (r1)) & 0xf) << 20) | \ 367 ((((unsigned short) (b3)) & 0xf) << 16) | \ 368 ((((unsigned short) (b2)) & 0xf) << 12) | \ 369 ((((unsigned short) (d2)) & 0xfff))) 370 371 #define RS_MASK RS (0xff, 0x0, 0x0, 0x0, 0x0) 372 373 /* An RSI form instruction. */ 374 #define RSI(op, r1, r3, i2) \ 375 (XOPS(op) | ((((unsigned short) (r1)) & 0xf) << 20) | \ 376 ((((unsigned short) (r3)) & 0xf) << 16) | \ 377 ((((unsigned short) (i2)) & 0xffff))) 378 379 #define RSI_MASK RSI (0xff, 0x0, 0x0, 0x0) 380 381 /* An RI form instruction. */ 382 #define RI(op, r1, i2) \ 383 (ROPS(op) | ((((unsigned short) (r1)) & 0xf) << 20) | \ 384 ((((unsigned short) (i2)) & 0xffff))) 385 386 #define RI_MASK RI (0xfff, 0x0, 0x0) 387 388 /* An SI form instruction. */ 389 #define SI(op, i2, b1, d1) \ 390 (XOPS(op) | ((((unsigned short) (i2)) & 0xff) << 16) | \ 391 ((((unsigned short) (b1)) & 0xf) << 12) | \ 392 ((((unsigned short) (d1)) & 0xfff))) 393 394 #define SI_MASK SI (0xff, 0x0, 0x0, 0x0) 395 396 /* An S form instruction. */ 397 #define S(op, b2, d2) \ 398 (SOPS(op) | ((((unsigned short)(b2)) & 0xf) << 12) | \ 399 ((((unsigned short)(d2)) & 0xfff))) 400 401 #define S_MASK S (0xffff, 0x0, 0x0) 402 403 /* An SS form instruction high word. */ 404 #define SSH(op, l, b1, d1) \ 405 (XOPS(op) | ((((unsigned short) (l)) & 0xff) << 16) | \ 406 ((((unsigned short) (b1)) & 0xf) << 12) | \ 407 ((((unsigned short) (d1)) & 0xfff))) 408 409 /* An SS form instruction low word. */ 410 #define SSL(b2, d2) \ 411 ( ((((unsigned short) (b1)) & 0xf) << 28) | \ 412 ((((unsigned short) (d1)) & 0xfff) << 16 )) 413 414 #define SS_MASK SSH (0xff, 0x0, 0x0, 0x0) 415 416 /* An SSE form instruction high word. */ 417 #define SSEH(op, b1, d1) \ 418 (SOPS(op) | ((((unsigned short) (b1)) & 0xf) << 12) | \ 419 ((((unsigned short) (d1)) & 0xfff))) 420 421 /* An SSE form instruction low word. */ 422 #define SSEL(b2, d2) \ 423 ( ((((unsigned short) (b1)) & 0xf) << 28) | \ 424 ((((unsigned short) (d1)) & 0xfff) << 16 )) 425 426 #define SSE_MASK SSEH (0xffff, 0x0, 0x0) 427 428 429 /* Smaller names for the flags so each entry in the opcodes table will 431 fit on a single line. These flags are set up so that e.g. IXA means 432 the insn is supported on the 370/XA or newer architecture. 433 Note that 370 or older obsolete insn's are not supported ... */ 434 #define IBF I370_OPCODE_ESA390_BF 435 #define IBS I370_OPCODE_ESA390_BS 436 #define ICK I370_OPCODE_ESA390_CK 437 #define ICM I370_OPCODE_ESA390_CM 438 #define IFX I370_OPCODE_ESA390_FX 439 #define IHX I370_OPCODE_ESA390_HX 440 #define IIR I370_OPCODE_ESA390_IR 441 #define IMI I370_OPCODE_ESA390_MI 442 #define IPC I370_OPCODE_ESA390_PC 443 #define IPL I370_OPCODE_ESA390_PL 444 #define IQR I370_OPCODE_ESA390_QR 445 #define IRP I370_OPCODE_ESA390_RP 446 #define ISA I370_OPCODE_ESA390_SA 447 #define ISG I370_OPCODE_ESA390_SG 448 #define ISR I370_OPCODE_ESA390_SR 449 #define ITR I370_OPCODE_ESA390_SR 450 #define I390 IBF | IBS | ICK | ICM | IIR | IFX | IHX | IMI | IPC | IPL | IQR | IRP | ISA | ISG | ISR | ITR | I370_OPCODE_ESA390 451 #define IESA I390 | I370_OPCODE_ESA370 452 #define IXA IESA | I370_OPCODE_370_XA 453 #define I370 IXA | I370_OPCODE_370 454 #define I360 I370 | I370_OPCODE_360 455 456 457 /* The opcode table. 459 460 The format of the opcode table is: 461 462 NAME LEN OPCODE_HI OPCODE_LO MASK_HI MASK_LO FLAGS { OPERANDS } 463 464 NAME is the name of the instruction. 465 OPCODE is the instruction opcode. 466 MASK is the opcode mask; this is used to tell the disassembler 467 which bits in the actual opcode must match OPCODE. 468 FLAGS are flags indicated what processors support the instruction. 469 OPERANDS is the list of operands. 470 471 The disassembler reads the table in order and prints the first 472 instruction which matches, so this table is sorted to put more 473 specific instructions before more general instructions. It is also 474 sorted by major opcode. */ 475 476 const struct i370_opcode i370_opcodes[] = 477 { 478 /* E form instructions */ 479 { "pr", 2, {{E(0x0101), 0}}, {{E_MASK, 0}}, IESA, {0} }, 480 481 { "trap2", 2, {{E(0x01FF), 0}}, {{E_MASK, 0}}, ITR, {0} }, 482 { "upt", 2, {{E(0x0102), 0}}, {{E_MASK, 0}}, IXA, {0} }, 483 484 /* RR form instructions */ 485 { "ar", 2, {{RR(0x1a,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, 486 { "adr", 2, {{RR(0x2a,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, 487 { "aer", 2, {{RR(0x3a,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, 488 { "alr", 2, {{RR(0x1e,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, 489 { "aur", 2, {{RR(0x2e,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, 490 { "awr", 2, {{RR(0x3e,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, 491 { "axr", 2, {{RR(0x36,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, 492 { "balr", 2, {{RR(0x05,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, 493 { "basr", 2, {{RR(0x0d,0,0), 0}}, {{RR_MASK, 0}}, IXA, {RR_R1, RR_R2} }, 494 { "bassm", 2, {{RR(0x0c,0,0), 0}}, {{RR_MASK, 0}}, IXA, {RR_R1, RR_R2} }, 495 { "bsm", 2, {{RR(0x0b,0,0), 0}}, {{RR_MASK, 0}}, IXA, {RR_R1, RR_R2} }, 496 { "bcr", 2, {{RR(0x07,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, 497 { "bctr", 2, {{RR(0x06,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, 498 { "cdr", 2, {{RR(0x29,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, 499 { "cer", 2, {{RR(0x39,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, 500 { "clr", 2, {{RR(0x15,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, 501 { "clcl", 2, {{RR(0x0f,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, 502 { "cr", 2, {{RR(0x19,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, 503 { "ddr", 2, {{RR(0x2d,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, 504 { "der", 2, {{RR(0x3d,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, 505 { "dr", 2, {{RR(0x1d,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, 506 { "hdr", 2, {{RR(0x24,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, 507 { "her", 2, {{RR(0x34,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, 508 { "lcdr", 2, {{RR(0x23,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, 509 { "lcer", 2, {{RR(0x33,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, 510 { "lcr", 2, {{RR(0x13,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, 511 { "ldr", 2, {{RR(0x28,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, 512 { "ler", 2, {{RR(0x38,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, 513 { "lndr", 2, {{RR(0x21,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, 514 { "lner", 2, {{RR(0x31,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, 515 { "lnr", 2, {{RR(0x11,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, 516 { "lpdr", 2, {{RR(0x20,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, 517 { "lper", 2, {{RR(0x30,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, 518 { "lpr", 2, {{RR(0x10,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, 519 { "lr", 2, {{RR(0x18,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, 520 { "lrdr", 2, {{RR(0x25,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, 521 { "lrer", 2, {{RR(0x35,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, 522 { "ltdr", 2, {{RR(0x22,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, 523 { "lter", 2, {{RR(0x32,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, 524 { "ltr", 2, {{RR(0x12,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, 525 { "mdr", 2, {{RR(0x2c,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, 526 { "mer", 2, {{RR(0x3c,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, 527 { "mr", 2, {{RR(0x1c,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, 528 { "mvcl", 2, {{RR(0x0e,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, 529 { "mxdr", 2, {{RR(0x27,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, 530 { "mxr", 2, {{RR(0x26,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, 531 { "nr", 2, {{RR(0x14,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, 532 { "or", 2, {{RR(0x16,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, 533 { "sdr", 2, {{RR(0x2b,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, 534 { "ser", 2, {{RR(0x3b,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, 535 { "slr", 2, {{RR(0x1f,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, 536 { "spm", 2, {{RR(0x04,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1} }, 537 { "sr", 2, {{RR(0x1b,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, 538 { "sur", 2, {{RR(0x3f,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, 539 { "swr", 2, {{RR(0x2f,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, 540 { "sxr", 2, {{RR(0x37,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, 541 { "xr", 2, {{RR(0x17,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, 542 543 /* Unusual RR formats. */ 544 { "svc", 2, {{SVC(0x0a,0), 0}}, {{SVC_MASK, 0}}, I370, {RR_I} }, 545 546 /* RRE form instructions. */ 547 { "adbr", 4, {{RRE(0xb31a,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, 548 { "aebr", 4, {{RRE(0xb30a,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, 549 { "axbr", 4, {{RRE(0xb34a,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, 550 { "bakr", 4, {{RRE(0xb240,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} }, 551 { "bsa", 4, {{RRE(0xb25a,0,0), 0}}, {{RRE_MASK, 0}}, IBS, {RRE_R1, RRE_R2} }, 552 { "bsg", 4, {{RRE(0xb258,0,0), 0}}, {{RRE_MASK, 0}}, ISG, {RRE_R1, RRE_R2} }, 553 { "cdbr", 4, {{RRE(0xb319,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, 554 { "cdfbr", 4, {{RRE(0xb395,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, 555 { "cdfr", 4, {{RRE(0xb3b5,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} }, 556 { "cebr", 4, {{RRE(0xb309,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, 557 { "cefbr", 4, {{RRE(0xb394,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, 558 { "cefr", 4, {{RRE(0xb3b4,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} }, 559 { "cksm", 4, {{RRE(0xb241,0,0), 0}}, {{RRE_MASK, 0}}, ICK, {RRE_R1, RRE_R2} }, 560 { "clst", 4, {{RRE(0xb25d,0,0), 0}}, {{RRE_MASK, 0}}, ISR, {RRE_R1, RRE_R2} }, 561 { "cpya", 4, {{RRE(0xb24d,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} }, 562 { "cuse", 4, {{RRE(0xb257,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} }, 563 { "cxbr", 4, {{RRE(0xb349,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, 564 { "cxfbr", 4, {{RRE(0xb396,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, 565 { "cxfr", 4, {{RRE(0xb3b6,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} }, 566 { "cxr", 4, {{RRE(0xb369,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} }, 567 { "ddbr", 4, {{RRE(0xb31d,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, 568 { "debr", 4, {{RRE(0xb30d,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, 569 { "dxbr", 4, {{RRE(0xb34d,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, 570 { "dxr", 4, {{RRE(0xb22d,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1, RRE_R2} }, 571 { "ear", 4, {{RRE(0xb24f,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} }, 572 { "efpc", 4, {{RRE(0xb38c,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, 573 { "epar", 4, {{RRE(0xb226,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1} }, 574 { "ereg", 4, {{RRE(0xb249,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} }, 575 { "esar", 4, {{RRE(0xb227,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1} }, 576 { "esta", 4, {{RRE(0xb24a,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} }, 577 { "fidr", 4, {{RRE(0xb37f,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} }, 578 { "fier", 4, {{RRE(0xb377,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} }, 579 { "fixr", 4, {{RRE(0xb367,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} }, 580 { "iac", 4, {{RRE(0xb224,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1} }, 581 { "ipm", 4, {{RRE(0xb222,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1} }, 582 { "ipte", 4, {{RRE(0xb221,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1, RRE_R2} }, 583 { "iske", 4, {{RRE(0xb229,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1, RRE_R2} }, 584 { "ivsk", 4, {{RRE(0xb223,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1, RRE_R2} }, 585 { "kdbr", 4, {{RRE(0xb318,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, 586 { "kebr", 4, {{RRE(0xb308,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, 587 { "kxbr", 4, {{RRE(0xb348,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, 588 { "lcdbr", 4, {{RRE(0xb313,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, 589 { "lcebr", 4, {{RRE(0xb303,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, 590 { "lcxbr", 4, {{RRE(0xb343,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, 591 { "lcxr", 4, {{RRE(0xb363,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} }, 592 { "lder", 4, {{RRE(0xb324,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} }, 593 { "ldxbr", 4, {{RRE(0xb345,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, 594 { "ledbr", 4, {{RRE(0xb344,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, 595 { "lexbr", 4, {{RRE(0xb346,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, 596 { "lexr", 4, {{RRE(0xb366,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} }, 597 { "lndbr", 4, {{RRE(0xb311,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, 598 { "lnebr", 4, {{RRE(0xb301,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, 599 { "lnxbr", 4, {{RRE(0xb341,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, 600 { "lnxr", 4, {{RRE(0xb361,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} }, 601 { "lpdbr", 4, {{RRE(0xb310,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, 602 { "lpebr", 4, {{RRE(0xb300,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, 603 { "lpxbr", 4, {{RRE(0xb340,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, 604 { "lpxr", 4, {{RRE(0xb360,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} }, 605 { "ltdbr", 4, {{RRE(0xb312,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, 606 { "ltebr", 4, {{RRE(0xb302,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, 607 { "ltxbr", 4, {{RRE(0xb342,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, 608 { "ltxr", 4, {{RRE(0xb362,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} }, 609 { "lura", 4, {{RRE(0xb24b,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} }, 610 { "lxdr", 4, {{RRE(0xb325,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} }, 611 { "lxer", 4, {{RRE(0xb326,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} }, 612 { "lxr", 4, {{RRE(0xb365,0,0), 0}}, {{RRE_MASK, 0}}, IFX, {RRE_R1, RRE_R2} }, 613 { "lzdr", 4, {{RRE(0xb375,0,0), 0}}, {{RRE_MASK, 0}}, IFX, {RRE_R1, RRE_R2} }, 614 { "lzer", 4, {{RRE(0xb374,0,0), 0}}, {{RRE_MASK, 0}}, IFX, {RRE_R1, RRE_R2} }, 615 { "lzxr", 4, {{RRE(0xb376,0,0), 0}}, {{RRE_MASK, 0}}, IFX, {RRE_R1, RRE_R2} }, 616 { "mdbr", 4, {{RRE(0xb31c,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, 617 { "mdebr", 4, {{RRE(0xb30c,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, 618 { "meebr", 4, {{RRE(0xb317,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, 619 { "meer", 4, {{RRE(0xb337,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} }, 620 { "msr", 4, {{RRE(0xb252,0,0), 0}}, {{RRE_MASK, 0}}, IIR, {RRE_R1, RRE_R2} }, 621 { "msta", 4, {{RRE(0xb247,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1} }, 622 { "mvpg", 4, {{RRE(0xb254,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} }, 623 { "mvst", 4, {{RRE(0xb255,0,0), 0}}, {{RRE_MASK, 0}}, ISR, {RRE_R1, RRE_R2} }, 624 { "mxbr", 4, {{RRE(0xb34c,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, 625 { "mxdbr", 4, {{RRE(0xb307,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, 626 { "palb", 4, {{RRE(0xb248,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {0} }, 627 { "prbe", 4, {{RRE(0xb22a,0,0), 0}}, {{RRE_MASK, 0}}, I370, {RRE_R1, RRE_R2} }, 628 { "pt", 4, {{RRE(0xb228,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1, RRE_R2} }, 629 { "rrbe", 4, {{RRE(0xb22a,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1, RRE_R2} }, 630 { "sar", 4, {{RRE(0xb24e,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} }, 631 { "sdbr", 4, {{RRE(0xb31b,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, 632 { "sebr", 4, {{RRE(0xb30b,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, 633 { "servc", 4, {{RRE(0xb220,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} }, 634 { "sfpc", 4, {{RRE(0xb384,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, 635 { "sqdbr", 4, {{RRE(0xb315,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, 636 { "sqdr", 4, {{RRE(0xb244,0,0), 0}}, {{RRE_MASK, 0}}, IQR, {RRE_R1, RRE_R2} }, 637 { "sqebr", 4, {{RRE(0xb314,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, 638 { "sqer", 4, {{RRE(0xb245,0,0), 0}}, {{RRE_MASK, 0}}, IQR, {RRE_R1, RRE_R2} }, 639 { "sqxbr", 4, {{RRE(0xb316,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, 640 { "sqxr", 4, {{RRE(0xb336,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} }, 641 { "srst", 4, {{RRE(0xb25e,0,0), 0}}, {{RRE_MASK, 0}}, ISR, {RRE_R1, RRE_R2} }, 642 { "ssar", 4, {{RRE(0xb225,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1} }, 643 { "sske", 4, {{RRE(0xb22b,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1, RRE_R2} }, 644 { "stura", 4, {{RRE(0xb246,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} }, 645 { "sxbr", 4, {{RRE(0xb34b,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, 646 { "tar", 4, {{RRE(0xb24c,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} }, 647 { "tb", 4, {{RRE(0xb22c,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1, RRE_R2} }, 648 { "thdr", 4, {{RRE(0xb359,0,0), 0}}, {{RRE_MASK, 0}}, IFX, {RRE_R1, RRE_R2} }, 649 { "thder", 4, {{RRE(0xb359,0,0), 0}}, {{RRE_MASK, 0}}, IFX, {RRE_R1, RRE_R2} }, 650 651 /* RRF form instructions. */ 652 { "cfdbr", 4, {{RRF(0xb399,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} }, 653 { "cfdr", 4, {{RRF(0xb3b9,0,0,0), 0}}, {{RRF_MASK, 0}}, IHX, {RRF_R1, RRF_R3, RRF_R2} }, 654 { "cfebr", 4, {{RRF(0xb398,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} }, 655 { "cfer", 4, {{RRF(0xb3b8,0,0,0), 0}}, {{RRF_MASK, 0}}, IHX, {RRF_R1, RRF_R3, RRF_R2} }, 656 { "cfxbr", 4, {{RRF(0xb39a,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} }, 657 { "cfxr", 4, {{RRF(0xb3ba,0,0,0), 0}}, {{RRF_MASK, 0}}, IHX, {RRF_R1, RRF_R3, RRF_R2} }, 658 { "didbr", 4, {{RRF(0xb35b,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} }, 659 { "diebr", 4, {{RRF(0xb353,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} }, 660 { "fidbr", 4, {{RRF(0xb35f,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} }, 661 { "fiebr", 4, {{RRF(0xb357,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} }, 662 { "fixbr", 4, {{RRF(0xb347,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} }, 663 { "madbr", 4, {{RRF(0xb31e,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} }, 664 { "maebr", 4, {{RRF(0xb30e,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} }, 665 { "msdbr", 4, {{RRF(0xb31f,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} }, 666 { "msebr", 4, {{RRF(0xb30f,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} }, 667 { "tbdr", 4, {{RRF(0xb351,0,0,0), 0}}, {{RRF_MASK, 0}}, IFX, {RRF_R1, RRF_R3, RRF_R2} }, 668 { "tbedr", 4, {{RRF(0xb350,0,0,0), 0}}, {{RRF_MASK, 0}}, IFX, {RRF_R1, RRF_R3, RRF_R2} }, 669 670 /* RX form instructions. */ 671 { "a", 4, {{RX(0x5a,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, 672 { "ad", 4, {{RX(0x6a,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, 673 { "ae", 4, {{RX(0x7a,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, 674 { "ah", 4, {{RX(0x4a,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, 675 { "al", 4, {{RX(0x5e,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, 676 { "au", 4, {{RX(0x7e,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, 677 { "aw", 4, {{RX(0x6e,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, 678 { "bal", 4, {{RX(0x45,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, 679 { "bas", 4, {{RX(0x4d,0,0,0,0), 0}}, {{RX_MASK, 0}}, IXA, {RX_R1, RX_D2, RX_X2, RX_B2} }, 680 { "bc", 4, {{RX(0x47,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, 681 { "bct", 4, {{RX(0x46,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, 682 { "c", 4, {{RX(0x59,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, 683 { "cd", 4, {{RX(0x69,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, 684 { "ce", 4, {{RX(0x79,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, 685 { "ch", 4, {{RX(0x49,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, 686 { "cl", 4, {{RX(0x55,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, 687 { "cvb", 4, {{RX(0x4f,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, 688 { "cvd", 4, {{RX(0x4e,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, 689 { "d", 4, {{RX(0x5d,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, 690 { "dd", 4, {{RX(0x6d,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, 691 { "de", 4, {{RX(0x7d,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, 692 { "ex", 4, {{RX(0x44,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, 693 { "ic", 4, {{RX(0x43,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, 694 { "l", 4, {{RX(0x58,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, 695 { "la", 4, {{RX(0x41,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, 696 { "lae", 4, {{RX(0x51,0,0,0,0), 0}}, {{RX_MASK, 0}}, IESA, {RX_R1, RX_D2, RX_X2, RX_B2} }, 697 { "ld", 4, {{RX(0x68,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, 698 { "le", 4, {{RX(0x78,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, 699 { "lh", 4, {{RX(0x48,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, 700 { "lra", 4, {{RX(0xb1,0,0,0,0), 0}}, {{RX_MASK, 0}}, IXA, {RX_R1, RX_D2, RX_X2, RX_B2} }, 701 { "m", 4, {{RX(0x5c,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, 702 { "md", 4, {{RX(0x6c,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, 703 { "me", 4, {{RX(0x7c,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, 704 { "mh", 4, {{RX(0x4c,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, 705 { "ms", 4, {{RX(0x71,0,0,0,0), 0}}, {{RX_MASK, 0}}, IIR, {RX_R1, RX_D2, RX_X2, RX_B2} }, 706 { "mxd", 4, {{RX(0x67,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, 707 { "n", 4, {{RX(0x54,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, 708 { "o", 4, {{RX(0x56,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, 709 { "s", 4, {{RX(0x5b,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, 710 { "sd", 4, {{RX(0x6b,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, 711 { "se", 4, {{RX(0x7b,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, 712 { "sh", 4, {{RX(0x4b,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, 713 { "sl", 4, {{RX(0x5f,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, 714 { "st", 4, {{RX(0x50,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, 715 { "stc", 4, {{RX(0x42,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, 716 { "std", 4, {{RX(0x60,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, 717 { "ste", 4, {{RX(0x70,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, 718 { "sth", 4, {{RX(0x40,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, 719 { "su", 4, {{RX(0x7f,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, 720 { "sw", 4, {{RX(0x6f,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, 721 { "x", 4, {{RX(0x57,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, 722 723 /* RXE form instructions. */ 724 { "adb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x1a)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, 725 { "aeb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x0a)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, 726 { "cdb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x19)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, 727 { "ceb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x09)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, 728 { "ddb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x1d)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, 729 { "deb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x0d)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, 730 { "kdb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x18)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, 731 { "keb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x08)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, 732 { "lde", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x24)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, 733 { "ldeb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x04)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, 734 { "lxd", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x25)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, 735 { "lxdb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x05)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, 736 { "lxe", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x26)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, 737 { "lxeb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x06)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, 738 { "mdb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x1c)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, 739 { "mdeb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x0c)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, 740 { "mee", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x37)}}, {{RXEH_MASK, RXEL_MASK}}, IHX, {RX_R1, RX_D2, RX_X2, RX_B2} }, 741 { "meeb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x17)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, 742 { "mxdb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x07)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, 743 { "sqd", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x35)}}, {{RXEH_MASK, RXEL_MASK}}, IHX, {RX_R1, RX_D2, RX_X2, RX_B2} }, 744 { "sqdb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x15)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, 745 { "sqe", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x34)}}, {{RXEH_MASK, RXEL_MASK}}, IHX, {RX_R1, RX_D2, RX_X2, RX_B2} }, 746 { "sqeb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x14)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, 747 { "sdb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x1b)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, 748 { "seb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x0b)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, 749 { "tcdb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x11)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, 750 { "tceb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x10)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, 751 { "tcxb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x12)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, 752 753 /* RXF form instructions. */ 754 { "madb", 6, {{RXFH(0xed,0,0,0,0), RXFL(0x1e,0)}}, {{RXFH_MASK, RXFL_MASK}}, IBF, {RX_R1, RXF_R3, RX_D2, RX_X2, RX_B2} }, 755 { "maeb", 6, {{RXFH(0xed,0,0,0,0), RXFL(0x0e,0)}}, {{RXFH_MASK, RXFL_MASK}}, IBF, {RX_R1, RXF_R3, RX_D2, RX_X2, RX_B2} }, 756 { "msdb", 6, {{RXFH(0xed,0,0,0,0), RXFL(0x1f,0)}}, {{RXFH_MASK, RXFL_MASK}}, IBF, {RX_R1, RXF_R3, RX_D2, RX_X2, RX_B2} }, 757 { "mseb", 6, {{RXFH(0xed,0,0,0,0), RXFL(0x0f,0)}}, {{RXFH_MASK, RXFL_MASK}}, IBF, {RX_R1, RXF_R3, RX_D2, RX_X2, RX_B2} }, 758 759 /* RS form instructions. */ 760 { "bxh", 4, {{RS(0x86,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} }, 761 { "bxle", 4, {{RS(0x87,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} }, 762 { "cds", 4, {{RS(0xbb,0,0,0,0), 0}}, {{RS_MASK, 0}}, IXA, {RX_R1, RS_R3, RS_D2, RS_B2} }, 763 { "clcle", 4, {{RS(0xa9,0,0,0,0), 0}}, {{RS_MASK, 0}}, ICM, {RX_R1, RS_R3, RS_D2, RS_B2} }, 764 { "clm", 4, {{RS(0xbd,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} }, 765 { "cs", 4, {{RS(0xba,0,0,0,0), 0}}, {{RS_MASK, 0}}, IXA, {RX_R1, RS_R3, RS_D2, RS_B2} }, 766 { "icm", 4, {{RS(0xbf,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} }, 767 { "lam", 4, {{RS(0x9a,0,0,0,0), 0}}, {{RS_MASK, 0}}, IESA, {RX_R1, RS_R3, RS_D2, RS_B2} }, 768 { "lctl", 4, {{RS(0xb7,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} }, 769 { "lm", 4, {{RS(0x98,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} }, 770 { "mvcle", 4, {{RS(0xa8,0,0,0,0), 0}}, {{RS_MASK, 0}}, ICM, {RX_R1, RS_R3, RS_D2, RS_B2} }, 771 { "sigp", 4, {{RS(0xae,0,0,0,0), 0}}, {{RS_MASK, 0}}, IXA, {RX_R1, RS_R3, RS_D2, RS_B2} }, 772 { "stam", 4, {{RS(0x9b,0,0,0,0), 0}}, {{RS_MASK, 0}}, IESA, {RX_R1, RS_R3, RS_D2, RS_B2} }, 773 { "stcm", 4, {{RS(0xbe,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} }, 774 { "stctl", 4, {{RS(0xb6,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} }, 775 { "stm", 4, {{RS(0x90,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} }, 776 { "trace", 4, {{RS(0x99,0,0,0,0), 0}}, {{RS_MASK, 0}}, IXA, {RX_R1, RS_R3, RS_D2, RS_B2} }, 777 778 /* RS form instructions with blank R3 and optional B2 (shift left/right). */ 779 { "sla", 4, {{RS(0x8b,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_D2, RS_B2_OPT} }, 780 { "slda", 4, {{RS(0x8f,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_D2, RS_B2_OPT} }, 781 { "sldl", 4, {{RS(0x8d,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_D2, RS_B2_OPT} }, 782 { "sll", 4, {{RS(0x89,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_D2, RS_B2_OPT} }, 783 { "sra", 4, {{RS(0x8a,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_D2, RS_B2_OPT} }, 784 { "srda", 4, {{RS(0x8e,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_D2, RS_B2_OPT} }, 785 { "srdl", 4, {{RS(0x8c,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_D2, RS_B2_OPT} }, 786 { "srl", 4, {{RS(0x88,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_D2, RS_B2_OPT} }, 787 788 /* RSI form instructions. */ 789 { "brxh", 4, {{RSI(0x84,0,0,0), 0}}, {{RSI_MASK, 0}}, IIR, {RSI_R1, RSI_R3, RSI_I2} }, 790 { "brxle", 4, {{RSI(0x85,0,0,0), 0}}, {{RSI_MASK, 0}}, IIR, {RSI_R1, RSI_R3, RSI_I2} }, 791 792 /* RI form instructions. */ 793 { "ahi", 4, {{RI(0xa7a,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} }, 794 { "bras", 4, {{RI(0xa75,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} }, 795 { "brc", 4, {{RI(0xa74,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} }, 796 { "brct", 4, {{RI(0xa76,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} }, 797 { "chi", 4, {{RI(0xa7e,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} }, 798 { "lhi", 4, {{RI(0xa78,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} }, 799 { "mhi", 4, {{RI(0xa7c,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} }, 800 { "tmh", 4, {{RI(0xa70,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} }, 801 { "tml", 4, {{RI(0xa71,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} }, 802 803 /* SI form instructions. */ 804 { "cli", 4, {{SI(0x95,0,0,0), 0}}, {{SI_MASK, 0}}, I370, {SI_D1, SI_B1, SI_I2} }, 805 { "mc", 4, {{SI(0xaf,0,0,0), 0}}, {{SI_MASK, 0}}, I370, {SI_D1, SI_B1, SI_I2} }, 806 { "mvi", 4, {{SI(0x92,0,0,0), 0}}, {{SI_MASK, 0}}, I370, {SI_D1, SI_B1, SI_I2} }, 807 { "ni", 4, {{SI(0x94,0,0,0), 0}}, {{SI_MASK, 0}}, I370, {SI_D1, SI_B1, SI_I2} }, 808 { "oi", 4, {{SI(0x96,0,0,0), 0}}, {{SI_MASK, 0}}, I370, {SI_D1, SI_B1, SI_I2} }, 809 { "stnsm", 4, {{SI(0xac,0,0,0), 0}}, {{SI_MASK, 0}}, IXA, {SI_D1, SI_B1, SI_I2} }, 810 { "stosm", 4, {{SI(0xad,0,0,0), 0}}, {{SI_MASK, 0}}, IXA, {SI_D1, SI_B1, SI_I2} }, 811 { "tm", 4, {{SI(0x91,0,0,0), 0}}, {{SI_MASK, 0}}, I370, {SI_D1, SI_B1, SI_I2} }, 812 { "xi", 4, {{SI(0x97,0,0,0), 0}}, {{SI_MASK, 0}}, I370, {SI_D1, SI_B1, SI_I2} }, 813 814 /* S form instructions. */ 815 { "cfc", 4, {{S(0xb21a,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, 816 { "csch", 4, {{S(0xb230,0,0), 0}}, {{S_MASK, 0}}, IXA, {0} }, 817 { "hsch", 4, {{S(0xb231,0,0), 0}}, {{S_MASK, 0}}, IXA, {0} }, 818 { "ipk", 4, {{S(0xb20b,0,0), 0}}, {{S_MASK, 0}}, IXA, {0} }, 819 { "lfpc", 4, {{S(0xb29d,0,0), 0}}, {{S_MASK, 0}}, IBF, {S_D2, S_B2} }, 820 { "lpsw", 4, {{S(0x8200,0,0), 0}}, {{S_MASK, 0}}, I370, {S_D2, S_B2} }, 821 { "msch", 4, {{S(0xb232,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, 822 { "pc", 4, {{S(0xb218,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, 823 { "pcf", 4, {{S(0xb218,0,0), 0}}, {{S_MASK, 0}}, IPC, {S_D2, S_B2} }, 824 { "ptlb", 4, {{S(0xb20d,0,0), 0}}, {{S_MASK, 0}}, IXA, {0} }, 825 { "rchp", 4, {{S(0xb23b,0,0), 0}}, {{S_MASK, 0}}, IXA, {0} }, 826 { "rp", 4, {{S(0xb277,0,0), 0}}, {{S_MASK, 0}}, IRP, {0} }, 827 { "rsch", 4, {{S(0xb238,0,0), 0}}, {{S_MASK, 0}}, IXA, {0} }, 828 { "sac", 4, {{S(0xb219,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, 829 { "sacf", 4, {{S(0xb279,0,0), 0}}, {{S_MASK, 0}}, ISA, {S_D2, S_B2} }, 830 { "sal", 4, {{S(0xb237,0,0), 0}}, {{S_MASK, 0}}, IXA, {0} }, 831 { "schm", 4, {{S(0xb23c,0,0), 0}}, {{S_MASK, 0}}, IXA, {0} }, 832 { "sck", 4, {{S(0xb204,0,0), 0}}, {{S_MASK, 0}}, I370, {S_D2, S_B2} }, 833 { "sckc", 4, {{S(0xb206,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, 834 { "spka", 4, {{S(0xb20a,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, 835 { "spt", 4, {{S(0xb208,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, 836 { "spx", 4, {{S(0xb210,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, 837 { "srnm", 4, {{S(0xb299,0,0), 0}}, {{S_MASK, 0}}, IBF, {S_D2, S_B2} }, 838 { "ssch", 4, {{S(0xb233,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, 839 { "ssm", 4, {{S(0x8000,0,0), 0}}, {{S_MASK, 0}}, I370, {S_D2, S_B2} }, 840 { "stap", 4, {{S(0xb212,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, 841 { "stck", 4, {{S(0xb205,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, 842 { "stckc", 4, {{S(0xb207,0,0), 0}}, {{S_MASK, 0}}, I370, {S_D2, S_B2} }, 843 { "stcps", 4, {{S(0xb23a,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, 844 { "stcrw", 4, {{S(0xb239,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, 845 { "stfpc", 4, {{S(0xb29c,0,0), 0}}, {{S_MASK, 0}}, IBF, {S_D2, S_B2} }, 846 { "stidp", 4, {{S(0xb202,0,0), 0}}, {{S_MASK, 0}}, I370, {S_D2, S_B2} }, 847 { "stpt", 4, {{S(0xb209,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, 848 { "stpx", 4, {{S(0xb211,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, 849 { "stsch", 4, {{S(0xb234,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, 850 { "tpi", 4, {{S(0xb236,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, 851 { "trap4", 4, {{S(0xb2ff,0,0), 0}}, {{S_MASK, 0}}, ITR, {S_D2, S_B2} }, 852 { "ts", 4, {{S(0x9300,0,0), 0}}, {{S_MASK, 0}}, I370, {S_D2, S_B2} }, 853 { "tsch", 4, {{S(0xb235,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, 854 855 /* SS form instructions. */ 856 { "ap", 6, {{SSH(0xfa,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, 857 { "clc", 6, {{SSH(0xd5,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, 858 { "cp", 6, {{SSH(0xf9,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, 859 { "dp", 6, {{SSH(0xfd,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, 860 { "ed", 6, {{SSH(0xde,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, 861 { "edmk", 6, {{SSH(0xdf,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, 862 { "mvc", 6, {{SSH(0xd2,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, 863 { "mvcin", 6, {{SSH(0xe8,0,0,0), 0}}, {{SS_MASK, 0}}, IMI, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, 864 { "mvck", 6, {{SSH(0xd9,0,0,0), 0}}, {{SS_MASK, 0}}, IXA, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, 865 { "mvcp", 6, {{SSH(0xda,0,0,0), 0}}, {{SS_MASK, 0}}, IXA, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, 866 { "mvcs", 6, {{SSH(0xdb,0,0,0), 0}}, {{SS_MASK, 0}}, IXA, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, 867 { "mvn", 6, {{SSH(0xd1,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, 868 { "mvo", 6, {{SSH(0xf1,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, 869 { "mvz", 6, {{SSH(0xd3,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, 870 { "nc", 6, {{SSH(0xd4,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, 871 { "oc", 6, {{SSH(0xd6,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, 872 { "pack", 6, {{SSH(0xf2,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, 873 { "plo", 6, {{SSH(0xee,0,0,0), 0}}, {{SS_MASK, 0}}, IPL, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, 874 { "sp", 6, {{SSH(0xfb,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, 875 { "srp", 6, {{SSH(0xf0,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, 876 { "tr", 6, {{SSH(0xdc,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, 877 { "trt", 6, {{SSH(0xdd,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, 878 { "unpk", 6, {{SSH(0xf3,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, 879 { "xc", 6, {{SSH(0xd7,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, 880 { "zap", 6, {{SSH(0xf8,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, 881 882 /* SSE form instructions. */ 883 { "lasp", 6, {{SSEH(0xe500,0,0), 0}}, {{SSE_MASK, 0}}, IXA, {SS_D1, SS_B1, SS_D2, SS_B2} }, 884 { "mvcdk", 6, {{SSEH(0xe50f,0,0), 0}}, {{SSE_MASK, 0}}, IESA, {SS_D1, SS_B1, SS_D2, SS_B2} }, 885 { "mvcsk", 6, {{SSEH(0xe50e,0,0), 0}}, {{SSE_MASK, 0}}, IESA, {SS_D1, SS_B1, SS_D2, SS_B2} }, 886 { "tprot", 6, {{SSEH(0xe501,0,0), 0}}, {{SSE_MASK, 0}}, IXA, {SS_D1, SS_B1, SS_D2, SS_B2} }, 887 888 /* */ 889 }; 890 891 const int i370_num_opcodes = 892 sizeof (i370_opcodes) / sizeof (i370_opcodes[0]); 893 894 /* The macro table. This is only used by the assembler. */ 896 897 const struct i370_macro i370_macros[] = 898 { 899 { "b", 1, I370, "bc 15,%0" }, 900 { "br", 1, I370, "bcr 15,%0" }, 901 902 { "nop", 1, I370, "bc 0,%0" }, 903 { "nopr", 1, I370, "bcr 0,%0" }, 904 905 { "bh", 1, I370, "bc 2,%0" }, 906 { "bhr", 1, I370, "bcr 2,%0" }, 907 { "bl", 1, I370, "bc 4,%0" }, 908 { "blr", 1, I370, "bcr 4,%0" }, 909 { "be", 1, I370, "bc 8,%0" }, 910 { "ber", 1, I370, "bcr 8,%0" }, 911 912 { "bnh", 1, I370, "bc 13,%0" }, 913 { "bnhr", 1, I370, "bcr 13,%0" }, 914 { "bnl", 1, I370, "bc 11,%0" }, 915 { "bnlr", 1, I370, "bcr 11,%0" }, 916 { "bne", 1, I370, "bc 7,%0" }, 917 { "bner", 1, I370, "bcr 7,%0" }, 918 919 { "bp", 1, I370, "bc 2,%0" }, 920 { "bpr", 1, I370, "bcr 2,%0" }, 921 { "bm", 1, I370, "bc 4,%0" }, 922 { "bmr", 1, I370, "bcr 4,%0" }, 923 { "bz", 1, I370, "bc 8,%0" }, 924 { "bzr", 1, I370, "bcr 8,%0" }, 925 { "bo", 1, I370, "bc 1,%0" }, 926 { "bor", 1, I370, "bcr 1,%0" }, 927 928 { "bnp", 1, I370, "bc 13,%0" }, 929 { "bnpr", 1, I370, "bcr 13,%0" }, 930 { "bnm", 1, I370, "bc 11,%0" }, 931 { "bnmr", 1, I370, "bcr 11,%0" }, 932 { "bnz", 1, I370, "bc 7,%0" }, 933 { "bnzr", 1, I370, "bcr 7,%0" }, 934 { "bno", 1, I370, "bc 14,%0" }, 935 { "bnor", 1, I370, "bcr 14,%0" }, 936 937 { "sync", 0, I370, "bcr 15,0" }, 938 939 }; 940 941 const int i370_num_macros = 942 sizeof (i370_macros) / sizeof (i370_macros[0]); 943
