1 //===- ARMISelLowering.h - ARM DAG Lowering Interface -----------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the interfaces that ARM uses to lower LLVM code into a 11 // selection DAG. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H 16 #define LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H 17 18 #include "MCTargetDesc/ARMBaseInfo.h" 19 #include "llvm/ADT/SmallVector.h" 20 #include "llvm/ADT/StringRef.h" 21 #include "llvm/CodeGen/CallingConvLower.h" 22 #include "llvm/CodeGen/ISDOpcodes.h" 23 #include "llvm/CodeGen/MachineFunction.h" 24 #include "llvm/CodeGen/SelectionDAGNodes.h" 25 #include "llvm/CodeGen/TargetLowering.h" 26 #include "llvm/CodeGen/ValueTypes.h" 27 #include "llvm/IR/Attributes.h" 28 #include "llvm/IR/CallingConv.h" 29 #include "llvm/IR/Function.h" 30 #include "llvm/IR/IRBuilder.h" 31 #include "llvm/IR/InlineAsm.h" 32 #include "llvm/Support/CodeGen.h" 33 #include "llvm/Support/MachineValueType.h" 34 #include <utility> 35 36 namespace llvm { 37 38 class ARMSubtarget; 39 class DataLayout; 40 class FastISel; 41 class FunctionLoweringInfo; 42 class GlobalValue; 43 class InstrItineraryData; 44 class Instruction; 45 class MachineBasicBlock; 46 class MachineInstr; 47 class SelectionDAG; 48 class TargetLibraryInfo; 49 class TargetMachine; 50 class TargetRegisterInfo; 51 class VectorType; 52 53 namespace ARMISD { 54 55 // ARM Specific DAG Nodes 56 enum NodeType : unsigned { 57 // Start the numbering where the builtin ops and target ops leave off. 58 FIRST_NUMBER = ISD::BUILTIN_OP_END, 59 60 Wrapper, // Wrapper - A wrapper node for TargetConstantPool, 61 // TargetExternalSymbol, and TargetGlobalAddress. 62 WrapperPIC, // WrapperPIC - A wrapper node for TargetGlobalAddress in 63 // PIC mode. 64 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable 65 66 // Add pseudo op to model memcpy for struct byval. 67 COPY_STRUCT_BYVAL, 68 69 CALL, // Function call. 70 CALL_PRED, // Function call that's predicable. 71 CALL_NOLINK, // Function call with branch not branch-and-link. 72 BRCOND, // Conditional branch. 73 BR_JT, // Jumptable branch. 74 BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump). 75 RET_FLAG, // Return with a flag operand. 76 INTRET_FLAG, // Interrupt return with an LR-offset and a flag operand. 77 78 PIC_ADD, // Add with a PC operand and a PIC label. 79 80 CMP, // ARM compare instructions. 81 CMN, // ARM CMN instructions. 82 CMPZ, // ARM compare that sets only Z flag. 83 CMPFP, // ARM VFP compare instruction, sets FPSCR. 84 CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR. 85 FMSTAT, // ARM fmstat instruction. 86 87 CMOV, // ARM conditional move instructions. 88 89 SSAT, // Signed saturation 90 USAT, // Unsigned saturation 91 92 BCC_i64, 93 94 SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out. 95 SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out. 96 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag. 97 98 ADDC, // Add with carry 99 ADDE, // Add using carry 100 SUBC, // Sub with carry 101 SUBE, // Sub using carry 102 103 VMOVRRD, // double to two gprs. 104 VMOVDRR, // Two gprs to double. 105 VMOVSR, // move gpr to single, used for f32 literal constructed in a gpr 106 107 EH_SJLJ_SETJMP, // SjLj exception handling setjmp. 108 EH_SJLJ_LONGJMP, // SjLj exception handling longjmp. 109 EH_SJLJ_SETUP_DISPATCH, // SjLj exception handling setup_dispatch. 110 111 TC_RETURN, // Tail call return pseudo. 112 113 THREAD_POINTER, 114 115 DYN_ALLOC, // Dynamic allocation on the stack. 116 117 MEMBARRIER_MCR, // Memory barrier (MCR) 118 119 PRELOAD, // Preload 120 121 WIN__CHKSTK, // Windows' __chkstk call to do stack probing. 122 WIN__DBZCHK, // Windows' divide by zero check 123 124 VCEQ, // Vector compare equal. 125 VCEQZ, // Vector compare equal to zero. 126 VCGE, // Vector compare greater than or equal. 127 VCGEZ, // Vector compare greater than or equal to zero. 128 VCLEZ, // Vector compare less than or equal to zero. 129 VCGEU, // Vector compare unsigned greater than or equal. 130 VCGT, // Vector compare greater than. 131 VCGTZ, // Vector compare greater than zero. 132 VCLTZ, // Vector compare less than zero. 133 VCGTU, // Vector compare unsigned greater than. 134 VTST, // Vector test bits. 135 136 // Vector shift by immediate: 137 VSHL, // ...left 138 VSHRs, // ...right (signed) 139 VSHRu, // ...right (unsigned) 140 141 // Vector rounding shift by immediate: 142 VRSHRs, // ...right (signed) 143 VRSHRu, // ...right (unsigned) 144 VRSHRN, // ...right narrow 145 146 // Vector saturating shift by immediate: 147 VQSHLs, // ...left (signed) 148 VQSHLu, // ...left (unsigned) 149 VQSHLsu, // ...left (signed to unsigned) 150 VQSHRNs, // ...right narrow (signed) 151 VQSHRNu, // ...right narrow (unsigned) 152 VQSHRNsu, // ...right narrow (signed to unsigned) 153 154 // Vector saturating rounding shift by immediate: 155 VQRSHRNs, // ...right narrow (signed) 156 VQRSHRNu, // ...right narrow (unsigned) 157 VQRSHRNsu, // ...right narrow (signed to unsigned) 158 159 // Vector shift and insert: 160 VSLI, // ...left 161 VSRI, // ...right 162 163 // Vector get lane (VMOV scalar to ARM core register) 164 // (These are used for 8- and 16-bit element types only.) 165 VGETLANEu, // zero-extend vector extract element 166 VGETLANEs, // sign-extend vector extract element 167 168 // Vector move immediate and move negated immediate: 169 VMOVIMM, 170 VMVNIMM, 171 172 // Vector move f32 immediate: 173 VMOVFPIMM, 174 175 // Move H <-> R, clearing top 16 bits 176 VMOVrh, 177 VMOVhr, 178 179 // Vector duplicate: 180 VDUP, 181 VDUPLANE, 182 183 // Vector shuffles: 184 VEXT, // extract 185 VREV64, // reverse elements within 64-bit doublewords 186 VREV32, // reverse elements within 32-bit words 187 VREV16, // reverse elements within 16-bit halfwords 188 VZIP, // zip (interleave) 189 VUZP, // unzip (deinterleave) 190 VTRN, // transpose 191 VTBL1, // 1-register shuffle with mask 192 VTBL2, // 2-register shuffle with mask 193 194 // Vector multiply long: 195 VMULLs, // ...signed 196 VMULLu, // ...unsigned 197 198 SMULWB, // Signed multiply word by half word, bottom 199 SMULWT, // Signed multiply word by half word, top 200 UMLAL, // 64bit Unsigned Accumulate Multiply 201 SMLAL, // 64bit Signed Accumulate Multiply 202 UMAAL, // 64-bit Unsigned Accumulate Accumulate Multiply 203 SMLALBB, // 64-bit signed accumulate multiply bottom, bottom 16 204 SMLALBT, // 64-bit signed accumulate multiply bottom, top 16 205 SMLALTB, // 64-bit signed accumulate multiply top, bottom 16 206 SMLALTT, // 64-bit signed accumulate multiply top, top 16 207 SMLALD, // Signed multiply accumulate long dual 208 SMLALDX, // Signed multiply accumulate long dual exchange 209 SMLSLD, // Signed multiply subtract long dual 210 SMLSLDX, // Signed multiply subtract long dual exchange 211 SMMLAR, // Signed multiply long, round and add 212 SMMLSR, // Signed multiply long, subtract and round 213 214 // Operands of the standard BUILD_VECTOR node are not legalized, which 215 // is fine if BUILD_VECTORs are always lowered to shuffles or other 216 // operations, but for ARM some BUILD_VECTORs are legal as-is and their 217 // operands need to be legalized. Define an ARM-specific version of 218 // BUILD_VECTOR for this purpose. 219 BUILD_VECTOR, 220 221 // Bit-field insert 222 BFI, 223 224 // Vector OR with immediate 225 VORRIMM, 226 // Vector AND with NOT of immediate 227 VBICIMM, 228 229 // Vector bitwise select 230 VBSL, 231 232 // Pseudo-instruction representing a memory copy using ldm/stm 233 // instructions. 234 MEMCPY, 235 236 // Vector load N-element structure to all lanes: 237 VLD1DUP = ISD::FIRST_TARGET_MEMORY_OPCODE, 238 VLD2DUP, 239 VLD3DUP, 240 VLD4DUP, 241 242 // NEON loads with post-increment base updates: 243 VLD1_UPD, 244 VLD2_UPD, 245 VLD3_UPD, 246 VLD4_UPD, 247 VLD2LN_UPD, 248 VLD3LN_UPD, 249 VLD4LN_UPD, 250 VLD1DUP_UPD, 251 VLD2DUP_UPD, 252 VLD3DUP_UPD, 253 VLD4DUP_UPD, 254 255 // NEON stores with post-increment base updates: 256 VST1_UPD, 257 VST2_UPD, 258 VST3_UPD, 259 VST4_UPD, 260 VST2LN_UPD, 261 VST3LN_UPD, 262 VST4LN_UPD 263 }; 264 265 } // end namespace ARMISD 266 267 /// Define some predicates that are used for node matching. 268 namespace ARM { 269 270 bool isBitFieldInvertedMask(unsigned v); 271 272 } // end namespace ARM 273 274 //===--------------------------------------------------------------------===// 275 // ARMTargetLowering - ARM Implementation of the TargetLowering interface 276 277 class ARMTargetLowering : public TargetLowering { 278 public: 279 explicit ARMTargetLowering(const TargetMachine &TM, 280 const ARMSubtarget &STI); 281 282 unsigned getJumpTableEncoding() const override; 283 bool useSoftFloat() const override; 284 285 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 286 287 /// ReplaceNodeResults - Replace the results of node with an illegal result 288 /// type with new values built out of custom code. 289 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, 290 SelectionDAG &DAG) const override; 291 292 const char *getTargetNodeName(unsigned Opcode) const override; 293 294 bool isSelectSupported(SelectSupportKind Kind) const override { 295 // ARM does not support scalar condition selects on vectors. 296 return (Kind != ScalarCondVectorVal); 297 } 298 299 bool isReadOnly(const GlobalValue *GV) const; 300 301 /// getSetCCResultType - Return the value type to use for ISD::SETCC. 302 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, 303 EVT VT) const override; 304 305 MachineBasicBlock * 306 EmitInstrWithCustomInserter(MachineInstr &MI, 307 MachineBasicBlock *MBB) const override; 308 309 void AdjustInstrPostInstrSelection(MachineInstr &MI, 310 SDNode *Node) const override; 311 312 SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const; 313 SDValue PerformBRCONDCombine(SDNode *N, SelectionDAG &DAG) const; 314 SDValue PerformCMOVToBFICombine(SDNode *N, SelectionDAG &DAG) const; 315 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 316 317 bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const override; 318 319 /// allowsMisalignedMemoryAccesses - Returns true if the target allows 320 /// unaligned memory accesses of the specified type. Returns whether it 321 /// is "fast" by reference in the second argument. 322 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace, 323 unsigned Align, 324 bool *Fast) const override; 325 326 EVT getOptimalMemOpType(uint64_t Size, 327 unsigned DstAlign, unsigned SrcAlign, 328 bool IsMemset, bool ZeroMemset, 329 bool MemcpyStrSrc, 330 MachineFunction &MF) const override; 331 332 bool isTruncateFree(Type *SrcTy, Type *DstTy) const override; 333 bool isTruncateFree(EVT SrcVT, EVT DstVT) const override; 334 bool isZExtFree(SDValue Val, EVT VT2) const override; 335 bool isFNegFree(EVT VT) const override; 336 337 bool isVectorLoadExtDesirable(SDValue ExtVal) const override; 338 339 bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override; 340 341 342 /// isLegalAddressingMode - Return true if the addressing mode represented 343 /// by AM is legal for this target, for a load/store of the specified type. 344 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, 345 Type *Ty, unsigned AS, 346 Instruction *I = nullptr) const override; 347 348 /// getScalingFactorCost - Return the cost of the scaling used in 349 /// addressing mode represented by AM. 350 /// If the AM is supported, the return value must be >= 0. 351 /// If the AM is not supported, the return value must be negative. 352 int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM, Type *Ty, 353 unsigned AS) const override; 354 355 bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const; 356 357 /// Returns true if the addresing mode representing by AM is legal 358 /// for the Thumb1 target, for a load/store of the specified type. 359 bool isLegalT1ScaledAddressingMode(const AddrMode &AM, EVT VT) const; 360 361 /// isLegalICmpImmediate - Return true if the specified immediate is legal 362 /// icmp immediate, that is the target has icmp instructions which can 363 /// compare a register against the immediate without having to materialize 364 /// the immediate into a register. 365 bool isLegalICmpImmediate(int64_t Imm) const override; 366 367 /// isLegalAddImmediate - Return true if the specified immediate is legal 368 /// add immediate, that is the target has add instructions which can 369 /// add a register and the immediate without having to materialize 370 /// the immediate into a register. 371 bool isLegalAddImmediate(int64_t Imm) const override; 372 373 /// getPreIndexedAddressParts - returns true by value, base pointer and 374 /// offset pointer and addressing mode by reference if the node's address 375 /// can be legally represented as pre-indexed load / store address. 376 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset, 377 ISD::MemIndexedMode &AM, 378 SelectionDAG &DAG) const override; 379 380 /// getPostIndexedAddressParts - returns true by value, base pointer and 381 /// offset pointer and addressing mode by reference if this node can be 382 /// combined with a load / store to form a post-indexed load / store. 383 bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, 384 SDValue &Offset, ISD::MemIndexedMode &AM, 385 SelectionDAG &DAG) const override; 386 387 void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, 388 const APInt &DemandedElts, 389 const SelectionDAG &DAG, 390 unsigned Depth) const override; 391 392 393 bool ExpandInlineAsm(CallInst *CI) const override; 394 395 ConstraintType getConstraintType(StringRef Constraint) const override; 396 397 /// Examine constraint string and operand type and determine a weight value. 398 /// The operand object must already have been set up with the operand type. 399 ConstraintWeight getSingleConstraintMatchWeight( 400 AsmOperandInfo &info, const char *constraint) const override; 401 402 std::pair<unsigned, const TargetRegisterClass *> 403 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 404 StringRef Constraint, MVT VT) const override; 405 406 const char *LowerXConstraint(EVT ConstraintVT) const override; 407 408 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 409 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is 410 /// true it means one of the asm constraint of the inline asm instruction 411 /// being processed is 'm'. 412 void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, 413 std::vector<SDValue> &Ops, 414 SelectionDAG &DAG) const override; 415 416 unsigned 417 getInlineAsmMemConstraint(StringRef ConstraintCode) const override { 418 if (ConstraintCode == "Q") 419 return InlineAsm::Constraint_Q; 420 else if (ConstraintCode == "o") 421 return InlineAsm::Constraint_o; 422 else if (ConstraintCode.size() == 2) { 423 if (ConstraintCode[0] == 'U') { 424 switch(ConstraintCode[1]) { 425 default: 426 break; 427 case 'm': 428 return InlineAsm::Constraint_Um; 429 case 'n': 430 return InlineAsm::Constraint_Un; 431 case 'q': 432 return InlineAsm::Constraint_Uq; 433 case 's': 434 return InlineAsm::Constraint_Us; 435 case 't': 436 return InlineAsm::Constraint_Ut; 437 case 'v': 438 return InlineAsm::Constraint_Uv; 439 case 'y': 440 return InlineAsm::Constraint_Uy; 441 } 442 } 443 } 444 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode); 445 } 446 447 const ARMSubtarget* getSubtarget() const { 448 return Subtarget; 449 } 450 451 /// getRegClassFor - Return the register class that should be used for the 452 /// specified value type. 453 const TargetRegisterClass *getRegClassFor(MVT VT) const override; 454 455 /// Returns true if a cast between SrcAS and DestAS is a noop. 456 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override { 457 // Addrspacecasts are always noops. 458 return true; 459 } 460 461 bool shouldAlignPointerArgs(CallInst *CI, unsigned &MinSize, 462 unsigned &PrefAlign) const override; 463 464 /// createFastISel - This method returns a target specific FastISel object, 465 /// or null if the target does not support "fast" ISel. 466 FastISel *createFastISel(FunctionLoweringInfo &funcInfo, 467 const TargetLibraryInfo *libInfo) const override; 468 469 Sched::Preference getSchedulingPreference(SDNode *N) const override; 470 471 bool 472 isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const override; 473 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override; 474 475 /// isFPImmLegal - Returns true if the target can instruction select the 476 /// specified FP immediate natively. If false, the legalizer will 477 /// materialize the FP immediate as a load from a constant pool. 478 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override; 479 480 bool getTgtMemIntrinsic(IntrinsicInfo &Info, 481 const CallInst &I, 482 MachineFunction &MF, 483 unsigned Intrinsic) const override; 484 485 /// Returns true if it is beneficial to convert a load of a constant 486 /// to just the constant itself. 487 bool shouldConvertConstantLoadToIntImm(const APInt &Imm, 488 Type *Ty) const override; 489 490 /// Return true if EXTRACT_SUBVECTOR is cheap for this result type 491 /// with this index. 492 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, 493 unsigned Index) const override; 494 495 /// Returns true if an argument of type Ty needs to be passed in a 496 /// contiguous block of registers in calling convention CallConv. 497 bool functionArgumentNeedsConsecutiveRegisters( 498 Type *Ty, CallingConv::ID CallConv, bool isVarArg) const override; 499 500 /// If a physical register, this returns the register that receives the 501 /// exception address on entry to an EH pad. 502 unsigned 503 getExceptionPointerRegister(const Constant *PersonalityFn) const override; 504 505 /// If a physical register, this returns the register that receives the 506 /// exception typeid on entry to a landing pad. 507 unsigned 508 getExceptionSelectorRegister(const Constant *PersonalityFn) const override; 509 510 Instruction *makeDMB(IRBuilder<> &Builder, ARM_MB::MemBOpt Domain) const; 511 Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr, 512 AtomicOrdering Ord) const override; 513 Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val, 514 Value *Addr, AtomicOrdering Ord) const override; 515 516 void emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> &Builder) const override; 517 518 Instruction *emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst, 519 AtomicOrdering Ord) const override; 520 Instruction *emitTrailingFence(IRBuilder<> &Builder, Instruction *Inst, 521 AtomicOrdering Ord) const override; 522 523 unsigned getMaxSupportedInterleaveFactor() const override { return 4; } 524 525 bool lowerInterleavedLoad(LoadInst *LI, 526 ArrayRef<ShuffleVectorInst *> Shuffles, 527 ArrayRef<unsigned> Indices, 528 unsigned Factor) const override; 529 bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI, 530 unsigned Factor) const override; 531 532 bool shouldInsertFencesForAtomic(const Instruction *I) const override; 533 TargetLoweringBase::AtomicExpansionKind 534 shouldExpandAtomicLoadInIR(LoadInst *LI) const override; 535 bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override; 536 TargetLoweringBase::AtomicExpansionKind 537 shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override; 538 bool shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override; 539 540 bool useLoadStackGuardNode() const override; 541 542 bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx, 543 unsigned &Cost) const override; 544 545 bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT, 546 const SelectionDAG &DAG) const override { 547 // Do not merge to larger than i32. 548 return (MemVT.getSizeInBits() <= 32); 549 } 550 551 bool isCheapToSpeculateCttz() const override; 552 bool isCheapToSpeculateCtlz() const override; 553 554 bool convertSetCCLogicToBitwiseLogic(EVT VT) const override { 555 return VT.isScalarInteger(); 556 } 557 558 bool supportSwiftError() const override { 559 return true; 560 } 561 562 bool hasStandaloneRem(EVT VT) const override { 563 return HasStandaloneRem; 564 } 565 566 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool isVarArg) const; 567 CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC, bool isVarArg) const; 568 569 /// Returns true if \p VecTy is a legal interleaved access type. This 570 /// function checks the vector element type and the overall width of the 571 /// vector. 572 bool isLegalInterleavedAccessType(VectorType *VecTy, 573 const DataLayout &DL) const; 574 575 /// Returns the number of interleaved accesses that will be generated when 576 /// lowering accesses of the given type. 577 unsigned getNumInterleavedAccesses(VectorType *VecTy, 578 const DataLayout &DL) const; 579 580 void finalizeLowering(MachineFunction &MF) const override; 581 582 /// Return the correct alignment for the current calling convention. 583 unsigned getABIAlignmentForCallingConv(Type *ArgTy, 584 DataLayout DL) const override; 585 586 protected: 587 std::pair<const TargetRegisterClass *, uint8_t> 588 findRepresentativeClass(const TargetRegisterInfo *TRI, 589 MVT VT) const override; 590 591 private: 592 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can 593 /// make the right decision when generating code for different targets. 594 const ARMSubtarget *Subtarget; 595 596 const TargetRegisterInfo *RegInfo; 597 598 const InstrItineraryData *Itins; 599 600 /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created. 601 unsigned ARMPCLabelIndex; 602 603 // TODO: remove this, and have shouldInsertFencesForAtomic do the proper 604 // check. 605 bool InsertFencesForAtomic; 606 607 bool HasStandaloneRem = true; 608 609 void addTypeForNEON(MVT VT, MVT PromotedLdStVT, MVT PromotedBitwiseVT); 610 void addDRTypeForNEON(MVT VT); 611 void addQRTypeForNEON(MVT VT); 612 std::pair<SDValue, SDValue> getARMXALUOOp(SDValue Op, SelectionDAG &DAG, SDValue &ARMcc) const; 613 614 using RegsToPassVector = SmallVector<std::pair<unsigned, SDValue>, 8>; 615 616 void PassF64ArgInRegs(const SDLoc &dl, SelectionDAG &DAG, SDValue Chain, 617 SDValue &Arg, RegsToPassVector &RegsToPass, 618 CCValAssign &VA, CCValAssign &NextVA, 619 SDValue &StackPtr, 620 SmallVectorImpl<SDValue> &MemOpChains, 621 ISD::ArgFlagsTy Flags) const; 622 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA, 623 SDValue &Root, SelectionDAG &DAG, 624 const SDLoc &dl) const; 625 626 CallingConv::ID getEffectiveCallingConv(CallingConv::ID CC, 627 bool isVarArg) const; 628 CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return, 629 bool isVarArg) const; 630 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg, 631 const SDLoc &dl, SelectionDAG &DAG, 632 const CCValAssign &VA, 633 ISD::ArgFlagsTy Flags) const; 634 SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const; 635 SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const; 636 SDValue LowerEH_SJLJ_SETUP_DISPATCH(SDValue Op, SelectionDAG &DAG) const; 637 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG, 638 const ARMSubtarget *Subtarget) const; 639 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 640 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 641 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 642 SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const; 643 SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const; 644 SDValue LowerGlobalAddressWindows(SDValue Op, SelectionDAG &DAG) const; 645 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 646 SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, 647 SelectionDAG &DAG) const; 648 SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA, 649 SelectionDAG &DAG, 650 TLSModel::Model model) const; 651 SDValue LowerGlobalTLSAddressDarwin(SDValue Op, SelectionDAG &DAG) const; 652 SDValue LowerGlobalTLSAddressWindows(SDValue Op, SelectionDAG &DAG) const; 653 SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const; 654 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const; 655 SDValue LowerSignedALUO(SDValue Op, SelectionDAG &DAG) const; 656 SDValue LowerUnsignedALUO(SDValue Op, SelectionDAG &DAG) const; 657 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const; 658 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 659 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const; 660 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const; 661 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const; 662 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 663 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 664 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const; 665 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const; 666 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const; 667 SDValue LowerConstantFP(SDValue Op, SelectionDAG &DAG, 668 const ARMSubtarget *ST) const; 669 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG, 670 const ARMSubtarget *ST) const; 671 SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const; 672 SDValue LowerDivRem(SDValue Op, SelectionDAG &DAG) const; 673 SDValue LowerDIV_Windows(SDValue Op, SelectionDAG &DAG, bool Signed) const; 674 void ExpandDIV_Windows(SDValue Op, SelectionDAG &DAG, bool Signed, 675 SmallVectorImpl<SDValue> &Results) const; 676 SDValue LowerWindowsDIVLibCall(SDValue Op, SelectionDAG &DAG, bool Signed, 677 SDValue &Chain) const; 678 SDValue LowerREM(SDNode *N, SelectionDAG &DAG) const; 679 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const; 680 SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const; 681 SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const; 682 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const; 683 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const; 684 685 unsigned getRegisterByName(const char* RegName, EVT VT, 686 SelectionDAG &DAG) const override; 687 688 /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster 689 /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be 690 /// expanded to FMAs when this method returns true, otherwise fmuladd is 691 /// expanded to fmul + fadd. 692 /// 693 /// ARM supports both fused and unfused multiply-add operations; we already 694 /// lower a pair of fmul and fadd to the latter so it's not clear that there 695 /// would be a gain or that the gain would be worthwhile enough to risk 696 /// correctness bugs. 697 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override { return false; } 698 699 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const; 700 701 SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 702 CallingConv::ID CallConv, bool isVarArg, 703 const SmallVectorImpl<ISD::InputArg> &Ins, 704 const SDLoc &dl, SelectionDAG &DAG, 705 SmallVectorImpl<SDValue> &InVals, bool isThisReturn, 706 SDValue ThisVal) const; 707 708 bool supportSplitCSR(MachineFunction *MF) const override { 709 return MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS && 710 MF->getFunction().hasFnAttribute(Attribute::NoUnwind); 711 } 712 713 void initializeSplitCSR(MachineBasicBlock *Entry) const override; 714 void insertCopiesSplitCSR( 715 MachineBasicBlock *Entry, 716 const SmallVectorImpl<MachineBasicBlock *> &Exits) const override; 717 718 SDValue 719 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 720 const SmallVectorImpl<ISD::InputArg> &Ins, 721 const SDLoc &dl, SelectionDAG &DAG, 722 SmallVectorImpl<SDValue> &InVals) const override; 723 724 int StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG, const SDLoc &dl, 725 SDValue &Chain, const Value *OrigArg, 726 unsigned InRegsParamRecordIdx, int ArgOffset, 727 unsigned ArgSize) const; 728 729 void VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG, 730 const SDLoc &dl, SDValue &Chain, 731 unsigned ArgOffset, unsigned TotalArgRegsSaveSize, 732 bool ForceMutable = false) const; 733 734 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, 735 SmallVectorImpl<SDValue> &InVals) const override; 736 737 /// HandleByVal - Target-specific cleanup for ByVal support. 738 void HandleByVal(CCState *, unsigned &, unsigned) const override; 739 740 /// IsEligibleForTailCallOptimization - Check whether the call is eligible 741 /// for tail call optimization. Targets which want to do tail call 742 /// optimization should implement this function. 743 bool IsEligibleForTailCallOptimization(SDValue Callee, 744 CallingConv::ID CalleeCC, 745 bool isVarArg, 746 bool isCalleeStructRet, 747 bool isCallerStructRet, 748 const SmallVectorImpl<ISD::OutputArg> &Outs, 749 const SmallVectorImpl<SDValue> &OutVals, 750 const SmallVectorImpl<ISD::InputArg> &Ins, 751 SelectionDAG& DAG) const; 752 753 bool CanLowerReturn(CallingConv::ID CallConv, 754 MachineFunction &MF, bool isVarArg, 755 const SmallVectorImpl<ISD::OutputArg> &Outs, 756 LLVMContext &Context) const override; 757 758 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 759 const SmallVectorImpl<ISD::OutputArg> &Outs, 760 const SmallVectorImpl<SDValue> &OutVals, 761 const SDLoc &dl, SelectionDAG &DAG) const override; 762 763 bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override; 764 765 bool mayBeEmittedAsTailCall(const CallInst *CI) const override; 766 767 SDValue getCMOV(const SDLoc &dl, EVT VT, SDValue FalseVal, SDValue TrueVal, 768 SDValue ARMcc, SDValue CCR, SDValue Cmp, 769 SelectionDAG &DAG) const; 770 SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, 771 SDValue &ARMcc, SelectionDAG &DAG, const SDLoc &dl) const; 772 SDValue getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG, 773 const SDLoc &dl, bool InvalidOnQNaN) const; 774 SDValue duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const; 775 776 SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const; 777 778 void SetupEntryBlockForSjLj(MachineInstr &MI, MachineBasicBlock *MBB, 779 MachineBasicBlock *DispatchBB, int FI) const; 780 781 void EmitSjLjDispatchBlock(MachineInstr &MI, MachineBasicBlock *MBB) const; 782 783 bool RemapAddSubWithFlags(MachineInstr &MI, MachineBasicBlock *BB) const; 784 785 MachineBasicBlock *EmitStructByval(MachineInstr &MI, 786 MachineBasicBlock *MBB) const; 787 788 MachineBasicBlock *EmitLowered__chkstk(MachineInstr &MI, 789 MachineBasicBlock *MBB) const; 790 MachineBasicBlock *EmitLowered__dbzchk(MachineInstr &MI, 791 MachineBasicBlock *MBB) const; 792 }; 793 794 enum NEONModImmType { 795 VMOVModImm, 796 VMVNModImm, 797 OtherModImm 798 }; 799 800 namespace ARM { 801 802 FastISel *createFastISel(FunctionLoweringInfo &funcInfo, 803 const TargetLibraryInfo *libInfo); 804 805 } // end namespace ARM 806 807 } // end namespace llvm 808 809 #endif // LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H 810
