1 //===-- RISCVISelLowering.cpp - RISCV DAG Lowering Implementation --------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the interfaces that RISCV uses to lower LLVM code into a 11 // selection DAG. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "RISCVISelLowering.h" 16 #include "RISCV.h" 17 #include "RISCVMachineFunctionInfo.h" 18 #include "RISCVRegisterInfo.h" 19 #include "RISCVSubtarget.h" 20 #include "RISCVTargetMachine.h" 21 #include "llvm/ADT/Statistic.h" 22 #include "llvm/CodeGen/CallingConvLower.h" 23 #include "llvm/CodeGen/MachineFrameInfo.h" 24 #include "llvm/CodeGen/MachineFunction.h" 25 #include "llvm/CodeGen/MachineInstrBuilder.h" 26 #include "llvm/CodeGen/MachineRegisterInfo.h" 27 #include "llvm/CodeGen/SelectionDAGISel.h" 28 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" 29 #include "llvm/CodeGen/ValueTypes.h" 30 #include "llvm/IR/DiagnosticInfo.h" 31 #include "llvm/IR/DiagnosticPrinter.h" 32 #include "llvm/Support/Debug.h" 33 #include "llvm/Support/ErrorHandling.h" 34 #include "llvm/Support/raw_ostream.h" 35 36 using namespace llvm; 37 38 #define DEBUG_TYPE "riscv-lower" 39 40 STATISTIC(NumTailCalls, "Number of tail calls"); 41 42 RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM, 43 const RISCVSubtarget &STI) 44 : TargetLowering(TM), Subtarget(STI) { 45 46 MVT XLenVT = Subtarget.getXLenVT(); 47 48 // Set up the register classes. 49 addRegisterClass(XLenVT, &RISCV::GPRRegClass); 50 51 if (Subtarget.hasStdExtF()) 52 addRegisterClass(MVT::f32, &RISCV::FPR32RegClass); 53 if (Subtarget.hasStdExtD()) 54 addRegisterClass(MVT::f64, &RISCV::FPR64RegClass); 55 56 // Compute derived properties from the register classes. 57 computeRegisterProperties(STI.getRegisterInfo()); 58 59 setStackPointerRegisterToSaveRestore(RISCV::X2); 60 61 for (auto N : {ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}) 62 setLoadExtAction(N, XLenVT, MVT::i1, Promote); 63 64 // TODO: add all necessary setOperationAction calls. 65 setOperationAction(ISD::DYNAMIC_STACKALLOC, XLenVT, Expand); 66 67 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 68 setOperationAction(ISD::BR_CC, XLenVT, Expand); 69 setOperationAction(ISD::SELECT, XLenVT, Custom); 70 setOperationAction(ISD::SELECT_CC, XLenVT, Expand); 71 72 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 73 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 74 75 setOperationAction(ISD::VASTART, MVT::Other, Custom); 76 setOperationAction(ISD::VAARG, MVT::Other, Expand); 77 setOperationAction(ISD::VACOPY, MVT::Other, Expand); 78 setOperationAction(ISD::VAEND, MVT::Other, Expand); 79 80 for (auto VT : {MVT::i1, MVT::i8, MVT::i16}) 81 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand); 82 83 if (!Subtarget.hasStdExtM()) { 84 setOperationAction(ISD::MUL, XLenVT, Expand); 85 setOperationAction(ISD::MULHS, XLenVT, Expand); 86 setOperationAction(ISD::MULHU, XLenVT, Expand); 87 setOperationAction(ISD::SDIV, XLenVT, Expand); 88 setOperationAction(ISD::UDIV, XLenVT, Expand); 89 setOperationAction(ISD::SREM, XLenVT, Expand); 90 setOperationAction(ISD::UREM, XLenVT, Expand); 91 } 92 93 setOperationAction(ISD::SDIVREM, XLenVT, Expand); 94 setOperationAction(ISD::UDIVREM, XLenVT, Expand); 95 setOperationAction(ISD::SMUL_LOHI, XLenVT, Expand); 96 setOperationAction(ISD::UMUL_LOHI, XLenVT, Expand); 97 98 setOperationAction(ISD::SHL_PARTS, XLenVT, Expand); 99 setOperationAction(ISD::SRL_PARTS, XLenVT, Expand); 100 setOperationAction(ISD::SRA_PARTS, XLenVT, Expand); 101 102 setOperationAction(ISD::ROTL, XLenVT, Expand); 103 setOperationAction(ISD::ROTR, XLenVT, Expand); 104 setOperationAction(ISD::BSWAP, XLenVT, Expand); 105 setOperationAction(ISD::CTTZ, XLenVT, Expand); 106 setOperationAction(ISD::CTLZ, XLenVT, Expand); 107 setOperationAction(ISD::CTPOP, XLenVT, Expand); 108 109 ISD::CondCode FPCCToExtend[] = { 110 ISD::SETOGT, ISD::SETOGE, ISD::SETONE, ISD::SETO, ISD::SETUEQ, 111 ISD::SETUGT, ISD::SETUGE, ISD::SETULT, ISD::SETULE, ISD::SETUNE, 112 ISD::SETGT, ISD::SETGE, ISD::SETNE}; 113 114 if (Subtarget.hasStdExtF()) { 115 setOperationAction(ISD::FMINNUM, MVT::f32, Legal); 116 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal); 117 for (auto CC : FPCCToExtend) 118 setCondCodeAction(CC, MVT::f32, Expand); 119 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand); 120 setOperationAction(ISD::SELECT, MVT::f32, Custom); 121 setOperationAction(ISD::BR_CC, MVT::f32, Expand); 122 } 123 124 if (Subtarget.hasStdExtD()) { 125 setOperationAction(ISD::FMINNUM, MVT::f64, Legal); 126 setOperationAction(ISD::FMAXNUM, MVT::f64, Legal); 127 for (auto CC : FPCCToExtend) 128 setCondCodeAction(CC, MVT::f64, Expand); 129 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand); 130 setOperationAction(ISD::SELECT, MVT::f64, Custom); 131 setOperationAction(ISD::BR_CC, MVT::f64, Expand); 132 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand); 133 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 134 } 135 136 setOperationAction(ISD::GlobalAddress, XLenVT, Custom); 137 setOperationAction(ISD::BlockAddress, XLenVT, Custom); 138 setOperationAction(ISD::ConstantPool, XLenVT, Custom); 139 140 if (Subtarget.hasStdExtA()) 141 setMaxAtomicSizeInBitsSupported(Subtarget.getXLen()); 142 else 143 setMaxAtomicSizeInBitsSupported(0); 144 145 setBooleanContents(ZeroOrOneBooleanContent); 146 147 // Function alignments (log2). 148 unsigned FunctionAlignment = Subtarget.hasStdExtC() ? 1 : 2; 149 setMinFunctionAlignment(FunctionAlignment); 150 setPrefFunctionAlignment(FunctionAlignment); 151 152 // Effectively disable jump table generation. 153 setMinimumJumpTableEntries(INT_MAX); 154 } 155 156 EVT RISCVTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &, 157 EVT VT) const { 158 if (!VT.isVector()) 159 return getPointerTy(DL); 160 return VT.changeVectorElementTypeToInteger(); 161 } 162 163 bool RISCVTargetLowering::isLegalAddressingMode(const DataLayout &DL, 164 const AddrMode &AM, Type *Ty, 165 unsigned AS, 166 Instruction *I) const { 167 // No global is ever allowed as a base. 168 if (AM.BaseGV) 169 return false; 170 171 // Require a 12-bit signed offset. 172 if (!isInt<12>(AM.BaseOffs)) 173 return false; 174 175 switch (AM.Scale) { 176 case 0: // "r+i" or just "i", depending on HasBaseReg. 177 break; 178 case 1: 179 if (!AM.HasBaseReg) // allow "r+i". 180 break; 181 return false; // disallow "r+r" or "r+r+i". 182 default: 183 return false; 184 } 185 186 return true; 187 } 188 189 bool RISCVTargetLowering::isLegalICmpImmediate(int64_t Imm) const { 190 return isInt<12>(Imm); 191 } 192 193 bool RISCVTargetLowering::isLegalAddImmediate(int64_t Imm) const { 194 return isInt<12>(Imm); 195 } 196 197 // On RV32, 64-bit integers are split into their high and low parts and held 198 // in two different registers, so the trunc is free since the low register can 199 // just be used. 200 bool RISCVTargetLowering::isTruncateFree(Type *SrcTy, Type *DstTy) const { 201 if (Subtarget.is64Bit() || !SrcTy->isIntegerTy() || !DstTy->isIntegerTy()) 202 return false; 203 unsigned SrcBits = SrcTy->getPrimitiveSizeInBits(); 204 unsigned DestBits = DstTy->getPrimitiveSizeInBits(); 205 return (SrcBits == 64 && DestBits == 32); 206 } 207 208 bool RISCVTargetLowering::isTruncateFree(EVT SrcVT, EVT DstVT) const { 209 if (Subtarget.is64Bit() || SrcVT.isVector() || DstVT.isVector() || 210 !SrcVT.isInteger() || !DstVT.isInteger()) 211 return false; 212 unsigned SrcBits = SrcVT.getSizeInBits(); 213 unsigned DestBits = DstVT.getSizeInBits(); 214 return (SrcBits == 64 && DestBits == 32); 215 } 216 217 bool RISCVTargetLowering::isZExtFree(SDValue Val, EVT VT2) const { 218 // Zexts are free if they can be combined with a load. 219 if (auto *LD = dyn_cast<LoadSDNode>(Val)) { 220 EVT MemVT = LD->getMemoryVT(); 221 if ((MemVT == MVT::i8 || MemVT == MVT::i16 || 222 (Subtarget.is64Bit() && MemVT == MVT::i32)) && 223 (LD->getExtensionType() == ISD::NON_EXTLOAD || 224 LD->getExtensionType() == ISD::ZEXTLOAD)) 225 return true; 226 } 227 228 return TargetLowering::isZExtFree(Val, VT2); 229 } 230 231 // Changes the condition code and swaps operands if necessary, so the SetCC 232 // operation matches one of the comparisons supported directly in the RISC-V 233 // ISA. 234 static void normaliseSetCC(SDValue &LHS, SDValue &RHS, ISD::CondCode &CC) { 235 switch (CC) { 236 default: 237 break; 238 case ISD::SETGT: 239 case ISD::SETLE: 240 case ISD::SETUGT: 241 case ISD::SETULE: 242 CC = ISD::getSetCCSwappedOperands(CC); 243 std::swap(LHS, RHS); 244 break; 245 } 246 } 247 248 // Return the RISC-V branch opcode that matches the given DAG integer 249 // condition code. The CondCode must be one of those supported by the RISC-V 250 // ISA (see normaliseSetCC). 251 static unsigned getBranchOpcodeForIntCondCode(ISD::CondCode CC) { 252 switch (CC) { 253 default: 254 llvm_unreachable("Unsupported CondCode"); 255 case ISD::SETEQ: 256 return RISCV::BEQ; 257 case ISD::SETNE: 258 return RISCV::BNE; 259 case ISD::SETLT: 260 return RISCV::BLT; 261 case ISD::SETGE: 262 return RISCV::BGE; 263 case ISD::SETULT: 264 return RISCV::BLTU; 265 case ISD::SETUGE: 266 return RISCV::BGEU; 267 } 268 } 269 270 SDValue RISCVTargetLowering::LowerOperation(SDValue Op, 271 SelectionDAG &DAG) const { 272 switch (Op.getOpcode()) { 273 default: 274 report_fatal_error("unimplemented operand"); 275 case ISD::GlobalAddress: 276 return lowerGlobalAddress(Op, DAG); 277 case ISD::BlockAddress: 278 return lowerBlockAddress(Op, DAG); 279 case ISD::ConstantPool: 280 return lowerConstantPool(Op, DAG); 281 case ISD::SELECT: 282 return lowerSELECT(Op, DAG); 283 case ISD::VASTART: 284 return lowerVASTART(Op, DAG); 285 case ISD::FRAMEADDR: 286 return LowerFRAMEADDR(Op, DAG); 287 case ISD::RETURNADDR: 288 return LowerRETURNADDR(Op, DAG); 289 } 290 } 291 292 SDValue RISCVTargetLowering::lowerGlobalAddress(SDValue Op, 293 SelectionDAG &DAG) const { 294 SDLoc DL(Op); 295 EVT Ty = Op.getValueType(); 296 GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op); 297 const GlobalValue *GV = N->getGlobal(); 298 int64_t Offset = N->getOffset(); 299 MVT XLenVT = Subtarget.getXLenVT(); 300 301 if (isPositionIndependent() || Subtarget.is64Bit()) 302 report_fatal_error("Unable to lowerGlobalAddress"); 303 // In order to maximise the opportunity for common subexpression elimination, 304 // emit a separate ADD node for the global address offset instead of folding 305 // it in the global address node. Later peephole optimisations may choose to 306 // fold it back in when profitable. 307 SDValue GAHi = DAG.getTargetGlobalAddress(GV, DL, Ty, 0, RISCVII::MO_HI); 308 SDValue GALo = DAG.getTargetGlobalAddress(GV, DL, Ty, 0, RISCVII::MO_LO); 309 SDValue MNHi = SDValue(DAG.getMachineNode(RISCV::LUI, DL, Ty, GAHi), 0); 310 SDValue MNLo = 311 SDValue(DAG.getMachineNode(RISCV::ADDI, DL, Ty, MNHi, GALo), 0); 312 if (Offset != 0) 313 return DAG.getNode(ISD::ADD, DL, Ty, MNLo, 314 DAG.getConstant(Offset, DL, XLenVT)); 315 return MNLo; 316 } 317 318 SDValue RISCVTargetLowering::lowerBlockAddress(SDValue Op, 319 SelectionDAG &DAG) const { 320 SDLoc DL(Op); 321 EVT Ty = Op.getValueType(); 322 BlockAddressSDNode *N = cast<BlockAddressSDNode>(Op); 323 const BlockAddress *BA = N->getBlockAddress(); 324 int64_t Offset = N->getOffset(); 325 326 if (isPositionIndependent() || Subtarget.is64Bit()) 327 report_fatal_error("Unable to lowerBlockAddress"); 328 329 SDValue BAHi = DAG.getTargetBlockAddress(BA, Ty, Offset, RISCVII::MO_HI); 330 SDValue BALo = DAG.getTargetBlockAddress(BA, Ty, Offset, RISCVII::MO_LO); 331 SDValue MNHi = SDValue(DAG.getMachineNode(RISCV::LUI, DL, Ty, BAHi), 0); 332 SDValue MNLo = 333 SDValue(DAG.getMachineNode(RISCV::ADDI, DL, Ty, MNHi, BALo), 0); 334 return MNLo; 335 } 336 337 SDValue RISCVTargetLowering::lowerConstantPool(SDValue Op, 338 SelectionDAG &DAG) const { 339 SDLoc DL(Op); 340 EVT Ty = Op.getValueType(); 341 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op); 342 const Constant *CPA = N->getConstVal(); 343 int64_t Offset = N->getOffset(); 344 unsigned Alignment = N->getAlignment(); 345 346 if (!isPositionIndependent()) { 347 SDValue CPAHi = 348 DAG.getTargetConstantPool(CPA, Ty, Alignment, Offset, RISCVII::MO_HI); 349 SDValue CPALo = 350 DAG.getTargetConstantPool(CPA, Ty, Alignment, Offset, RISCVII::MO_LO); 351 SDValue MNHi = SDValue(DAG.getMachineNode(RISCV::LUI, DL, Ty, CPAHi), 0); 352 SDValue MNLo = 353 SDValue(DAG.getMachineNode(RISCV::ADDI, DL, Ty, MNHi, CPALo), 0); 354 return MNLo; 355 } else { 356 report_fatal_error("Unable to lowerConstantPool"); 357 } 358 } 359 360 SDValue RISCVTargetLowering::lowerExternalSymbol(SDValue Op, 361 SelectionDAG &DAG) const { 362 SDLoc DL(Op); 363 EVT Ty = Op.getValueType(); 364 ExternalSymbolSDNode *N = cast<ExternalSymbolSDNode>(Op); 365 const char *Sym = N->getSymbol(); 366 367 // TODO: should also handle gp-relative loads. 368 369 if (isPositionIndependent() || Subtarget.is64Bit()) 370 report_fatal_error("Unable to lowerExternalSymbol"); 371 372 SDValue GAHi = DAG.getTargetExternalSymbol(Sym, Ty, RISCVII::MO_HI); 373 SDValue GALo = DAG.getTargetExternalSymbol(Sym, Ty, RISCVII::MO_LO); 374 SDValue MNHi = SDValue(DAG.getMachineNode(RISCV::LUI, DL, Ty, GAHi), 0); 375 SDValue MNLo = 376 SDValue(DAG.getMachineNode(RISCV::ADDI, DL, Ty, MNHi, GALo), 0); 377 return MNLo; 378 } 379 380 SDValue RISCVTargetLowering::lowerSELECT(SDValue Op, SelectionDAG &DAG) const { 381 SDValue CondV = Op.getOperand(0); 382 SDValue TrueV = Op.getOperand(1); 383 SDValue FalseV = Op.getOperand(2); 384 SDLoc DL(Op); 385 MVT XLenVT = Subtarget.getXLenVT(); 386 387 // If the result type is XLenVT and CondV is the output of a SETCC node 388 // which also operated on XLenVT inputs, then merge the SETCC node into the 389 // lowered RISCVISD::SELECT_CC to take advantage of the integer 390 // compare+branch instructions. i.e.: 391 // (select (setcc lhs, rhs, cc), truev, falsev) 392 // -> (riscvisd::select_cc lhs, rhs, cc, truev, falsev) 393 if (Op.getSimpleValueType() == XLenVT && CondV.getOpcode() == ISD::SETCC && 394 CondV.getOperand(0).getSimpleValueType() == XLenVT) { 395 SDValue LHS = CondV.getOperand(0); 396 SDValue RHS = CondV.getOperand(1); 397 auto CC = cast<CondCodeSDNode>(CondV.getOperand(2)); 398 ISD::CondCode CCVal = CC->get(); 399 400 normaliseSetCC(LHS, RHS, CCVal); 401 402 SDValue TargetCC = DAG.getConstant(CCVal, DL, XLenVT); 403 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue); 404 SDValue Ops[] = {LHS, RHS, TargetCC, TrueV, FalseV}; 405 return DAG.getNode(RISCVISD::SELECT_CC, DL, VTs, Ops); 406 } 407 408 // Otherwise: 409 // (select condv, truev, falsev) 410 // -> (riscvisd::select_cc condv, zero, setne, truev, falsev) 411 SDValue Zero = DAG.getConstant(0, DL, XLenVT); 412 SDValue SetNE = DAG.getConstant(ISD::SETNE, DL, XLenVT); 413 414 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue); 415 SDValue Ops[] = {CondV, Zero, SetNE, TrueV, FalseV}; 416 417 return DAG.getNode(RISCVISD::SELECT_CC, DL, VTs, Ops); 418 } 419 420 SDValue RISCVTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const { 421 MachineFunction &MF = DAG.getMachineFunction(); 422 RISCVMachineFunctionInfo *FuncInfo = MF.getInfo<RISCVMachineFunctionInfo>(); 423 424 SDLoc DL(Op); 425 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 426 getPointerTy(MF.getDataLayout())); 427 428 // vastart just stores the address of the VarArgsFrameIndex slot into the 429 // memory location argument. 430 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 431 return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1), 432 MachinePointerInfo(SV)); 433 } 434 435 SDValue RISCVTargetLowering::LowerFRAMEADDR(SDValue Op, 436 SelectionDAG &DAG) const { 437 const RISCVRegisterInfo &RI = *Subtarget.getRegisterInfo(); 438 MachineFunction &MF = DAG.getMachineFunction(); 439 MachineFrameInfo &MFI = MF.getFrameInfo(); 440 MFI.setFrameAddressIsTaken(true); 441 unsigned FrameReg = RI.getFrameRegister(MF); 442 int XLenInBytes = Subtarget.getXLen() / 8; 443 444 EVT VT = Op.getValueType(); 445 SDLoc DL(Op); 446 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), DL, FrameReg, VT); 447 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 448 while (Depth--) { 449 int Offset = -(XLenInBytes * 2); 450 SDValue Ptr = DAG.getNode(ISD::ADD, DL, VT, FrameAddr, 451 DAG.getIntPtrConstant(Offset, DL)); 452 FrameAddr = 453 DAG.getLoad(VT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo()); 454 } 455 return FrameAddr; 456 } 457 458 SDValue RISCVTargetLowering::LowerRETURNADDR(SDValue Op, 459 SelectionDAG &DAG) const { 460 const RISCVRegisterInfo &RI = *Subtarget.getRegisterInfo(); 461 MachineFunction &MF = DAG.getMachineFunction(); 462 MachineFrameInfo &MFI = MF.getFrameInfo(); 463 MFI.setReturnAddressIsTaken(true); 464 MVT XLenVT = Subtarget.getXLenVT(); 465 int XLenInBytes = Subtarget.getXLen() / 8; 466 467 if (verifyReturnAddressArgumentIsConstant(Op, DAG)) 468 return SDValue(); 469 470 EVT VT = Op.getValueType(); 471 SDLoc DL(Op); 472 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 473 if (Depth) { 474 int Off = -XLenInBytes; 475 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG); 476 SDValue Offset = DAG.getConstant(Off, DL, VT); 477 return DAG.getLoad(VT, DL, DAG.getEntryNode(), 478 DAG.getNode(ISD::ADD, DL, VT, FrameAddr, Offset), 479 MachinePointerInfo()); 480 } 481 482 // Return the value of the return address register, marking it an implicit 483 // live-in. 484 unsigned Reg = MF.addLiveIn(RI.getRARegister(), getRegClassFor(XLenVT)); 485 return DAG.getCopyFromReg(DAG.getEntryNode(), DL, Reg, XLenVT); 486 } 487 488 static MachineBasicBlock *emitSplitF64Pseudo(MachineInstr &MI, 489 MachineBasicBlock *BB) { 490 assert(MI.getOpcode() == RISCV::SplitF64Pseudo && "Unexpected instruction"); 491 492 MachineFunction &MF = *BB->getParent(); 493 DebugLoc DL = MI.getDebugLoc(); 494 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); 495 const TargetRegisterInfo *RI = MF.getSubtarget().getRegisterInfo(); 496 unsigned LoReg = MI.getOperand(0).getReg(); 497 unsigned HiReg = MI.getOperand(1).getReg(); 498 unsigned SrcReg = MI.getOperand(2).getReg(); 499 const TargetRegisterClass *SrcRC = &RISCV::FPR64RegClass; 500 int FI = MF.getInfo<RISCVMachineFunctionInfo>()->getMoveF64FrameIndex(); 501 502 TII.storeRegToStackSlot(*BB, MI, SrcReg, MI.getOperand(2).isKill(), FI, SrcRC, 503 RI); 504 MachineMemOperand *MMO = 505 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, FI), 506 MachineMemOperand::MOLoad, 8, 8); 507 BuildMI(*BB, MI, DL, TII.get(RISCV::LW), LoReg) 508 .addFrameIndex(FI) 509 .addImm(0) 510 .addMemOperand(MMO); 511 BuildMI(*BB, MI, DL, TII.get(RISCV::LW), HiReg) 512 .addFrameIndex(FI) 513 .addImm(4) 514 .addMemOperand(MMO); 515 MI.eraseFromParent(); // The pseudo instruction is gone now. 516 return BB; 517 } 518 519 static MachineBasicBlock *emitBuildPairF64Pseudo(MachineInstr &MI, 520 MachineBasicBlock *BB) { 521 assert(MI.getOpcode() == RISCV::BuildPairF64Pseudo && 522 "Unexpected instruction"); 523 524 MachineFunction &MF = *BB->getParent(); 525 DebugLoc DL = MI.getDebugLoc(); 526 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); 527 const TargetRegisterInfo *RI = MF.getSubtarget().getRegisterInfo(); 528 unsigned DstReg = MI.getOperand(0).getReg(); 529 unsigned LoReg = MI.getOperand(1).getReg(); 530 unsigned HiReg = MI.getOperand(2).getReg(); 531 const TargetRegisterClass *DstRC = &RISCV::FPR64RegClass; 532 int FI = MF.getInfo<RISCVMachineFunctionInfo>()->getMoveF64FrameIndex(); 533 534 MachineMemOperand *MMO = 535 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, FI), 536 MachineMemOperand::MOStore, 8, 8); 537 BuildMI(*BB, MI, DL, TII.get(RISCV::SW)) 538 .addReg(LoReg, getKillRegState(MI.getOperand(1).isKill())) 539 .addFrameIndex(FI) 540 .addImm(0) 541 .addMemOperand(MMO); 542 BuildMI(*BB, MI, DL, TII.get(RISCV::SW)) 543 .addReg(HiReg, getKillRegState(MI.getOperand(2).isKill())) 544 .addFrameIndex(FI) 545 .addImm(4) 546 .addMemOperand(MMO); 547 TII.loadRegFromStackSlot(*BB, MI, DstReg, FI, DstRC, RI); 548 MI.eraseFromParent(); // The pseudo instruction is gone now. 549 return BB; 550 } 551 552 MachineBasicBlock * 553 RISCVTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, 554 MachineBasicBlock *BB) const { 555 switch (MI.getOpcode()) { 556 default: 557 llvm_unreachable("Unexpected instr type to insert"); 558 case RISCV::Select_GPR_Using_CC_GPR: 559 case RISCV::Select_FPR32_Using_CC_GPR: 560 case RISCV::Select_FPR64_Using_CC_GPR: 561 break; 562 case RISCV::BuildPairF64Pseudo: 563 return emitBuildPairF64Pseudo(MI, BB); 564 case RISCV::SplitF64Pseudo: 565 return emitSplitF64Pseudo(MI, BB); 566 } 567 568 // To "insert" a SELECT instruction, we actually have to insert the triangle 569 // control-flow pattern. The incoming instruction knows the destination vreg 570 // to set, the condition code register to branch on, the true/false values to 571 // select between, and the condcode to use to select the appropriate branch. 572 // 573 // We produce the following control flow: 574 // HeadMBB 575 // | \ 576 // | IfFalseMBB 577 // | / 578 // TailMBB 579 const TargetInstrInfo &TII = *BB->getParent()->getSubtarget().getInstrInfo(); 580 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 581 DebugLoc DL = MI.getDebugLoc(); 582 MachineFunction::iterator I = ++BB->getIterator(); 583 584 MachineBasicBlock *HeadMBB = BB; 585 MachineFunction *F = BB->getParent(); 586 MachineBasicBlock *TailMBB = F->CreateMachineBasicBlock(LLVM_BB); 587 MachineBasicBlock *IfFalseMBB = F->CreateMachineBasicBlock(LLVM_BB); 588 589 F->insert(I, IfFalseMBB); 590 F->insert(I, TailMBB); 591 // Move all remaining instructions to TailMBB. 592 TailMBB->splice(TailMBB->begin(), HeadMBB, 593 std::next(MachineBasicBlock::iterator(MI)), HeadMBB->end()); 594 // Update machine-CFG edges by transferring all successors of the current 595 // block to the new block which will contain the Phi node for the select. 596 TailMBB->transferSuccessorsAndUpdatePHIs(HeadMBB); 597 // Set the successors for HeadMBB. 598 HeadMBB->addSuccessor(IfFalseMBB); 599 HeadMBB->addSuccessor(TailMBB); 600 601 // Insert appropriate branch. 602 unsigned LHS = MI.getOperand(1).getReg(); 603 unsigned RHS = MI.getOperand(2).getReg(); 604 auto CC = static_cast<ISD::CondCode>(MI.getOperand(3).getImm()); 605 unsigned Opcode = getBranchOpcodeForIntCondCode(CC); 606 607 BuildMI(HeadMBB, DL, TII.get(Opcode)) 608 .addReg(LHS) 609 .addReg(RHS) 610 .addMBB(TailMBB); 611 612 // IfFalseMBB just falls through to TailMBB. 613 IfFalseMBB->addSuccessor(TailMBB); 614 615 // %Result = phi [ %TrueValue, HeadMBB ], [ %FalseValue, IfFalseMBB ] 616 BuildMI(*TailMBB, TailMBB->begin(), DL, TII.get(RISCV::PHI), 617 MI.getOperand(0).getReg()) 618 .addReg(MI.getOperand(4).getReg()) 619 .addMBB(HeadMBB) 620 .addReg(MI.getOperand(5).getReg()) 621 .addMBB(IfFalseMBB); 622 623 MI.eraseFromParent(); // The pseudo instruction is gone now. 624 return TailMBB; 625 } 626 627 // Calling Convention Implementation. 628 // The expectations for frontend ABI lowering vary from target to target. 629 // Ideally, an LLVM frontend would be able to avoid worrying about many ABI 630 // details, but this is a longer term goal. For now, we simply try to keep the 631 // role of the frontend as simple and well-defined as possible. The rules can 632 // be summarised as: 633 // * Never split up large scalar arguments. We handle them here. 634 // * If a hardfloat calling convention is being used, and the struct may be 635 // passed in a pair of registers (fp+fp, int+fp), and both registers are 636 // available, then pass as two separate arguments. If either the GPRs or FPRs 637 // are exhausted, then pass according to the rule below. 638 // * If a struct could never be passed in registers or directly in a stack 639 // slot (as it is larger than 2*XLEN and the floating point rules don't 640 // apply), then pass it using a pointer with the byval attribute. 641 // * If a struct is less than 2*XLEN, then coerce to either a two-element 642 // word-sized array or a 2*XLEN scalar (depending on alignment). 643 // * The frontend can determine whether a struct is returned by reference or 644 // not based on its size and fields. If it will be returned by reference, the 645 // frontend must modify the prototype so a pointer with the sret annotation is 646 // passed as the first argument. This is not necessary for large scalar 647 // returns. 648 // * Struct return values and varargs should be coerced to structs containing 649 // register-size fields in the same situations they would be for fixed 650 // arguments. 651 652 static const MCPhysReg ArgGPRs[] = { 653 RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, 654 RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17 655 }; 656 657 // Pass a 2*XLEN argument that has been split into two XLEN values through 658 // registers or the stack as necessary. 659 static bool CC_RISCVAssign2XLen(unsigned XLen, CCState &State, CCValAssign VA1, 660 ISD::ArgFlagsTy ArgFlags1, unsigned ValNo2, 661 MVT ValVT2, MVT LocVT2, 662 ISD::ArgFlagsTy ArgFlags2) { 663 unsigned XLenInBytes = XLen / 8; 664 if (unsigned Reg = State.AllocateReg(ArgGPRs)) { 665 // At least one half can be passed via register. 666 State.addLoc(CCValAssign::getReg(VA1.getValNo(), VA1.getValVT(), Reg, 667 VA1.getLocVT(), CCValAssign::Full)); 668 } else { 669 // Both halves must be passed on the stack, with proper alignment. 670 unsigned StackAlign = std::max(XLenInBytes, ArgFlags1.getOrigAlign()); 671 State.addLoc( 672 CCValAssign::getMem(VA1.getValNo(), VA1.getValVT(), 673 State.AllocateStack(XLenInBytes, StackAlign), 674 VA1.getLocVT(), CCValAssign::Full)); 675 State.addLoc(CCValAssign::getMem( 676 ValNo2, ValVT2, State.AllocateStack(XLenInBytes, XLenInBytes), LocVT2, 677 CCValAssign::Full)); 678 return false; 679 } 680 681 if (unsigned Reg = State.AllocateReg(ArgGPRs)) { 682 // The second half can also be passed via register. 683 State.addLoc( 684 CCValAssign::getReg(ValNo2, ValVT2, Reg, LocVT2, CCValAssign::Full)); 685 } else { 686 // The second half is passed via the stack, without additional alignment. 687 State.addLoc(CCValAssign::getMem( 688 ValNo2, ValVT2, State.AllocateStack(XLenInBytes, XLenInBytes), LocVT2, 689 CCValAssign::Full)); 690 } 691 692 return false; 693 } 694 695 // Implements the RISC-V calling convention. Returns true upon failure. 696 static bool CC_RISCV(const DataLayout &DL, unsigned ValNo, MVT ValVT, MVT LocVT, 697 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, 698 CCState &State, bool IsFixed, bool IsRet, Type *OrigTy) { 699 unsigned XLen = DL.getLargestLegalIntTypeSizeInBits(); 700 assert(XLen == 32 || XLen == 64); 701 MVT XLenVT = XLen == 32 ? MVT::i32 : MVT::i64; 702 if (ValVT == MVT::f32) { 703 LocVT = MVT::i32; 704 LocInfo = CCValAssign::BCvt; 705 } 706 707 // Any return value split in to more than two values can't be returned 708 // directly. 709 if (IsRet && ValNo > 1) 710 return true; 711 712 // If this is a variadic argument, the RISC-V calling convention requires 713 // that it is assigned an 'even' or 'aligned' register if it has 8-byte 714 // alignment (RV32) or 16-byte alignment (RV64). An aligned register should 715 // be used regardless of whether the original argument was split during 716 // legalisation or not. The argument will not be passed by registers if the 717 // original type is larger than 2*XLEN, so the register alignment rule does 718 // not apply. 719 unsigned TwoXLenInBytes = (2 * XLen) / 8; 720 if (!IsFixed && ArgFlags.getOrigAlign() == TwoXLenInBytes && 721 DL.getTypeAllocSize(OrigTy) == TwoXLenInBytes) { 722 unsigned RegIdx = State.getFirstUnallocated(ArgGPRs); 723 // Skip 'odd' register if necessary. 724 if (RegIdx != array_lengthof(ArgGPRs) && RegIdx % 2 == 1) 725 State.AllocateReg(ArgGPRs); 726 } 727 728 SmallVectorImpl<CCValAssign> &PendingLocs = State.getPendingLocs(); 729 SmallVectorImpl<ISD::ArgFlagsTy> &PendingArgFlags = 730 State.getPendingArgFlags(); 731 732 assert(PendingLocs.size() == PendingArgFlags.size() && 733 "PendingLocs and PendingArgFlags out of sync"); 734 735 // Handle passing f64 on RV32D with a soft float ABI. 736 if (XLen == 32 && ValVT == MVT::f64) { 737 assert(!ArgFlags.isSplit() && PendingLocs.empty() && 738 "Can't lower f64 if it is split"); 739 // Depending on available argument GPRS, f64 may be passed in a pair of 740 // GPRs, split between a GPR and the stack, or passed completely on the 741 // stack. LowerCall/LowerFormalArguments/LowerReturn must recognise these 742 // cases. 743 unsigned Reg = State.AllocateReg(ArgGPRs); 744 LocVT = MVT::i32; 745 if (!Reg) { 746 unsigned StackOffset = State.AllocateStack(8, 8); 747 State.addLoc( 748 CCValAssign::getMem(ValNo, ValVT, StackOffset, LocVT, LocInfo)); 749 return false; 750 } 751 if (!State.AllocateReg(ArgGPRs)) 752 State.AllocateStack(4, 4); 753 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 754 return false; 755 } 756 757 // Split arguments might be passed indirectly, so keep track of the pending 758 // values. 759 if (ArgFlags.isSplit() || !PendingLocs.empty()) { 760 LocVT = XLenVT; 761 LocInfo = CCValAssign::Indirect; 762 PendingLocs.push_back( 763 CCValAssign::getPending(ValNo, ValVT, LocVT, LocInfo)); 764 PendingArgFlags.push_back(ArgFlags); 765 if (!ArgFlags.isSplitEnd()) { 766 return false; 767 } 768 } 769 770 // If the split argument only had two elements, it should be passed directly 771 // in registers or on the stack. 772 if (ArgFlags.isSplitEnd() && PendingLocs.size() <= 2) { 773 assert(PendingLocs.size() == 2 && "Unexpected PendingLocs.size()"); 774 // Apply the normal calling convention rules to the first half of the 775 // split argument. 776 CCValAssign VA = PendingLocs[0]; 777 ISD::ArgFlagsTy AF = PendingArgFlags[0]; 778 PendingLocs.clear(); 779 PendingArgFlags.clear(); 780 return CC_RISCVAssign2XLen(XLen, State, VA, AF, ValNo, ValVT, LocVT, 781 ArgFlags); 782 } 783 784 // Allocate to a register if possible, or else a stack slot. 785 unsigned Reg = State.AllocateReg(ArgGPRs); 786 unsigned StackOffset = Reg ? 0 : State.AllocateStack(XLen / 8, XLen / 8); 787 788 // If we reach this point and PendingLocs is non-empty, we must be at the 789 // end of a split argument that must be passed indirectly. 790 if (!PendingLocs.empty()) { 791 assert(ArgFlags.isSplitEnd() && "Expected ArgFlags.isSplitEnd()"); 792 assert(PendingLocs.size() > 2 && "Unexpected PendingLocs.size()"); 793 794 for (auto &It : PendingLocs) { 795 if (Reg) 796 It.convertToReg(Reg); 797 else 798 It.convertToMem(StackOffset); 799 State.addLoc(It); 800 } 801 PendingLocs.clear(); 802 PendingArgFlags.clear(); 803 return false; 804 } 805 806 assert(LocVT == XLenVT && "Expected an XLenVT at this stage"); 807 808 if (Reg) { 809 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 810 } else { 811 State.addLoc( 812 CCValAssign::getMem(ValNo, ValVT, StackOffset, LocVT, LocInfo)); 813 } 814 return false; 815 } 816 817 void RISCVTargetLowering::analyzeInputArgs( 818 MachineFunction &MF, CCState &CCInfo, 819 const SmallVectorImpl<ISD::InputArg> &Ins, bool IsRet) const { 820 unsigned NumArgs = Ins.size(); 821 FunctionType *FType = MF.getFunction().getFunctionType(); 822 823 for (unsigned i = 0; i != NumArgs; ++i) { 824 MVT ArgVT = Ins[i].VT; 825 ISD::ArgFlagsTy ArgFlags = Ins[i].Flags; 826 827 Type *ArgTy = nullptr; 828 if (IsRet) 829 ArgTy = FType->getReturnType(); 830 else if (Ins[i].isOrigArg()) 831 ArgTy = FType->getParamType(Ins[i].getOrigArgIndex()); 832 833 if (CC_RISCV(MF.getDataLayout(), i, ArgVT, ArgVT, CCValAssign::Full, 834 ArgFlags, CCInfo, /*IsRet=*/true, IsRet, ArgTy)) { 835 LLVM_DEBUG(dbgs() << "InputArg #" << i << " has unhandled type " 836 << EVT(ArgVT).getEVTString() << '\n'); 837 llvm_unreachable(nullptr); 838 } 839 } 840 } 841 842 void RISCVTargetLowering::analyzeOutputArgs( 843 MachineFunction &MF, CCState &CCInfo, 844 const SmallVectorImpl<ISD::OutputArg> &Outs, bool IsRet, 845 CallLoweringInfo *CLI) const { 846 unsigned NumArgs = Outs.size(); 847 848 for (unsigned i = 0; i != NumArgs; i++) { 849 MVT ArgVT = Outs[i].VT; 850 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags; 851 Type *OrigTy = CLI ? CLI->getArgs()[Outs[i].OrigArgIndex].Ty : nullptr; 852 853 if (CC_RISCV(MF.getDataLayout(), i, ArgVT, ArgVT, CCValAssign::Full, 854 ArgFlags, CCInfo, Outs[i].IsFixed, IsRet, OrigTy)) { 855 LLVM_DEBUG(dbgs() << "OutputArg #" << i << " has unhandled type " 856 << EVT(ArgVT).getEVTString() << "\n"); 857 llvm_unreachable(nullptr); 858 } 859 } 860 } 861 862 // The caller is responsible for loading the full value if the argument is 863 // passed with CCValAssign::Indirect. 864 static SDValue unpackFromRegLoc(SelectionDAG &DAG, SDValue Chain, 865 const CCValAssign &VA, const SDLoc &DL) { 866 MachineFunction &MF = DAG.getMachineFunction(); 867 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 868 EVT LocVT = VA.getLocVT(); 869 EVT ValVT = VA.getValVT(); 870 SDValue Val; 871 872 unsigned VReg = RegInfo.createVirtualRegister(&RISCV::GPRRegClass); 873 RegInfo.addLiveIn(VA.getLocReg(), VReg); 874 Val = DAG.getCopyFromReg(Chain, DL, VReg, LocVT); 875 876 switch (VA.getLocInfo()) { 877 default: 878 llvm_unreachable("Unexpected CCValAssign::LocInfo"); 879 case CCValAssign::Full: 880 case CCValAssign::Indirect: 881 break; 882 case CCValAssign::BCvt: 883 Val = DAG.getNode(ISD::BITCAST, DL, ValVT, Val); 884 break; 885 } 886 return Val; 887 } 888 889 // The caller is responsible for loading the full value if the argument is 890 // passed with CCValAssign::Indirect. 891 static SDValue unpackFromMemLoc(SelectionDAG &DAG, SDValue Chain, 892 const CCValAssign &VA, const SDLoc &DL) { 893 MachineFunction &MF = DAG.getMachineFunction(); 894 MachineFrameInfo &MFI = MF.getFrameInfo(); 895 EVT LocVT = VA.getLocVT(); 896 EVT ValVT = VA.getValVT(); 897 EVT PtrVT = MVT::getIntegerVT(DAG.getDataLayout().getPointerSizeInBits(0)); 898 int FI = MFI.CreateFixedObject(ValVT.getSizeInBits() / 8, 899 VA.getLocMemOffset(), /*Immutable=*/true); 900 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 901 SDValue Val; 902 903 ISD::LoadExtType ExtType; 904 switch (VA.getLocInfo()) { 905 default: 906 llvm_unreachable("Unexpected CCValAssign::LocInfo"); 907 case CCValAssign::Full: 908 case CCValAssign::Indirect: 909 ExtType = ISD::NON_EXTLOAD; 910 break; 911 } 912 Val = DAG.getExtLoad( 913 ExtType, DL, LocVT, Chain, FIN, 914 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), ValVT); 915 return Val; 916 } 917 918 static SDValue unpackF64OnRV32DSoftABI(SelectionDAG &DAG, SDValue Chain, 919 const CCValAssign &VA, const SDLoc &DL) { 920 assert(VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64 && 921 "Unexpected VA"); 922 MachineFunction &MF = DAG.getMachineFunction(); 923 MachineFrameInfo &MFI = MF.getFrameInfo(); 924 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 925 926 if (VA.isMemLoc()) { 927 // f64 is passed on the stack. 928 int FI = MFI.CreateFixedObject(8, VA.getLocMemOffset(), /*Immutable=*/true); 929 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32); 930 return DAG.getLoad(MVT::f64, DL, Chain, FIN, 931 MachinePointerInfo::getFixedStack(MF, FI)); 932 } 933 934 assert(VA.isRegLoc() && "Expected register VA assignment"); 935 936 unsigned LoVReg = RegInfo.createVirtualRegister(&RISCV::GPRRegClass); 937 RegInfo.addLiveIn(VA.getLocReg(), LoVReg); 938 SDValue Lo = DAG.getCopyFromReg(Chain, DL, LoVReg, MVT::i32); 939 SDValue Hi; 940 if (VA.getLocReg() == RISCV::X17) { 941 // Second half of f64 is passed on the stack. 942 int FI = MFI.CreateFixedObject(4, 0, /*Immutable=*/true); 943 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32); 944 Hi = DAG.getLoad(MVT::i32, DL, Chain, FIN, 945 MachinePointerInfo::getFixedStack(MF, FI)); 946 } else { 947 // Second half of f64 is passed in another GPR. 948 unsigned HiVReg = RegInfo.createVirtualRegister(&RISCV::GPRRegClass); 949 RegInfo.addLiveIn(VA.getLocReg() + 1, HiVReg); 950 Hi = DAG.getCopyFromReg(Chain, DL, HiVReg, MVT::i32); 951 } 952 return DAG.getNode(RISCVISD::BuildPairF64, DL, MVT::f64, Lo, Hi); 953 } 954 955 // Transform physical registers into virtual registers. 956 SDValue RISCVTargetLowering::LowerFormalArguments( 957 SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, 958 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, 959 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const { 960 961 switch (CallConv) { 962 default: 963 report_fatal_error("Unsupported calling convention"); 964 case CallingConv::C: 965 case CallingConv::Fast: 966 break; 967 } 968 969 MachineFunction &MF = DAG.getMachineFunction(); 970 971 const Function &Func = MF.getFunction(); 972 if (Func.hasFnAttribute("interrupt")) { 973 if (!Func.arg_empty()) 974 report_fatal_error( 975 "Functions with the interrupt attribute cannot have arguments!"); 976 977 StringRef Kind = 978 MF.getFunction().getFnAttribute("interrupt").getValueAsString(); 979 980 if (!(Kind == "user" || Kind == "supervisor" || Kind == "machine")) 981 report_fatal_error( 982 "Function interrupt attribute argument not supported!"); 983 } 984 985 EVT PtrVT = getPointerTy(DAG.getDataLayout()); 986 MVT XLenVT = Subtarget.getXLenVT(); 987 unsigned XLenInBytes = Subtarget.getXLen() / 8; 988 // Used with vargs to acumulate store chains. 989 std::vector<SDValue> OutChains; 990 991 // Assign locations to all of the incoming arguments. 992 SmallVector<CCValAssign, 16> ArgLocs; 993 CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext()); 994 analyzeInputArgs(MF, CCInfo, Ins, /*IsRet=*/false); 995 996 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 997 CCValAssign &VA = ArgLocs[i]; 998 assert(VA.getLocVT() == XLenVT && "Unhandled argument type"); 999 SDValue ArgValue; 1000 // Passing f64 on RV32D with a soft float ABI must be handled as a special 1001 // case. 1002 if (VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64) 1003 ArgValue = unpackF64OnRV32DSoftABI(DAG, Chain, VA, DL); 1004 else if (VA.isRegLoc()) 1005 ArgValue = unpackFromRegLoc(DAG, Chain, VA, DL); 1006 else 1007 ArgValue = unpackFromMemLoc(DAG, Chain, VA, DL); 1008 1009 if (VA.getLocInfo() == CCValAssign::Indirect) { 1010 // If the original argument was split and passed by reference (e.g. i128 1011 // on RV32), we need to load all parts of it here (using the same 1012 // address). 1013 InVals.push_back(DAG.getLoad(VA.getValVT(), DL, Chain, ArgValue, 1014 MachinePointerInfo())); 1015 unsigned ArgIndex = Ins[i].OrigArgIndex; 1016 assert(Ins[i].PartOffset == 0); 1017 while (i + 1 != e && Ins[i + 1].OrigArgIndex == ArgIndex) { 1018 CCValAssign &PartVA = ArgLocs[i + 1]; 1019 unsigned PartOffset = Ins[i + 1].PartOffset; 1020 SDValue Address = DAG.getNode(ISD::ADD, DL, PtrVT, ArgValue, 1021 DAG.getIntPtrConstant(PartOffset, DL)); 1022 InVals.push_back(DAG.getLoad(PartVA.getValVT(), DL, Chain, Address, 1023 MachinePointerInfo())); 1024 ++i; 1025 } 1026 continue; 1027 } 1028 InVals.push_back(ArgValue); 1029 } 1030 1031 if (IsVarArg) { 1032 ArrayRef<MCPhysReg> ArgRegs = makeArrayRef(ArgGPRs); 1033 unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs); 1034 const TargetRegisterClass *RC = &RISCV::GPRRegClass; 1035 MachineFrameInfo &MFI = MF.getFrameInfo(); 1036 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 1037 RISCVMachineFunctionInfo *RVFI = MF.getInfo<RISCVMachineFunctionInfo>(); 1038 1039 // Offset of the first variable argument from stack pointer, and size of 1040 // the vararg save area. For now, the varargs save area is either zero or 1041 // large enough to hold a0-a7. 1042 int VaArgOffset, VarArgsSaveSize; 1043 1044 // If all registers are allocated, then all varargs must be passed on the 1045 // stack and we don't need to save any argregs. 1046 if (ArgRegs.size() == Idx) { 1047 VaArgOffset = CCInfo.getNextStackOffset(); 1048 VarArgsSaveSize = 0; 1049 } else { 1050 VarArgsSaveSize = XLenInBytes * (ArgRegs.size() - Idx); 1051 VaArgOffset = -VarArgsSaveSize; 1052 } 1053 1054 // Record the frame index of the first variable argument 1055 // which is a value necessary to VASTART. 1056 int FI = MFI.CreateFixedObject(XLenInBytes, VaArgOffset, true); 1057 RVFI->setVarArgsFrameIndex(FI); 1058 1059 // If saving an odd number of registers then create an extra stack slot to 1060 // ensure that the frame pointer is 2*XLEN-aligned, which in turn ensures 1061 // offsets to even-numbered registered remain 2*XLEN-aligned. 1062 if (Idx % 2) { 1063 FI = MFI.CreateFixedObject(XLenInBytes, VaArgOffset - (int)XLenInBytes, 1064 true); 1065 VarArgsSaveSize += XLenInBytes; 1066 } 1067 1068 // Copy the integer registers that may have been used for passing varargs 1069 // to the vararg save area. 1070 for (unsigned I = Idx; I < ArgRegs.size(); 1071 ++I, VaArgOffset += XLenInBytes) { 1072 const unsigned Reg = RegInfo.createVirtualRegister(RC); 1073 RegInfo.addLiveIn(ArgRegs[I], Reg); 1074 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, XLenVT); 1075 FI = MFI.CreateFixedObject(XLenInBytes, VaArgOffset, true); 1076 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); 1077 SDValue Store = DAG.getStore(Chain, DL, ArgValue, PtrOff, 1078 MachinePointerInfo::getFixedStack(MF, FI)); 1079 cast<StoreSDNode>(Store.getNode()) 1080 ->getMemOperand() 1081 ->setValue((Value *)nullptr); 1082 OutChains.push_back(Store); 1083 } 1084 RVFI->setVarArgsSaveSize(VarArgsSaveSize); 1085 } 1086 1087 // All stores are grouped in one node to allow the matching between 1088 // the size of Ins and InVals. This only happens for vararg functions. 1089 if (!OutChains.empty()) { 1090 OutChains.push_back(Chain); 1091 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains); 1092 } 1093 1094 return Chain; 1095 } 1096 1097 /// IsEligibleForTailCallOptimization - Check whether the call is eligible 1098 /// for tail call optimization. 1099 /// Note: This is modelled after ARM's IsEligibleForTailCallOptimization. 1100 bool RISCVTargetLowering::IsEligibleForTailCallOptimization( 1101 CCState &CCInfo, CallLoweringInfo &CLI, MachineFunction &MF, 1102 const SmallVector<CCValAssign, 16> &ArgLocs) const { 1103 1104 auto &Callee = CLI.Callee; 1105 auto CalleeCC = CLI.CallConv; 1106 auto IsVarArg = CLI.IsVarArg; 1107 auto &Outs = CLI.Outs; 1108 auto &Caller = MF.getFunction(); 1109 auto CallerCC = Caller.getCallingConv(); 1110 1111 // Do not tail call opt functions with "disable-tail-calls" attribute. 1112 if (Caller.getFnAttribute("disable-tail-calls").getValueAsString() == "true") 1113 return false; 1114 1115 // Exception-handling functions need a special set of instructions to 1116 // indicate a return to the hardware. Tail-calling another function would 1117 // probably break this. 1118 // TODO: The "interrupt" attribute isn't currently defined by RISC-V. This 1119 // should be expanded as new function attributes are introduced. 1120 if (Caller.hasFnAttribute("interrupt")) 1121 return false; 1122 1123 // Do not tail call opt functions with varargs. 1124 if (IsVarArg) 1125 return false; 1126 1127 // Do not tail call opt if the stack is used to pass parameters. 1128 if (CCInfo.getNextStackOffset() != 0) 1129 return false; 1130 1131 // Do not tail call opt if any parameters need to be passed indirectly. 1132 // Since long doubles (fp128) and i128 are larger than 2*XLEN, they are 1133 // passed indirectly. So the address of the value will be passed in a 1134 // register, or if not available, then the address is put on the stack. In 1135 // order to pass indirectly, space on the stack often needs to be allocated 1136 // in order to store the value. In this case the CCInfo.getNextStackOffset() 1137 // != 0 check is not enough and we need to check if any CCValAssign ArgsLocs 1138 // are passed CCValAssign::Indirect. 1139 for (auto &VA : ArgLocs) 1140 if (VA.getLocInfo() == CCValAssign::Indirect) 1141 return false; 1142 1143 // Do not tail call opt if either caller or callee uses struct return 1144 // semantics. 1145 auto IsCallerStructRet = Caller.hasStructRetAttr(); 1146 auto IsCalleeStructRet = Outs.empty() ? false : Outs[0].Flags.isSRet(); 1147 if (IsCallerStructRet || IsCalleeStructRet) 1148 return false; 1149 1150 // Externally-defined functions with weak linkage should not be 1151 // tail-called. The behaviour of branch instructions in this situation (as 1152 // used for tail calls) is implementation-defined, so we cannot rely on the 1153 // linker replacing the tail call with a return. 1154 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 1155 const GlobalValue *GV = G->getGlobal(); 1156 if (GV->hasExternalWeakLinkage()) 1157 return false; 1158 } 1159 1160 // The callee has to preserve all registers the caller needs to preserve. 1161 const RISCVRegisterInfo *TRI = Subtarget.getRegisterInfo(); 1162 const uint32_t *CallerPreserved = TRI->getCallPreservedMask(MF, CallerCC); 1163 if (CalleeCC != CallerCC) { 1164 const uint32_t *CalleePreserved = TRI->getCallPreservedMask(MF, CalleeCC); 1165 if (!TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved)) 1166 return false; 1167 } 1168 1169 // Byval parameters hand the function a pointer directly into the stack area 1170 // we want to reuse during a tail call. Working around this *is* possible 1171 // but less efficient and uglier in LowerCall. 1172 for (auto &Arg : Outs) 1173 if (Arg.Flags.isByVal()) 1174 return false; 1175 1176 return true; 1177 } 1178 1179 // Lower a call to a callseq_start + CALL + callseq_end chain, and add input 1180 // and output parameter nodes. 1181 SDValue RISCVTargetLowering::LowerCall(CallLoweringInfo &CLI, 1182 SmallVectorImpl<SDValue> &InVals) const { 1183 SelectionDAG &DAG = CLI.DAG; 1184 SDLoc &DL = CLI.DL; 1185 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; 1186 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals; 1187 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; 1188 SDValue Chain = CLI.Chain; 1189 SDValue Callee = CLI.Callee; 1190 bool &IsTailCall = CLI.IsTailCall; 1191 CallingConv::ID CallConv = CLI.CallConv; 1192 bool IsVarArg = CLI.IsVarArg; 1193 EVT PtrVT = getPointerTy(DAG.getDataLayout()); 1194 MVT XLenVT = Subtarget.getXLenVT(); 1195 1196 MachineFunction &MF = DAG.getMachineFunction(); 1197 1198 // Analyze the operands of the call, assigning locations to each operand. 1199 SmallVector<CCValAssign, 16> ArgLocs; 1200 CCState ArgCCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext()); 1201 analyzeOutputArgs(MF, ArgCCInfo, Outs, /*IsRet=*/false, &CLI); 1202 1203 // Check if it's really possible to do a tail call. 1204 if (IsTailCall) 1205 IsTailCall = IsEligibleForTailCallOptimization(ArgCCInfo, CLI, MF, 1206 ArgLocs); 1207 1208 if (IsTailCall) 1209 ++NumTailCalls; 1210 else if (CLI.CS && CLI.CS.isMustTailCall()) 1211 report_fatal_error("failed to perform tail call elimination on a call " 1212 "site marked musttail"); 1213 1214 // Get a count of how many bytes are to be pushed on the stack. 1215 unsigned NumBytes = ArgCCInfo.getNextStackOffset(); 1216 1217 // Create local copies for byval args 1218 SmallVector<SDValue, 8> ByValArgs; 1219 for (unsigned i = 0, e = Outs.size(); i != e; ++i) { 1220 ISD::ArgFlagsTy Flags = Outs[i].Flags; 1221 if (!Flags.isByVal()) 1222 continue; 1223 1224 SDValue Arg = OutVals[i]; 1225 unsigned Size = Flags.getByValSize(); 1226 unsigned Align = Flags.getByValAlign(); 1227 1228 int FI = MF.getFrameInfo().CreateStackObject(Size, Align, /*isSS=*/false); 1229 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); 1230 SDValue SizeNode = DAG.getConstant(Size, DL, XLenVT); 1231 1232 Chain = DAG.getMemcpy(Chain, DL, FIPtr, Arg, SizeNode, Align, 1233 /*IsVolatile=*/false, 1234 /*AlwaysInline=*/false, 1235 IsTailCall, MachinePointerInfo(), 1236 MachinePointerInfo()); 1237 ByValArgs.push_back(FIPtr); 1238 } 1239 1240 if (!IsTailCall) 1241 Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, CLI.DL); 1242 1243 // Copy argument values to their designated locations. 1244 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 1245 SmallVector<SDValue, 8> MemOpChains; 1246 SDValue StackPtr; 1247 for (unsigned i = 0, j = 0, e = ArgLocs.size(); i != e; ++i) { 1248 CCValAssign &VA = ArgLocs[i]; 1249 SDValue ArgValue = OutVals[i]; 1250 ISD::ArgFlagsTy Flags = Outs[i].Flags; 1251 1252 // Handle passing f64 on RV32D with a soft float ABI as a special case. 1253 bool IsF64OnRV32DSoftABI = 1254 VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64; 1255 if (IsF64OnRV32DSoftABI && VA.isRegLoc()) { 1256 SDValue SplitF64 = DAG.getNode( 1257 RISCVISD::SplitF64, DL, DAG.getVTList(MVT::i32, MVT::i32), ArgValue); 1258 SDValue Lo = SplitF64.getValue(0); 1259 SDValue Hi = SplitF64.getValue(1); 1260 1261 unsigned RegLo = VA.getLocReg(); 1262 RegsToPass.push_back(std::make_pair(RegLo, Lo)); 1263 1264 if (RegLo == RISCV::X17) { 1265 // Second half of f64 is passed on the stack. 1266 // Work out the address of the stack slot. 1267 if (!StackPtr.getNode()) 1268 StackPtr = DAG.getCopyFromReg(Chain, DL, RISCV::X2, PtrVT); 1269 // Emit the store. 1270 MemOpChains.push_back( 1271 DAG.getStore(Chain, DL, Hi, StackPtr, MachinePointerInfo())); 1272 } else { 1273 // Second half of f64 is passed in another GPR. 1274 unsigned RegHigh = RegLo + 1; 1275 RegsToPass.push_back(std::make_pair(RegHigh, Hi)); 1276 } 1277 continue; 1278 } 1279 1280 // IsF64OnRV32DSoftABI && VA.isMemLoc() is handled below in the same way 1281 // as any other MemLoc. 1282 1283 // Promote the value if needed. 1284 // For now, only handle fully promoted and indirect arguments. 1285 switch (VA.getLocInfo()) { 1286 case CCValAssign::Full: 1287 break; 1288 case CCValAssign::BCvt: 1289 ArgValue = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), ArgValue); 1290 break; 1291 case CCValAssign::Indirect: { 1292 // Store the argument in a stack slot and pass its address. 1293 SDValue SpillSlot = DAG.CreateStackTemporary(Outs[i].ArgVT); 1294 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex(); 1295 MemOpChains.push_back( 1296 DAG.getStore(Chain, DL, ArgValue, SpillSlot, 1297 MachinePointerInfo::getFixedStack(MF, FI))); 1298 // If the original argument was split (e.g. i128), we need 1299 // to store all parts of it here (and pass just one address). 1300 unsigned ArgIndex = Outs[i].OrigArgIndex; 1301 assert(Outs[i].PartOffset == 0); 1302 while (i + 1 != e && Outs[i + 1].OrigArgIndex == ArgIndex) { 1303 SDValue PartValue = OutVals[i + 1]; 1304 unsigned PartOffset = Outs[i + 1].PartOffset; 1305 SDValue Address = DAG.getNode(ISD::ADD, DL, PtrVT, SpillSlot, 1306 DAG.getIntPtrConstant(PartOffset, DL)); 1307 MemOpChains.push_back( 1308 DAG.getStore(Chain, DL, PartValue, Address, 1309 MachinePointerInfo::getFixedStack(MF, FI))); 1310 ++i; 1311 } 1312 ArgValue = SpillSlot; 1313 break; 1314 } 1315 default: 1316 llvm_unreachable("Unknown loc info!"); 1317 } 1318 1319 // Use local copy if it is a byval arg. 1320 if (Flags.isByVal()) 1321 ArgValue = ByValArgs[j++]; 1322 1323 if (VA.isRegLoc()) { 1324 // Queue up the argument copies and emit them at the end. 1325 RegsToPass.push_back(std::make_pair(VA.getLocReg(), ArgValue)); 1326 } else { 1327 assert(VA.isMemLoc() && "Argument not register or memory"); 1328 assert(!IsTailCall && "Tail call not allowed if stack is used " 1329 "for passing parameters"); 1330 1331 // Work out the address of the stack slot. 1332 if (!StackPtr.getNode()) 1333 StackPtr = DAG.getCopyFromReg(Chain, DL, RISCV::X2, PtrVT); 1334 SDValue Address = 1335 DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr, 1336 DAG.getIntPtrConstant(VA.getLocMemOffset(), DL)); 1337 1338 // Emit the store. 1339 MemOpChains.push_back( 1340 DAG.getStore(Chain, DL, ArgValue, Address, MachinePointerInfo())); 1341 } 1342 } 1343 1344 // Join the stores, which are independent of one another. 1345 if (!MemOpChains.empty()) 1346 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains); 1347 1348 SDValue Glue; 1349 1350 // Build a sequence of copy-to-reg nodes, chained and glued together. 1351 for (auto &Reg : RegsToPass) { 1352 Chain = DAG.getCopyToReg(Chain, DL, Reg.first, Reg.second, Glue); 1353 Glue = Chain.getValue(1); 1354 } 1355 1356 // If the callee is a GlobalAddress/ExternalSymbol node, turn it into a 1357 // TargetGlobalAddress/TargetExternalSymbol node so that legalize won't 1358 // split it and then direct call can be matched by PseudoCALL. 1359 if (GlobalAddressSDNode *S = dyn_cast<GlobalAddressSDNode>(Callee)) { 1360 Callee = DAG.getTargetGlobalAddress(S->getGlobal(), DL, PtrVT, 0, 0); 1361 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 1362 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), PtrVT, 0); 1363 } 1364 1365 // The first call operand is the chain and the second is the target address. 1366 SmallVector<SDValue, 8> Ops; 1367 Ops.push_back(Chain); 1368 Ops.push_back(Callee); 1369 1370 // Add argument registers to the end of the list so that they are 1371 // known live into the call. 1372 for (auto &Reg : RegsToPass) 1373 Ops.push_back(DAG.getRegister(Reg.first, Reg.second.getValueType())); 1374 1375 if (!IsTailCall) { 1376 // Add a register mask operand representing the call-preserved registers. 1377 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo(); 1378 const uint32_t *Mask = TRI->getCallPreservedMask(MF, CallConv); 1379 assert(Mask && "Missing call preserved mask for calling convention"); 1380 Ops.push_back(DAG.getRegisterMask(Mask)); 1381 } 1382 1383 // Glue the call to the argument copies, if any. 1384 if (Glue.getNode()) 1385 Ops.push_back(Glue); 1386 1387 // Emit the call. 1388 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 1389 1390 if (IsTailCall) { 1391 MF.getFrameInfo().setHasTailCall(); 1392 return DAG.getNode(RISCVISD::TAIL, DL, NodeTys, Ops); 1393 } 1394 1395 Chain = DAG.getNode(RISCVISD::CALL, DL, NodeTys, Ops); 1396 Glue = Chain.getValue(1); 1397 1398 // Mark the end of the call, which is glued to the call itself. 1399 Chain = DAG.getCALLSEQ_END(Chain, 1400 DAG.getConstant(NumBytes, DL, PtrVT, true), 1401 DAG.getConstant(0, DL, PtrVT, true), 1402 Glue, DL); 1403 Glue = Chain.getValue(1); 1404 1405 // Assign locations to each value returned by this call. 1406 SmallVector<CCValAssign, 16> RVLocs; 1407 CCState RetCCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext()); 1408 analyzeInputArgs(MF, RetCCInfo, Ins, /*IsRet=*/true); 1409 1410 // Copy all of the result registers out of their specified physreg. 1411 for (auto &VA : RVLocs) { 1412 // Copy the value out 1413 SDValue RetValue = 1414 DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), VA.getLocVT(), Glue); 1415 // Glue the RetValue to the end of the call sequence 1416 Chain = RetValue.getValue(1); 1417 Glue = RetValue.getValue(2); 1418 if (VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64) { 1419 assert(VA.getLocReg() == ArgGPRs[0] && "Unexpected reg assignment"); 1420 SDValue RetValue2 = 1421 DAG.getCopyFromReg(Chain, DL, ArgGPRs[1], MVT::i32, Glue); 1422 Chain = RetValue2.getValue(1); 1423 Glue = RetValue2.getValue(2); 1424 RetValue = DAG.getNode(RISCVISD::BuildPairF64, DL, MVT::f64, RetValue, 1425 RetValue2); 1426 } 1427 1428 switch (VA.getLocInfo()) { 1429 default: 1430 llvm_unreachable("Unknown loc info!"); 1431 case CCValAssign::Full: 1432 break; 1433 case CCValAssign::BCvt: 1434 RetValue = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), RetValue); 1435 break; 1436 } 1437 1438 InVals.push_back(RetValue); 1439 } 1440 1441 return Chain; 1442 } 1443 1444 bool RISCVTargetLowering::CanLowerReturn( 1445 CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg, 1446 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const { 1447 SmallVector<CCValAssign, 16> RVLocs; 1448 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context); 1449 for (unsigned i = 0, e = Outs.size(); i != e; ++i) { 1450 MVT VT = Outs[i].VT; 1451 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags; 1452 if (CC_RISCV(MF.getDataLayout(), i, VT, VT, CCValAssign::Full, ArgFlags, 1453 CCInfo, /*IsFixed=*/true, /*IsRet=*/true, nullptr)) 1454 return false; 1455 } 1456 return true; 1457 } 1458 1459 static SDValue packIntoRegLoc(SelectionDAG &DAG, SDValue Val, 1460 const CCValAssign &VA, const SDLoc &DL) { 1461 EVT LocVT = VA.getLocVT(); 1462 1463 switch (VA.getLocInfo()) { 1464 default: 1465 llvm_unreachable("Unexpected CCValAssign::LocInfo"); 1466 case CCValAssign::Full: 1467 break; 1468 case CCValAssign::BCvt: 1469 Val = DAG.getNode(ISD::BITCAST, DL, LocVT, Val); 1470 break; 1471 } 1472 return Val; 1473 } 1474 1475 SDValue 1476 RISCVTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, 1477 bool IsVarArg, 1478 const SmallVectorImpl<ISD::OutputArg> &Outs, 1479 const SmallVectorImpl<SDValue> &OutVals, 1480 const SDLoc &DL, SelectionDAG &DAG) const { 1481 // Stores the assignment of the return value to a location. 1482 SmallVector<CCValAssign, 16> RVLocs; 1483 1484 // Info about the registers and stack slot. 1485 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs, 1486 *DAG.getContext()); 1487 1488 analyzeOutputArgs(DAG.getMachineFunction(), CCInfo, Outs, /*IsRet=*/true, 1489 nullptr); 1490 1491 SDValue Glue; 1492 SmallVector<SDValue, 4> RetOps(1, Chain); 1493 1494 // Copy the result values into the output registers. 1495 for (unsigned i = 0, e = RVLocs.size(); i < e; ++i) { 1496 SDValue Val = OutVals[i]; 1497 CCValAssign &VA = RVLocs[i]; 1498 assert(VA.isRegLoc() && "Can only return in registers!"); 1499 1500 if (VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64) { 1501 // Handle returning f64 on RV32D with a soft float ABI. 1502 assert(VA.isRegLoc() && "Expected return via registers"); 1503 SDValue SplitF64 = DAG.getNode(RISCVISD::SplitF64, DL, 1504 DAG.getVTList(MVT::i32, MVT::i32), Val); 1505 SDValue Lo = SplitF64.getValue(0); 1506 SDValue Hi = SplitF64.getValue(1); 1507 unsigned RegLo = VA.getLocReg(); 1508 unsigned RegHi = RegLo + 1; 1509 Chain = DAG.getCopyToReg(Chain, DL, RegLo, Lo, Glue); 1510 Glue = Chain.getValue(1); 1511 RetOps.push_back(DAG.getRegister(RegLo, MVT::i32)); 1512 Chain = DAG.getCopyToReg(Chain, DL, RegHi, Hi, Glue); 1513 Glue = Chain.getValue(1); 1514 RetOps.push_back(DAG.getRegister(RegHi, MVT::i32)); 1515 } else { 1516 // Handle a 'normal' return. 1517 Val = packIntoRegLoc(DAG, Val, VA, DL); 1518 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Glue); 1519 1520 // Guarantee that all emitted copies are stuck together. 1521 Glue = Chain.getValue(1); 1522 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); 1523 } 1524 } 1525 1526 RetOps[0] = Chain; // Update chain. 1527 1528 // Add the glue node if we have it. 1529 if (Glue.getNode()) { 1530 RetOps.push_back(Glue); 1531 } 1532 1533 // Interrupt service routines use different return instructions. 1534 const Function &Func = DAG.getMachineFunction().getFunction(); 1535 if (Func.hasFnAttribute("interrupt")) { 1536 if (!Func.getReturnType()->isVoidTy()) 1537 report_fatal_error( 1538 "Functions with the interrupt attribute must have void return type!"); 1539 1540 MachineFunction &MF = DAG.getMachineFunction(); 1541 StringRef Kind = 1542 MF.getFunction().getFnAttribute("interrupt").getValueAsString(); 1543 1544 unsigned RetOpc; 1545 if (Kind == "user") 1546 RetOpc = RISCVISD::URET_FLAG; 1547 else if (Kind == "supervisor") 1548 RetOpc = RISCVISD::SRET_FLAG; 1549 else 1550 RetOpc = RISCVISD::MRET_FLAG; 1551 1552 return DAG.getNode(RetOpc, DL, MVT::Other, RetOps); 1553 } 1554 1555 return DAG.getNode(RISCVISD::RET_FLAG, DL, MVT::Other, RetOps); 1556 } 1557 1558 const char *RISCVTargetLowering::getTargetNodeName(unsigned Opcode) const { 1559 switch ((RISCVISD::NodeType)Opcode) { 1560 case RISCVISD::FIRST_NUMBER: 1561 break; 1562 case RISCVISD::RET_FLAG: 1563 return "RISCVISD::RET_FLAG"; 1564 case RISCVISD::URET_FLAG: 1565 return "RISCVISD::URET_FLAG"; 1566 case RISCVISD::SRET_FLAG: 1567 return "RISCVISD::SRET_FLAG"; 1568 case RISCVISD::MRET_FLAG: 1569 return "RISCVISD::MRET_FLAG"; 1570 case RISCVISD::CALL: 1571 return "RISCVISD::CALL"; 1572 case RISCVISD::SELECT_CC: 1573 return "RISCVISD::SELECT_CC"; 1574 case RISCVISD::BuildPairF64: 1575 return "RISCVISD::BuildPairF64"; 1576 case RISCVISD::SplitF64: 1577 return "RISCVISD::SplitF64"; 1578 case RISCVISD::TAIL: 1579 return "RISCVISD::TAIL"; 1580 } 1581 return nullptr; 1582 } 1583 1584 std::pair<unsigned, const TargetRegisterClass *> 1585 RISCVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 1586 StringRef Constraint, 1587 MVT VT) const { 1588 // First, see if this is a constraint that directly corresponds to a 1589 // RISCV register class. 1590 if (Constraint.size() == 1) { 1591 switch (Constraint[0]) { 1592 case 'r': 1593 return std::make_pair(0U, &RISCV::GPRRegClass); 1594 default: 1595 break; 1596 } 1597 } 1598 1599 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT); 1600 } 1601 1602 Instruction *RISCVTargetLowering::emitLeadingFence(IRBuilder<> &Builder, 1603 Instruction *Inst, 1604 AtomicOrdering Ord) const { 1605 if (isa<LoadInst>(Inst) && Ord == AtomicOrdering::SequentiallyConsistent) 1606 return Builder.CreateFence(Ord); 1607 if (isa<StoreInst>(Inst) && isReleaseOrStronger(Ord)) 1608 return Builder.CreateFence(AtomicOrdering::Release); 1609 return nullptr; 1610 } 1611 1612 Instruction *RISCVTargetLowering::emitTrailingFence(IRBuilder<> &Builder, 1613 Instruction *Inst, 1614 AtomicOrdering Ord) const { 1615 if (isa<LoadInst>(Inst) && isAcquireOrStronger(Ord)) 1616 return Builder.CreateFence(AtomicOrdering::Acquire); 1617 return nullptr; 1618 } 1619
