1 //===-- RISCVISelLowering.h - RISCV DAG Lowering Interface ------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the interfaces that RISCV uses to lower LLVM code into a 11 // selection DAG. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef LLVM_LIB_TARGET_RISCV_RISCVISELLOWERING_H 16 #define LLVM_LIB_TARGET_RISCV_RISCVISELLOWERING_H 17 18 #include "RISCV.h" 19 #include "llvm/CodeGen/SelectionDAG.h" 20 #include "llvm/CodeGen/TargetLowering.h" 21 22 namespace llvm { 23 class RISCVSubtarget; 24 namespace RISCVISD { 25 enum NodeType : unsigned { 26 FIRST_NUMBER = ISD::BUILTIN_OP_END, 27 RET_FLAG, 28 URET_FLAG, 29 SRET_FLAG, 30 MRET_FLAG, 31 CALL, 32 SELECT_CC, 33 BuildPairF64, 34 SplitF64, 35 TAIL 36 }; 37 } 38 39 class RISCVTargetLowering : public TargetLowering { 40 const RISCVSubtarget &Subtarget; 41 42 public: 43 explicit RISCVTargetLowering(const TargetMachine &TM, 44 const RISCVSubtarget &STI); 45 46 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, 47 unsigned AS, 48 Instruction *I = nullptr) const override; 49 bool isLegalICmpImmediate(int64_t Imm) const override; 50 bool isLegalAddImmediate(int64_t Imm) const override; 51 bool isTruncateFree(Type *SrcTy, Type *DstTy) const override; 52 bool isTruncateFree(EVT SrcVT, EVT DstVT) const override; 53 bool isZExtFree(SDValue Val, EVT VT2) const override; 54 55 // Provide custom lowering hooks for some operations. 56 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 57 58 // This method returns the name of a target specific DAG node. 59 const char *getTargetNodeName(unsigned Opcode) const override; 60 61 std::pair<unsigned, const TargetRegisterClass *> 62 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 63 StringRef Constraint, MVT VT) const override; 64 65 MachineBasicBlock * 66 EmitInstrWithCustomInserter(MachineInstr &MI, 67 MachineBasicBlock *BB) const override; 68 69 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, 70 EVT VT) const override; 71 72 bool shouldInsertFencesForAtomic(const Instruction *I) const override { 73 return isa<LoadInst>(I) || isa<StoreInst>(I); 74 } 75 Instruction *emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst, 76 AtomicOrdering Ord) const override; 77 Instruction *emitTrailingFence(IRBuilder<> &Builder, Instruction *Inst, 78 AtomicOrdering Ord) const override; 79 80 private: 81 void analyzeInputArgs(MachineFunction &MF, CCState &CCInfo, 82 const SmallVectorImpl<ISD::InputArg> &Ins, 83 bool IsRet) const; 84 void analyzeOutputArgs(MachineFunction &MF, CCState &CCInfo, 85 const SmallVectorImpl<ISD::OutputArg> &Outs, 86 bool IsRet, CallLoweringInfo *CLI) const; 87 // Lower incoming arguments, copy physregs into vregs 88 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, 89 bool IsVarArg, 90 const SmallVectorImpl<ISD::InputArg> &Ins, 91 const SDLoc &DL, SelectionDAG &DAG, 92 SmallVectorImpl<SDValue> &InVals) const override; 93 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, 94 bool IsVarArg, 95 const SmallVectorImpl<ISD::OutputArg> &Outs, 96 LLVMContext &Context) const override; 97 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, 98 const SmallVectorImpl<ISD::OutputArg> &Outs, 99 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL, 100 SelectionDAG &DAG) const override; 101 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, 102 SmallVectorImpl<SDValue> &InVals) const override; 103 bool shouldConvertConstantLoadToIntImm(const APInt &Imm, 104 Type *Ty) const override { 105 return true; 106 } 107 SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 108 SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 109 SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 110 SDValue lowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const; 111 SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const; 112 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const; 113 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 114 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 115 116 bool IsEligibleForTailCallOptimization(CCState &CCInfo, 117 CallLoweringInfo &CLI, MachineFunction &MF, 118 const SmallVector<CCValAssign, 16> &ArgLocs) const; 119 }; 120 } 121 122 #endif 123