| /external/vogar/src/vogar/commands/ |
| Rm.java | 23 * A rm command.
25 public final class Rm {
28 public Rm(Log log) {
33 new Command(log, "rm", "-rf", file.getPath()).execute();
|
| /cts/libs/vogar-expect/src/vogar/commands/ |
| Rm.java | 22 * A rm command.
24 public final class Rm {
27 new Command("rm", "-f", file.getPath()).execute();
31 new Command("rm", "-rf", directory.getPath()).execute();
|
| /device/linaro/bootloader/edk2/ArmPkg/Library/ArmDisassemblerLib/ |
| ArmDisassembler.c | 169 UINT32 Rn, Rd, Rm;
184 Rm = (OpCode & 0xf);
199 // A4.1.103 STREX{<cond>} <Rd>, <Rm>, [<Rn>]
234 // A5.2.3 [<Rn>, +/-<Rm>]
235 // A5.2.6 [<Rn>, +/-<Rm>]!
238 // A5.2.4 [<Rn>, +/-<Rm>, LSL #<shift_imm>]
239 // A5.2.7 [<Rn>, +/-<Rm>, LSL #<shift_imm>]!
252 AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%a, %a, RRX]%a", gReg[Rn], SIGN (U), gReg[Rm], WRITE (W));
258 AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%a, %a, #%d]%a", gReg[Rn], SIGN (U), gReg[Rm], Type, shift_imm, WRITE (W));
265 // A5.2.9 [<Rn>], +/-<Rm>
[all...] |
| ThumbDisassembler.c | 114 { "ADC" , 0x4140, 0xffc0, DATA_FORMAT5 }, // ADC <Rndn>, <Rm>
150 { "LDR" , 0x5800, 0xfe00, LOAD_STORE_FORMAT2 }, // STR <Rt>, [<Rn>, <Rm>]
154 { "LDRB" , 0x5c00, 0xfe00, LOAD_STORE_FORMAT2 }, // STR <Rt>, [<Rn>, <Rm>]
157 { "LDRSB" , 0x5600, 0xfe00, LOAD_STORE_FORMAT2 }, // STR <Rt>, [<Rn>, <Rm>]
165 { "LSRS", 0x0800, 0xf800, DATA_FORMAT4 }, // LSRS <Rd>, <Rm>, #<imm5>
188 { "STR" , 0x5000, 0xfe00, LOAD_STORE_FORMAT2 }, // STR <Rt>, [<Rn>, <Rm>]
191 { "STRB" , 0x5400, 0xfe00, LOAD_STORE_FORMAT2 }, // STRB <Rt>, [<Rn>, <Rm>]
193 { "STRH" , 0x5200, 0xfe00, LOAD_STORE_FORMAT2 }, // STRH <Rt>, [<Rn>, <Rm>]
218 { "CMN", 0xeb100f00, 0xfff08f00, ADD_IMM5_2REG }, // CMN <Rn>, <Rm> {,<shift> #<const>}
221 { "TEQ", 0xea900f00, 0xfff08f00, ADD_IMM5_2REG }, // CMN <Rn>, <Rm> {,<shift> #<const>}
[all...] |
| /external/llvm/lib/Target/AArch64/Disassembler/ |
| AArch64Disassembler.cpp | [all...] |
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMMCCodeEmitter.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMMCCodeEmitter.cpp | [all...] |
| /external/capstone/arch/AArch64/ |
| AArch64Disassembler.c | 845 unsigned Rm = fieldFromInstruction(insn, 16, 5);
874 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
895 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/MCTargetDesc/ |
| ARMMCCodeEmitter.cpp | 687 // [Rn, Rm]
688 // {5-3} = Rm
693 unsigned Rm = getARMRegisterNumbering(MO2.getReg());
694 return (Rm << 3) | Rn;
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/Disassembler/ |
| AArch64Disassembler.cpp | [all...] |
| /external/v8/src/arm/ |
| disasm-arm.cc | 91 void FormatNeonMemory(int Rn, int align, int Rm);
196 int rm = instr->RmValue(); local
198 PrintRegister(rm);
201 // Special case for using rm only.
317 } else if (format[1] == 'm') { // 'rm: Rm register
417 void Decoder::FormatNeonMemory(int Rn, int align, int Rm) {
424 if (Rm == 15) {
426 } else if (Rm == 13) {
430 converter_.NameOfCPURegister(Rm));
[all...] |
| simulator-arm.cc | 1994 int rm = instr->RmValue(); local
2156 int rm = instr->RmValue(); local
2286 int rm = instr->RmValue(); local
2299 int rm = instr->RmValue(); local
2320 int rm = instr->RmValue(); local
2945 int rm = instr->RmValue(); local
2968 int rm = instr->RmValue(); local
[all...] |
| /external/capstone/arch/ARM/ |
| ARMDisassembler.c | [all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/Disassembler/ |
| ARMDisassembler.cpp | [all...] |
| /external/vixl/src/aarch64/ |
| assembler-aarch64.h | 712 void lslv(const Register& rd, const Register& rn, const Register& rm);
715 void lsrv(const Register& rd, const Register& rn, const Register& rm);
718 void asrv(const Register& rd, const Register& rn, const Register& rm);
721 void rorv(const Register& rd, const Register& rn, const Register& rm);
859 const Register& rm,
862 // Conditional select: rd = cond ? rn : rm.
865 const Register& rm,
868 // Conditional select increment: rd = cond ? rn : rm + 1.
871 const Register& rm,
874 // Conditional select inversion: rd = cond ? rn : ~rm
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMBaseInstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/ARM/Disassembler/ |
| ARMDisassembler.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| ARMBaseInstrInfo.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/Disassembler/ |
| ARMDisassembler.cpp | [all...] |
| /external/conscrypt/benchmark-android/ |
| vogar.jar | |
