1 //===-- ARM/ARMMCCodeEmitter.cpp - Convert ARM code to machine code -------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the ARMMCCodeEmitter class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "MCTargetDesc/ARMMCTargetDesc.h" 15 #include "MCTargetDesc/ARMAddressingModes.h" 16 #include "MCTargetDesc/ARMBaseInfo.h" 17 #include "MCTargetDesc/ARMFixupKinds.h" 18 #include "MCTargetDesc/ARMMCExpr.h" 19 #include "llvm/ADT/APFloat.h" 20 #include "llvm/ADT/Statistic.h" 21 #include "llvm/MC/MCCodeEmitter.h" 22 #include "llvm/MC/MCContext.h" 23 #include "llvm/MC/MCExpr.h" 24 #include "llvm/MC/MCInst.h" 25 #include "llvm/MC/MCInstrInfo.h" 26 #include "llvm/MC/MCRegisterInfo.h" 27 #include "llvm/MC/MCSubtargetInfo.h" 28 #include "llvm/Support/ErrorHandling.h" 29 #include "llvm/Support/raw_ostream.h" 30 31 using namespace llvm; 32 33 #define DEBUG_TYPE "mccodeemitter" 34 35 STATISTIC(MCNumEmitted, "Number of MC instructions emitted."); 36 STATISTIC(MCNumCPRelocations, "Number of constant pool relocations created."); 37 38 namespace { 39 class ARMMCCodeEmitter : public MCCodeEmitter { 40 ARMMCCodeEmitter(const ARMMCCodeEmitter &) = delete; 41 void operator=(const ARMMCCodeEmitter &) = delete; 42 const MCInstrInfo &MCII; 43 const MCContext &CTX; 44 bool IsLittleEndian; 45 46 public: 47 ARMMCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx, bool IsLittle) 48 : MCII(mcii), CTX(ctx), IsLittleEndian(IsLittle) { 49 } 50 51 ~ARMMCCodeEmitter() override {} 52 53 bool isThumb(const MCSubtargetInfo &STI) const { 54 return STI.getFeatureBits()[ARM::ModeThumb]; 55 } 56 bool isThumb2(const MCSubtargetInfo &STI) const { 57 return isThumb(STI) && STI.getFeatureBits()[ARM::FeatureThumb2]; 58 } 59 bool isTargetMachO(const MCSubtargetInfo &STI) const { 60 const Triple &TT = STI.getTargetTriple(); 61 return TT.isOSBinFormatMachO(); 62 } 63 64 unsigned getMachineSoImmOpValue(unsigned SoImm) const; 65 66 // getBinaryCodeForInstr - TableGen'erated function for getting the 67 // binary encoding for an instruction. 68 uint64_t getBinaryCodeForInstr(const MCInst &MI, 69 SmallVectorImpl<MCFixup> &Fixups, 70 const MCSubtargetInfo &STI) const; 71 72 /// getMachineOpValue - Return binary encoding of operand. If the machine 73 /// operand requires relocation, record the relocation and return zero. 74 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO, 75 SmallVectorImpl<MCFixup> &Fixups, 76 const MCSubtargetInfo &STI) const; 77 78 /// getHiLo16ImmOpValue - Return the encoding for the hi / low 16-bit of 79 /// the specified operand. This is used for operands with :lower16: and 80 /// :upper16: prefixes. 81 uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx, 82 SmallVectorImpl<MCFixup> &Fixups, 83 const MCSubtargetInfo &STI) const; 84 85 bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, 86 unsigned &Reg, unsigned &Imm, 87 SmallVectorImpl<MCFixup> &Fixups, 88 const MCSubtargetInfo &STI) const; 89 90 /// getThumbBLTargetOpValue - Return encoding info for Thumb immediate 91 /// BL branch target. 92 uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx, 93 SmallVectorImpl<MCFixup> &Fixups, 94 const MCSubtargetInfo &STI) const; 95 96 /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate 97 /// BLX branch target. 98 uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, 99 SmallVectorImpl<MCFixup> &Fixups, 100 const MCSubtargetInfo &STI) const; 101 102 /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target. 103 uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx, 104 SmallVectorImpl<MCFixup> &Fixups, 105 const MCSubtargetInfo &STI) const; 106 107 /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target. 108 uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx, 109 SmallVectorImpl<MCFixup> &Fixups, 110 const MCSubtargetInfo &STI) const; 111 112 /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target. 113 uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx, 114 SmallVectorImpl<MCFixup> &Fixups, 115 const MCSubtargetInfo &STI) const; 116 117 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate 118 /// branch target. 119 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 120 SmallVectorImpl<MCFixup> &Fixups, 121 const MCSubtargetInfo &STI) const; 122 123 /// getThumbBranchTargetOpValue - Return encoding info for 24-bit 124 /// immediate Thumb2 direct branch target. 125 uint32_t getThumbBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 126 SmallVectorImpl<MCFixup> &Fixups, 127 const MCSubtargetInfo &STI) const; 128 129 /// getARMBranchTargetOpValue - Return encoding info for 24-bit immediate 130 /// branch target. 131 uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 132 SmallVectorImpl<MCFixup> &Fixups, 133 const MCSubtargetInfo &STI) const; 134 uint32_t getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx, 135 SmallVectorImpl<MCFixup> &Fixups, 136 const MCSubtargetInfo &STI) const; 137 uint32_t getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, 138 SmallVectorImpl<MCFixup> &Fixups, 139 const MCSubtargetInfo &STI) const; 140 141 /// getAdrLabelOpValue - Return encoding info for 12-bit immediate 142 /// ADR label target. 143 uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, 144 SmallVectorImpl<MCFixup> &Fixups, 145 const MCSubtargetInfo &STI) const; 146 uint32_t getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, 147 SmallVectorImpl<MCFixup> &Fixups, 148 const MCSubtargetInfo &STI) const; 149 uint32_t getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx, 150 SmallVectorImpl<MCFixup> &Fixups, 151 const MCSubtargetInfo &STI) const; 152 153 154 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' 155 /// operand. 156 uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx, 157 SmallVectorImpl<MCFixup> &Fixups, 158 const MCSubtargetInfo &STI) const; 159 160 /// getThumbAddrModeRegRegOpValue - Return encoding for 'reg + reg' operand. 161 uint32_t getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx, 162 SmallVectorImpl<MCFixup> &Fixups, 163 const MCSubtargetInfo &STI) const; 164 165 /// getT2AddrModeImm8s4OpValue - Return encoding info for 'reg +/- imm8<<2' 166 /// operand. 167 uint32_t getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx, 168 SmallVectorImpl<MCFixup> &Fixups, 169 const MCSubtargetInfo &STI) const; 170 171 /// getT2AddrModeImm0_1020s4OpValue - Return encoding info for 'reg + imm8<<2' 172 /// operand. 173 uint32_t getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx, 174 SmallVectorImpl<MCFixup> &Fixups, 175 const MCSubtargetInfo &STI) const; 176 177 /// getT2Imm8s4OpValue - Return encoding info for '+/- imm8<<2' 178 /// operand. 179 uint32_t getT2Imm8s4OpValue(const MCInst &MI, unsigned OpIdx, 180 SmallVectorImpl<MCFixup> &Fixups, 181 const MCSubtargetInfo &STI) const; 182 183 184 /// getLdStSORegOpValue - Return encoding info for 'reg +/- reg shop imm' 185 /// operand as needed by load/store instructions. 186 uint32_t getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx, 187 SmallVectorImpl<MCFixup> &Fixups, 188 const MCSubtargetInfo &STI) const; 189 190 /// getLdStmModeOpValue - Return encoding for load/store multiple mode. 191 uint32_t getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx, 192 SmallVectorImpl<MCFixup> &Fixups, 193 const MCSubtargetInfo &STI) const { 194 ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm(); 195 switch (Mode) { 196 default: llvm_unreachable("Unknown addressing sub-mode!"); 197 case ARM_AM::da: return 0; 198 case ARM_AM::ia: return 1; 199 case ARM_AM::db: return 2; 200 case ARM_AM::ib: return 3; 201 } 202 } 203 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value. 204 /// 205 unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const { 206 switch (ShOpc) { 207 case ARM_AM::no_shift: 208 case ARM_AM::lsl: return 0; 209 case ARM_AM::lsr: return 1; 210 case ARM_AM::asr: return 2; 211 case ARM_AM::ror: 212 case ARM_AM::rrx: return 3; 213 } 214 llvm_unreachable("Invalid ShiftOpc!"); 215 } 216 217 /// getAddrMode2OffsetOpValue - Return encoding for am2offset operands. 218 uint32_t getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx, 219 SmallVectorImpl<MCFixup> &Fixups, 220 const MCSubtargetInfo &STI) const; 221 222 /// getPostIdxRegOpValue - Return encoding for postidx_reg operands. 223 uint32_t getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx, 224 SmallVectorImpl<MCFixup> &Fixups, 225 const MCSubtargetInfo &STI) const; 226 227 /// getAddrMode3OffsetOpValue - Return encoding for am3offset operands. 228 uint32_t getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx, 229 SmallVectorImpl<MCFixup> &Fixups, 230 const MCSubtargetInfo &STI) const; 231 232 /// getAddrMode3OpValue - Return encoding for addrmode3 operands. 233 uint32_t getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx, 234 SmallVectorImpl<MCFixup> &Fixups, 235 const MCSubtargetInfo &STI) const; 236 237 /// getAddrModeThumbSPOpValue - Return encoding info for 'reg +/- imm12' 238 /// operand. 239 uint32_t getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx, 240 SmallVectorImpl<MCFixup> &Fixups, 241 const MCSubtargetInfo &STI) const; 242 243 /// getAddrModeISOpValue - Encode the t_addrmode_is# operands. 244 uint32_t getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx, 245 SmallVectorImpl<MCFixup> &Fixups, 246 const MCSubtargetInfo &STI) const; 247 248 /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands. 249 uint32_t getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx, 250 SmallVectorImpl<MCFixup> &Fixups, 251 const MCSubtargetInfo &STI) const; 252 253 /// getAddrMode5OpValue - Return encoding info for 'reg +/- (imm8 << 2)' operand. 254 uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx, 255 SmallVectorImpl<MCFixup> &Fixups, 256 const MCSubtargetInfo &STI) const; 257 258 /// getAddrMode5FP16OpValue - Return encoding info for 'reg +/- (imm8 << 1)' operand. 259 uint32_t getAddrMode5FP16OpValue(const MCInst &MI, unsigned OpIdx, 260 SmallVectorImpl<MCFixup> &Fixups, 261 const MCSubtargetInfo &STI) const; 262 263 /// getCCOutOpValue - Return encoding of the 's' bit. 264 unsigned getCCOutOpValue(const MCInst &MI, unsigned Op, 265 SmallVectorImpl<MCFixup> &Fixups, 266 const MCSubtargetInfo &STI) const { 267 // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or 268 // '1' respectively. 269 return MI.getOperand(Op).getReg() == ARM::CPSR; 270 } 271 272 /// getSOImmOpValue - Return an encoded 12-bit shifted-immediate value. 273 unsigned getSOImmOpValue(const MCInst &MI, unsigned Op, 274 SmallVectorImpl<MCFixup> &Fixups, 275 const MCSubtargetInfo &STI) const { 276 277 const MCOperand &MO = MI.getOperand(Op); 278 279 // We expect MO to be an immediate or an expression, 280 // if it is an immediate - that's fine, just encode the value. 281 // Otherwise - create a Fixup. 282 if (MO.isExpr()) { 283 const MCExpr *Expr = MO.getExpr(); 284 // In instruction code this value always encoded as lowest 12 bits, 285 // so we don't have to perform any specific adjustments. 286 // Due to requirements of relocatable records we have to use FK_Data_4. 287 // See ARMELFObjectWriter::ExplicitRelSym and 288 // ARMELFObjectWriter::GetRelocTypeInner for more details. 289 MCFixupKind Kind = MCFixupKind(FK_Data_4); 290 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc())); 291 return 0; 292 } 293 294 unsigned SoImm = MO.getImm(); 295 int SoImmVal = ARM_AM::getSOImmVal(SoImm); 296 assert(SoImmVal != -1 && "Not a valid so_imm value!"); 297 298 // Encode rotate_imm. 299 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1) 300 << ARMII::SoRotImmShift; 301 302 // Encode immed_8. 303 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal); 304 return Binary; 305 } 306 307 unsigned getModImmOpValue(const MCInst &MI, unsigned Op, 308 SmallVectorImpl<MCFixup> &Fixups, 309 const MCSubtargetInfo &ST) const { 310 const MCOperand &MO = MI.getOperand(Op); 311 312 // Support for fixups (MCFixup) 313 if (MO.isExpr()) { 314 const MCExpr *Expr = MO.getExpr(); 315 // Fixups resolve to plain values that need to be encoded. 316 MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_mod_imm); 317 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc())); 318 return 0; 319 } 320 321 // Immediate is already in its encoded format 322 return MO.getImm(); 323 } 324 325 /// getT2SOImmOpValue - Return an encoded 12-bit shifted-immediate value. 326 unsigned getT2SOImmOpValue(const MCInst &MI, unsigned Op, 327 SmallVectorImpl<MCFixup> &Fixups, 328 const MCSubtargetInfo &STI) const { 329 unsigned SoImm = MI.getOperand(Op).getImm(); 330 unsigned Encoded = ARM_AM::getT2SOImmVal(SoImm); 331 assert(Encoded != ~0U && "Not a Thumb2 so_imm value?"); 332 return Encoded; 333 } 334 335 unsigned getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum, 336 SmallVectorImpl<MCFixup> &Fixups, 337 const MCSubtargetInfo &STI) const; 338 unsigned getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum, 339 SmallVectorImpl<MCFixup> &Fixups, 340 const MCSubtargetInfo &STI) const; 341 unsigned getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum, 342 SmallVectorImpl<MCFixup> &Fixups, 343 const MCSubtargetInfo &STI) const; 344 345 /// getSORegOpValue - Return an encoded so_reg shifted register value. 346 unsigned getSORegRegOpValue(const MCInst &MI, unsigned Op, 347 SmallVectorImpl<MCFixup> &Fixups, 348 const MCSubtargetInfo &STI) const; 349 unsigned getSORegImmOpValue(const MCInst &MI, unsigned Op, 350 SmallVectorImpl<MCFixup> &Fixups, 351 const MCSubtargetInfo &STI) const; 352 unsigned getT2SORegOpValue(const MCInst &MI, unsigned Op, 353 SmallVectorImpl<MCFixup> &Fixups, 354 const MCSubtargetInfo &STI) const; 355 356 unsigned getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op, 357 SmallVectorImpl<MCFixup> &Fixups, 358 const MCSubtargetInfo &STI) const { 359 return 64 - MI.getOperand(Op).getImm(); 360 } 361 362 unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op, 363 SmallVectorImpl<MCFixup> &Fixups, 364 const MCSubtargetInfo &STI) const; 365 366 unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op, 367 SmallVectorImpl<MCFixup> &Fixups, 368 const MCSubtargetInfo &STI) const; 369 unsigned getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op, 370 SmallVectorImpl<MCFixup> &Fixups, 371 const MCSubtargetInfo &STI) const; 372 unsigned getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op, 373 SmallVectorImpl<MCFixup> &Fixups, 374 const MCSubtargetInfo &STI) const; 375 unsigned getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op, 376 SmallVectorImpl<MCFixup> &Fixups, 377 const MCSubtargetInfo &STI) const; 378 unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op, 379 SmallVectorImpl<MCFixup> &Fixups, 380 const MCSubtargetInfo &STI) const; 381 382 unsigned getShiftRight8Imm(const MCInst &MI, unsigned Op, 383 SmallVectorImpl<MCFixup> &Fixups, 384 const MCSubtargetInfo &STI) const; 385 unsigned getShiftRight16Imm(const MCInst &MI, unsigned Op, 386 SmallVectorImpl<MCFixup> &Fixups, 387 const MCSubtargetInfo &STI) const; 388 unsigned getShiftRight32Imm(const MCInst &MI, unsigned Op, 389 SmallVectorImpl<MCFixup> &Fixups, 390 const MCSubtargetInfo &STI) const; 391 unsigned getShiftRight64Imm(const MCInst &MI, unsigned Op, 392 SmallVectorImpl<MCFixup> &Fixups, 393 const MCSubtargetInfo &STI) const; 394 395 unsigned getThumbSRImmOpValue(const MCInst &MI, unsigned Op, 396 SmallVectorImpl<MCFixup> &Fixups, 397 const MCSubtargetInfo &STI) const; 398 399 unsigned NEONThumb2DataIPostEncoder(const MCInst &MI, 400 unsigned EncodedValue, 401 const MCSubtargetInfo &STI) const; 402 unsigned NEONThumb2LoadStorePostEncoder(const MCInst &MI, 403 unsigned EncodedValue, 404 const MCSubtargetInfo &STI) const; 405 unsigned NEONThumb2DupPostEncoder(const MCInst &MI, 406 unsigned EncodedValue, 407 const MCSubtargetInfo &STI) const; 408 unsigned NEONThumb2V8PostEncoder(const MCInst &MI, 409 unsigned EncodedValue, 410 const MCSubtargetInfo &STI) const; 411 412 unsigned VFPThumb2PostEncoder(const MCInst &MI, 413 unsigned EncodedValue, 414 const MCSubtargetInfo &STI) const; 415 416 void EmitByte(unsigned char C, raw_ostream &OS) const { 417 OS << (char)C; 418 } 419 420 void EmitConstant(uint64_t Val, unsigned Size, raw_ostream &OS) const { 421 // Output the constant in little endian byte order. 422 for (unsigned i = 0; i != Size; ++i) { 423 unsigned Shift = IsLittleEndian ? i * 8 : (Size - 1 - i) * 8; 424 EmitByte((Val >> Shift) & 0xff, OS); 425 } 426 } 427 428 void encodeInstruction(const MCInst &MI, raw_ostream &OS, 429 SmallVectorImpl<MCFixup> &Fixups, 430 const MCSubtargetInfo &STI) const override; 431 }; 432 433 } // end anonymous namespace 434 435 MCCodeEmitter *llvm::createARMLEMCCodeEmitter(const MCInstrInfo &MCII, 436 const MCRegisterInfo &MRI, 437 MCContext &Ctx) { 438 return new ARMMCCodeEmitter(MCII, Ctx, true); 439 } 440 441 MCCodeEmitter *llvm::createARMBEMCCodeEmitter(const MCInstrInfo &MCII, 442 const MCRegisterInfo &MRI, 443 MCContext &Ctx) { 444 return new ARMMCCodeEmitter(MCII, Ctx, false); 445 } 446 447 /// NEONThumb2DataIPostEncoder - Post-process encoded NEON data-processing 448 /// instructions, and rewrite them to their Thumb2 form if we are currently in 449 /// Thumb2 mode. 450 unsigned ARMMCCodeEmitter::NEONThumb2DataIPostEncoder(const MCInst &MI, 451 unsigned EncodedValue, 452 const MCSubtargetInfo &STI) const { 453 if (isThumb2(STI)) { 454 // NEON Thumb2 data-processsing encodings are very simple: bit 24 is moved 455 // to bit 12 of the high half-word (i.e. bit 28), and bits 27-24 are 456 // set to 1111. 457 unsigned Bit24 = EncodedValue & 0x01000000; 458 unsigned Bit28 = Bit24 << 4; 459 EncodedValue &= 0xEFFFFFFF; 460 EncodedValue |= Bit28; 461 EncodedValue |= 0x0F000000; 462 } 463 464 return EncodedValue; 465 } 466 467 /// NEONThumb2LoadStorePostEncoder - Post-process encoded NEON load/store 468 /// instructions, and rewrite them to their Thumb2 form if we are currently in 469 /// Thumb2 mode. 470 unsigned ARMMCCodeEmitter::NEONThumb2LoadStorePostEncoder(const MCInst &MI, 471 unsigned EncodedValue, 472 const MCSubtargetInfo &STI) const { 473 if (isThumb2(STI)) { 474 EncodedValue &= 0xF0FFFFFF; 475 EncodedValue |= 0x09000000; 476 } 477 478 return EncodedValue; 479 } 480 481 /// NEONThumb2DupPostEncoder - Post-process encoded NEON vdup 482 /// instructions, and rewrite them to their Thumb2 form if we are currently in 483 /// Thumb2 mode. 484 unsigned ARMMCCodeEmitter::NEONThumb2DupPostEncoder(const MCInst &MI, 485 unsigned EncodedValue, 486 const MCSubtargetInfo &STI) const { 487 if (isThumb2(STI)) { 488 EncodedValue &= 0x00FFFFFF; 489 EncodedValue |= 0xEE000000; 490 } 491 492 return EncodedValue; 493 } 494 495 /// Post-process encoded NEON v8 instructions, and rewrite them to Thumb2 form 496 /// if we are in Thumb2. 497 unsigned ARMMCCodeEmitter::NEONThumb2V8PostEncoder(const MCInst &MI, 498 unsigned EncodedValue, 499 const MCSubtargetInfo &STI) const { 500 if (isThumb2(STI)) { 501 EncodedValue |= 0xC000000; // Set bits 27-26 502 } 503 504 return EncodedValue; 505 } 506 507 /// VFPThumb2PostEncoder - Post-process encoded VFP instructions and rewrite 508 /// them to their Thumb2 form if we are currently in Thumb2 mode. 509 unsigned ARMMCCodeEmitter:: 510 VFPThumb2PostEncoder(const MCInst &MI, unsigned EncodedValue, 511 const MCSubtargetInfo &STI) const { 512 if (isThumb2(STI)) { 513 EncodedValue &= 0x0FFFFFFF; 514 EncodedValue |= 0xE0000000; 515 } 516 return EncodedValue; 517 } 518 519 /// getMachineOpValue - Return binary encoding of operand. If the machine 520 /// operand requires relocation, record the relocation and return zero. 521 unsigned ARMMCCodeEmitter:: 522 getMachineOpValue(const MCInst &MI, const MCOperand &MO, 523 SmallVectorImpl<MCFixup> &Fixups, 524 const MCSubtargetInfo &STI) const { 525 if (MO.isReg()) { 526 unsigned Reg = MO.getReg(); 527 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg); 528 529 // Q registers are encoded as 2x their register number. 530 switch (Reg) { 531 default: 532 return RegNo; 533 case ARM::Q0: case ARM::Q1: case ARM::Q2: case ARM::Q3: 534 case ARM::Q4: case ARM::Q5: case ARM::Q6: case ARM::Q7: 535 case ARM::Q8: case ARM::Q9: case ARM::Q10: case ARM::Q11: 536 case ARM::Q12: case ARM::Q13: case ARM::Q14: case ARM::Q15: 537 return 2 * RegNo; 538 } 539 } else if (MO.isImm()) { 540 return static_cast<unsigned>(MO.getImm()); 541 } else if (MO.isFPImm()) { 542 return static_cast<unsigned>(APFloat(MO.getFPImm()) 543 .bitcastToAPInt().getHiBits(32).getLimitedValue()); 544 } 545 546 llvm_unreachable("Unable to encode MCOperand!"); 547 } 548 549 /// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand. 550 bool ARMMCCodeEmitter:: 551 EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg, 552 unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups, 553 const MCSubtargetInfo &STI) const { 554 const MCOperand &MO = MI.getOperand(OpIdx); 555 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); 556 557 Reg = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); 558 559 int32_t SImm = MO1.getImm(); 560 bool isAdd = true; 561 562 // Special value for #-0 563 if (SImm == INT32_MIN) { 564 SImm = 0; 565 isAdd = false; 566 } 567 568 // Immediate is always encoded as positive. The 'U' bit controls add vs sub. 569 if (SImm < 0) { 570 SImm = -SImm; 571 isAdd = false; 572 } 573 574 Imm = SImm; 575 return isAdd; 576 } 577 578 /// getBranchTargetOpValue - Helper function to get the branch target operand, 579 /// which is either an immediate or requires a fixup. 580 static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 581 unsigned FixupKind, 582 SmallVectorImpl<MCFixup> &Fixups, 583 const MCSubtargetInfo &STI) { 584 const MCOperand &MO = MI.getOperand(OpIdx); 585 586 // If the destination is an immediate, we have nothing to do. 587 if (MO.isImm()) return MO.getImm(); 588 assert(MO.isExpr() && "Unexpected branch target type!"); 589 const MCExpr *Expr = MO.getExpr(); 590 MCFixupKind Kind = MCFixupKind(FixupKind); 591 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc())); 592 593 // All of the information is in the fixup. 594 return 0; 595 } 596 597 // Thumb BL and BLX use a strange offset encoding where bits 22 and 21 are 598 // determined by negating them and XOR'ing them with bit 23. 599 static int32_t encodeThumbBLOffset(int32_t offset) { 600 offset >>= 1; 601 uint32_t S = (offset & 0x800000) >> 23; 602 uint32_t J1 = (offset & 0x400000) >> 22; 603 uint32_t J2 = (offset & 0x200000) >> 21; 604 J1 = (~J1 & 0x1); 605 J2 = (~J2 & 0x1); 606 J1 ^= S; 607 J2 ^= S; 608 609 offset &= ~0x600000; 610 offset |= J1 << 22; 611 offset |= J2 << 21; 612 613 return offset; 614 } 615 616 /// getThumbBLTargetOpValue - Return encoding info for immediate branch target. 617 uint32_t ARMMCCodeEmitter:: 618 getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx, 619 SmallVectorImpl<MCFixup> &Fixups, 620 const MCSubtargetInfo &STI) const { 621 const MCOperand MO = MI.getOperand(OpIdx); 622 if (MO.isExpr()) 623 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bl, 624 Fixups, STI); 625 return encodeThumbBLOffset(MO.getImm()); 626 } 627 628 /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate 629 /// BLX branch target. 630 uint32_t ARMMCCodeEmitter:: 631 getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, 632 SmallVectorImpl<MCFixup> &Fixups, 633 const MCSubtargetInfo &STI) const { 634 const MCOperand MO = MI.getOperand(OpIdx); 635 if (MO.isExpr()) 636 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_blx, 637 Fixups, STI); 638 return encodeThumbBLOffset(MO.getImm()); 639 } 640 641 /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target. 642 uint32_t ARMMCCodeEmitter:: 643 getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx, 644 SmallVectorImpl<MCFixup> &Fixups, 645 const MCSubtargetInfo &STI) const { 646 const MCOperand MO = MI.getOperand(OpIdx); 647 if (MO.isExpr()) 648 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_br, 649 Fixups, STI); 650 return (MO.getImm() >> 1); 651 } 652 653 /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target. 654 uint32_t ARMMCCodeEmitter:: 655 getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx, 656 SmallVectorImpl<MCFixup> &Fixups, 657 const MCSubtargetInfo &STI) const { 658 const MCOperand MO = MI.getOperand(OpIdx); 659 if (MO.isExpr()) 660 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bcc, 661 Fixups, STI); 662 return (MO.getImm() >> 1); 663 } 664 665 /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target. 666 uint32_t ARMMCCodeEmitter:: 667 getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx, 668 SmallVectorImpl<MCFixup> &Fixups, 669 const MCSubtargetInfo &STI) const { 670 const MCOperand MO = MI.getOperand(OpIdx); 671 if (MO.isExpr()) 672 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cb, Fixups, STI); 673 return (MO.getImm() >> 1); 674 } 675 676 /// Return true if this branch has a non-always predication 677 static bool HasConditionalBranch(const MCInst &MI) { 678 int NumOp = MI.getNumOperands(); 679 if (NumOp >= 2) { 680 for (int i = 0; i < NumOp-1; ++i) { 681 const MCOperand &MCOp1 = MI.getOperand(i); 682 const MCOperand &MCOp2 = MI.getOperand(i + 1); 683 if (MCOp1.isImm() && MCOp2.isReg() && 684 (MCOp2.getReg() == 0 || MCOp2.getReg() == ARM::CPSR)) { 685 if (ARMCC::CondCodes(MCOp1.getImm()) != ARMCC::AL) 686 return true; 687 } 688 } 689 } 690 return false; 691 } 692 693 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch 694 /// target. 695 uint32_t ARMMCCodeEmitter:: 696 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 697 SmallVectorImpl<MCFixup> &Fixups, 698 const MCSubtargetInfo &STI) const { 699 // FIXME: This really, really shouldn't use TargetMachine. We don't want 700 // coupling between MC and TM anywhere we can help it. 701 if (isThumb2(STI)) 702 return 703 ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_condbranch, Fixups, STI); 704 return getARMBranchTargetOpValue(MI, OpIdx, Fixups, STI); 705 } 706 707 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch 708 /// target. 709 uint32_t ARMMCCodeEmitter:: 710 getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 711 SmallVectorImpl<MCFixup> &Fixups, 712 const MCSubtargetInfo &STI) const { 713 const MCOperand MO = MI.getOperand(OpIdx); 714 if (MO.isExpr()) { 715 if (HasConditionalBranch(MI)) 716 return ::getBranchTargetOpValue(MI, OpIdx, 717 ARM::fixup_arm_condbranch, Fixups, STI); 718 return ::getBranchTargetOpValue(MI, OpIdx, 719 ARM::fixup_arm_uncondbranch, Fixups, STI); 720 } 721 722 return MO.getImm() >> 2; 723 } 724 725 uint32_t ARMMCCodeEmitter:: 726 getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx, 727 SmallVectorImpl<MCFixup> &Fixups, 728 const MCSubtargetInfo &STI) const { 729 const MCOperand MO = MI.getOperand(OpIdx); 730 if (MO.isExpr()) { 731 if (HasConditionalBranch(MI)) 732 return ::getBranchTargetOpValue(MI, OpIdx, 733 ARM::fixup_arm_condbl, Fixups, STI); 734 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_uncondbl, Fixups, STI); 735 } 736 737 return MO.getImm() >> 2; 738 } 739 740 uint32_t ARMMCCodeEmitter:: 741 getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, 742 SmallVectorImpl<MCFixup> &Fixups, 743 const MCSubtargetInfo &STI) const { 744 const MCOperand MO = MI.getOperand(OpIdx); 745 if (MO.isExpr()) 746 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_blx, Fixups, STI); 747 748 return MO.getImm() >> 1; 749 } 750 751 /// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit 752 /// immediate branch target. 753 uint32_t ARMMCCodeEmitter::getThumbBranchTargetOpValue( 754 const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, 755 const MCSubtargetInfo &STI) const { 756 unsigned Val = 0; 757 const MCOperand MO = MI.getOperand(OpIdx); 758 759 if(MO.isExpr()) 760 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_uncondbranch, Fixups, STI); 761 else 762 Val = MO.getImm() >> 1; 763 764 bool I = (Val & 0x800000); 765 bool J1 = (Val & 0x400000); 766 bool J2 = (Val & 0x200000); 767 if (I ^ J1) 768 Val &= ~0x400000; 769 else 770 Val |= 0x400000; 771 772 if (I ^ J2) 773 Val &= ~0x200000; 774 else 775 Val |= 0x200000; 776 777 return Val; 778 } 779 780 /// getAdrLabelOpValue - Return encoding info for 12-bit shifted-immediate 781 /// ADR label target. 782 uint32_t ARMMCCodeEmitter:: 783 getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, 784 SmallVectorImpl<MCFixup> &Fixups, 785 const MCSubtargetInfo &STI) const { 786 const MCOperand MO = MI.getOperand(OpIdx); 787 if (MO.isExpr()) 788 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_adr_pcrel_12, 789 Fixups, STI); 790 int64_t offset = MO.getImm(); 791 uint32_t Val = 0x2000; 792 793 int SoImmVal; 794 if (offset == INT32_MIN) { 795 Val = 0x1000; 796 SoImmVal = 0; 797 } else if (offset < 0) { 798 Val = 0x1000; 799 offset *= -1; 800 SoImmVal = ARM_AM::getSOImmVal(offset); 801 if(SoImmVal == -1) { 802 Val = 0x2000; 803 offset *= -1; 804 SoImmVal = ARM_AM::getSOImmVal(offset); 805 } 806 } else { 807 SoImmVal = ARM_AM::getSOImmVal(offset); 808 if(SoImmVal == -1) { 809 Val = 0x1000; 810 offset *= -1; 811 SoImmVal = ARM_AM::getSOImmVal(offset); 812 } 813 } 814 815 assert(SoImmVal != -1 && "Not a valid so_imm value!"); 816 817 Val |= SoImmVal; 818 return Val; 819 } 820 821 /// getT2AdrLabelOpValue - Return encoding info for 12-bit immediate ADR label 822 /// target. 823 uint32_t ARMMCCodeEmitter:: 824 getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx, 825 SmallVectorImpl<MCFixup> &Fixups, 826 const MCSubtargetInfo &STI) const { 827 const MCOperand MO = MI.getOperand(OpIdx); 828 if (MO.isExpr()) 829 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_adr_pcrel_12, 830 Fixups, STI); 831 int32_t Val = MO.getImm(); 832 if (Val == INT32_MIN) 833 Val = 0x1000; 834 else if (Val < 0) { 835 Val *= -1; 836 Val |= 0x1000; 837 } 838 return Val; 839 } 840 841 /// getThumbAdrLabelOpValue - Return encoding info for 8-bit immediate ADR label 842 /// target. 843 uint32_t ARMMCCodeEmitter:: 844 getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, 845 SmallVectorImpl<MCFixup> &Fixups, 846 const MCSubtargetInfo &STI) const { 847 const MCOperand MO = MI.getOperand(OpIdx); 848 if (MO.isExpr()) 849 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_thumb_adr_pcrel_10, 850 Fixups, STI); 851 return MO.getImm(); 852 } 853 854 /// getThumbAddrModeRegRegOpValue - Return encoding info for 'reg + reg' 855 /// operand. 856 uint32_t ARMMCCodeEmitter:: 857 getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx, 858 SmallVectorImpl<MCFixup> &, 859 const MCSubtargetInfo &STI) const { 860 // [Rn, Rm] 861 // {5-3} = Rm 862 // {2-0} = Rn 863 const MCOperand &MO1 = MI.getOperand(OpIdx); 864 const MCOperand &MO2 = MI.getOperand(OpIdx + 1); 865 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg()); 866 unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO2.getReg()); 867 return (Rm << 3) | Rn; 868 } 869 870 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' operand. 871 uint32_t ARMMCCodeEmitter:: 872 getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx, 873 SmallVectorImpl<MCFixup> &Fixups, 874 const MCSubtargetInfo &STI) const { 875 // {17-13} = reg 876 // {12} = (U)nsigned (add == '1', sub == '0') 877 // {11-0} = imm12 878 unsigned Reg, Imm12; 879 bool isAdd = true; 880 // If The first operand isn't a register, we have a label reference. 881 const MCOperand &MO = MI.getOperand(OpIdx); 882 if (!MO.isReg()) { 883 Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC. 884 Imm12 = 0; 885 886 if (MO.isExpr()) { 887 const MCExpr *Expr = MO.getExpr(); 888 isAdd = false ; // 'U' bit is set as part of the fixup. 889 890 MCFixupKind Kind; 891 if (isThumb2(STI)) 892 Kind = MCFixupKind(ARM::fixup_t2_ldst_pcrel_12); 893 else 894 Kind = MCFixupKind(ARM::fixup_arm_ldst_pcrel_12); 895 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc())); 896 897 ++MCNumCPRelocations; 898 } else { 899 Reg = ARM::PC; 900 int32_t Offset = MO.getImm(); 901 if (Offset == INT32_MIN) { 902 Offset = 0; 903 isAdd = false; 904 } else if (Offset < 0) { 905 Offset *= -1; 906 isAdd = false; 907 } 908 Imm12 = Offset; 909 } 910 } else 911 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups, STI); 912 913 uint32_t Binary = Imm12 & 0xfff; 914 // Immediate is always encoded as positive. The 'U' bit controls add vs sub. 915 if (isAdd) 916 Binary |= (1 << 12); 917 Binary |= (Reg << 13); 918 return Binary; 919 } 920 921 /// getT2Imm8s4OpValue - Return encoding info for 922 /// '+/- imm8<<2' operand. 923 uint32_t ARMMCCodeEmitter:: 924 getT2Imm8s4OpValue(const MCInst &MI, unsigned OpIdx, 925 SmallVectorImpl<MCFixup> &Fixups, 926 const MCSubtargetInfo &STI) const { 927 // FIXME: The immediate operand should have already been encoded like this 928 // before ever getting here. The encoder method should just need to combine 929 // the MI operands for the register and the offset into a single 930 // representation for the complex operand in the .td file. This isn't just 931 // style, unfortunately. As-is, we can't represent the distinct encoding 932 // for #-0. 933 934 // {8} = (U)nsigned (add == '1', sub == '0') 935 // {7-0} = imm8 936 int32_t Imm8 = MI.getOperand(OpIdx).getImm(); 937 bool isAdd = Imm8 >= 0; 938 939 // Immediate is always encoded as positive. The 'U' bit controls add vs sub. 940 if (Imm8 < 0) 941 Imm8 = -(uint32_t)Imm8; 942 943 // Scaled by 4. 944 Imm8 /= 4; 945 946 uint32_t Binary = Imm8 & 0xff; 947 // Immediate is always encoded as positive. The 'U' bit controls add vs sub. 948 if (isAdd) 949 Binary |= (1 << 8); 950 return Binary; 951 } 952 953 /// getT2AddrModeImm8s4OpValue - Return encoding info for 954 /// 'reg +/- imm8<<2' operand. 955 uint32_t ARMMCCodeEmitter:: 956 getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx, 957 SmallVectorImpl<MCFixup> &Fixups, 958 const MCSubtargetInfo &STI) const { 959 // {12-9} = reg 960 // {8} = (U)nsigned (add == '1', sub == '0') 961 // {7-0} = imm8 962 unsigned Reg, Imm8; 963 bool isAdd = true; 964 // If The first operand isn't a register, we have a label reference. 965 const MCOperand &MO = MI.getOperand(OpIdx); 966 if (!MO.isReg()) { 967 Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC. 968 Imm8 = 0; 969 isAdd = false ; // 'U' bit is set as part of the fixup. 970 971 assert(MO.isExpr() && "Unexpected machine operand type!"); 972 const MCExpr *Expr = MO.getExpr(); 973 MCFixupKind Kind = MCFixupKind(ARM::fixup_t2_pcrel_10); 974 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc())); 975 976 ++MCNumCPRelocations; 977 } else 978 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI); 979 980 // FIXME: The immediate operand should have already been encoded like this 981 // before ever getting here. The encoder method should just need to combine 982 // the MI operands for the register and the offset into a single 983 // representation for the complex operand in the .td file. This isn't just 984 // style, unfortunately. As-is, we can't represent the distinct encoding 985 // for #-0. 986 uint32_t Binary = (Imm8 >> 2) & 0xff; 987 // Immediate is always encoded as positive. The 'U' bit controls add vs sub. 988 if (isAdd) 989 Binary |= (1 << 8); 990 Binary |= (Reg << 9); 991 return Binary; 992 } 993 994 /// getT2AddrModeImm0_1020s4OpValue - Return encoding info for 995 /// 'reg + imm8<<2' operand. 996 uint32_t ARMMCCodeEmitter:: 997 getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx, 998 SmallVectorImpl<MCFixup> &Fixups, 999 const MCSubtargetInfo &STI) const { 1000 // {11-8} = reg 1001 // {7-0} = imm8 1002 const MCOperand &MO = MI.getOperand(OpIdx); 1003 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); 1004 unsigned Reg = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); 1005 unsigned Imm8 = MO1.getImm(); 1006 return (Reg << 8) | Imm8; 1007 } 1008 1009 uint32_t 1010 ARMMCCodeEmitter::getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx, 1011 SmallVectorImpl<MCFixup> &Fixups, 1012 const MCSubtargetInfo &STI) const { 1013 // {20-16} = imm{15-12} 1014 // {11-0} = imm{11-0} 1015 const MCOperand &MO = MI.getOperand(OpIdx); 1016 if (MO.isImm()) 1017 // Hi / lo 16 bits already extracted during earlier passes. 1018 return static_cast<unsigned>(MO.getImm()); 1019 1020 // Handle :upper16: and :lower16: assembly prefixes. 1021 const MCExpr *E = MO.getExpr(); 1022 MCFixupKind Kind; 1023 if (E->getKind() == MCExpr::Target) { 1024 const ARMMCExpr *ARM16Expr = cast<ARMMCExpr>(E); 1025 E = ARM16Expr->getSubExpr(); 1026 1027 if (const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(E)) { 1028 const int64_t Value = MCE->getValue(); 1029 if (Value > UINT32_MAX) 1030 report_fatal_error("constant value truncated (limited to 32-bit)"); 1031 1032 switch (ARM16Expr->getKind()) { 1033 case ARMMCExpr::VK_ARM_HI16: 1034 return (int32_t(Value) & 0xffff0000) >> 16; 1035 case ARMMCExpr::VK_ARM_LO16: 1036 return (int32_t(Value) & 0x0000ffff); 1037 default: llvm_unreachable("Unsupported ARMFixup"); 1038 } 1039 } 1040 1041 switch (ARM16Expr->getKind()) { 1042 default: llvm_unreachable("Unsupported ARMFixup"); 1043 case ARMMCExpr::VK_ARM_HI16: 1044 Kind = MCFixupKind(isThumb(STI) ? ARM::fixup_t2_movt_hi16 1045 : ARM::fixup_arm_movt_hi16); 1046 break; 1047 case ARMMCExpr::VK_ARM_LO16: 1048 Kind = MCFixupKind(isThumb(STI) ? ARM::fixup_t2_movw_lo16 1049 : ARM::fixup_arm_movw_lo16); 1050 break; 1051 } 1052 1053 Fixups.push_back(MCFixup::create(0, E, Kind, MI.getLoc())); 1054 return 0; 1055 } 1056 // If the expression doesn't have :upper16: or :lower16: on it, 1057 // it's just a plain immediate expression, previously those evaluated to 1058 // the lower 16 bits of the expression regardless of whether 1059 // we have a movt or a movw, but that led to misleadingly results. 1060 // This is disallowed in the AsmParser in validateInstruction() 1061 // so this should never happen. 1062 llvm_unreachable("expression without :upper16: or :lower16:"); 1063 } 1064 1065 uint32_t ARMMCCodeEmitter:: 1066 getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx, 1067 SmallVectorImpl<MCFixup> &Fixups, 1068 const MCSubtargetInfo &STI) const { 1069 const MCOperand &MO = MI.getOperand(OpIdx); 1070 const MCOperand &MO1 = MI.getOperand(OpIdx+1); 1071 const MCOperand &MO2 = MI.getOperand(OpIdx+2); 1072 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); 1073 unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg()); 1074 unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()); 1075 bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add; 1076 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm()); 1077 unsigned SBits = getShiftOp(ShOp); 1078 1079 // While "lsr #32" and "asr #32" exist, they are encoded with a 0 in the shift 1080 // amount. However, it would be an easy mistake to make so check here. 1081 assert((ShImm & ~0x1f) == 0 && "Out of range shift amount"); 1082 1083 // {16-13} = Rn 1084 // {12} = isAdd 1085 // {11-0} = shifter 1086 // {3-0} = Rm 1087 // {4} = 0 1088 // {6-5} = type 1089 // {11-7} = imm 1090 uint32_t Binary = Rm; 1091 Binary |= Rn << 13; 1092 Binary |= SBits << 5; 1093 Binary |= ShImm << 7; 1094 if (isAdd) 1095 Binary |= 1 << 12; 1096 return Binary; 1097 } 1098 1099 uint32_t ARMMCCodeEmitter:: 1100 getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx, 1101 SmallVectorImpl<MCFixup> &Fixups, 1102 const MCSubtargetInfo &STI) const { 1103 // {13} 1 == imm12, 0 == Rm 1104 // {12} isAdd 1105 // {11-0} imm12/Rm 1106 const MCOperand &MO = MI.getOperand(OpIdx); 1107 const MCOperand &MO1 = MI.getOperand(OpIdx+1); 1108 unsigned Imm = MO1.getImm(); 1109 bool isAdd = ARM_AM::getAM2Op(Imm) == ARM_AM::add; 1110 bool isReg = MO.getReg() != 0; 1111 uint32_t Binary = ARM_AM::getAM2Offset(Imm); 1112 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm12 1113 if (isReg) { 1114 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm); 1115 Binary <<= 7; // Shift amount is bits [11:7] 1116 Binary |= getShiftOp(ShOp) << 5; // Shift type is bits [6:5] 1117 Binary |= CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); // Rm is bits [3:0] 1118 } 1119 return Binary | (isAdd << 12) | (isReg << 13); 1120 } 1121 1122 uint32_t ARMMCCodeEmitter:: 1123 getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx, 1124 SmallVectorImpl<MCFixup> &Fixups, 1125 const MCSubtargetInfo &STI) const { 1126 // {4} isAdd 1127 // {3-0} Rm 1128 const MCOperand &MO = MI.getOperand(OpIdx); 1129 const MCOperand &MO1 = MI.getOperand(OpIdx+1); 1130 bool isAdd = MO1.getImm() != 0; 1131 return CTX.getRegisterInfo()->getEncodingValue(MO.getReg()) | (isAdd << 4); 1132 } 1133 1134 uint32_t ARMMCCodeEmitter:: 1135 getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx, 1136 SmallVectorImpl<MCFixup> &Fixups, 1137 const MCSubtargetInfo &STI) const { 1138 // {9} 1 == imm8, 0 == Rm 1139 // {8} isAdd 1140 // {7-4} imm7_4/zero 1141 // {3-0} imm3_0/Rm 1142 const MCOperand &MO = MI.getOperand(OpIdx); 1143 const MCOperand &MO1 = MI.getOperand(OpIdx+1); 1144 unsigned Imm = MO1.getImm(); 1145 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add; 1146 bool isImm = MO.getReg() == 0; 1147 uint32_t Imm8 = ARM_AM::getAM3Offset(Imm); 1148 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8 1149 if (!isImm) 1150 Imm8 = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); 1151 return Imm8 | (isAdd << 8) | (isImm << 9); 1152 } 1153 1154 uint32_t ARMMCCodeEmitter:: 1155 getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx, 1156 SmallVectorImpl<MCFixup> &Fixups, 1157 const MCSubtargetInfo &STI) const { 1158 // {13} 1 == imm8, 0 == Rm 1159 // {12-9} Rn 1160 // {8} isAdd 1161 // {7-4} imm7_4/zero 1162 // {3-0} imm3_0/Rm 1163 const MCOperand &MO = MI.getOperand(OpIdx); 1164 const MCOperand &MO1 = MI.getOperand(OpIdx+1); 1165 const MCOperand &MO2 = MI.getOperand(OpIdx+2); 1166 1167 // If The first operand isn't a register, we have a label reference. 1168 if (!MO.isReg()) { 1169 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC. 1170 1171 assert(MO.isExpr() && "Unexpected machine operand type!"); 1172 const MCExpr *Expr = MO.getExpr(); 1173 MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_pcrel_10_unscaled); 1174 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc())); 1175 1176 ++MCNumCPRelocations; 1177 return (Rn << 9) | (1 << 13); 1178 } 1179 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); 1180 unsigned Imm = MO2.getImm(); 1181 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add; 1182 bool isImm = MO1.getReg() == 0; 1183 uint32_t Imm8 = ARM_AM::getAM3Offset(Imm); 1184 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8 1185 if (!isImm) 1186 Imm8 = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg()); 1187 return (Rn << 9) | Imm8 | (isAdd << 8) | (isImm << 13); 1188 } 1189 1190 /// getAddrModeThumbSPOpValue - Encode the t_addrmode_sp operands. 1191 uint32_t ARMMCCodeEmitter:: 1192 getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx, 1193 SmallVectorImpl<MCFixup> &Fixups, 1194 const MCSubtargetInfo &STI) const { 1195 // [SP, #imm] 1196 // {7-0} = imm8 1197 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); 1198 assert(MI.getOperand(OpIdx).getReg() == ARM::SP && 1199 "Unexpected base register!"); 1200 1201 // The immediate is already shifted for the implicit zeroes, so no change 1202 // here. 1203 return MO1.getImm() & 0xff; 1204 } 1205 1206 /// getAddrModeISOpValue - Encode the t_addrmode_is# operands. 1207 uint32_t ARMMCCodeEmitter:: 1208 getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx, 1209 SmallVectorImpl<MCFixup> &Fixups, 1210 const MCSubtargetInfo &STI) const { 1211 // [Rn, #imm] 1212 // {7-3} = imm5 1213 // {2-0} = Rn 1214 const MCOperand &MO = MI.getOperand(OpIdx); 1215 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); 1216 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); 1217 unsigned Imm5 = MO1.getImm(); 1218 return ((Imm5 & 0x1f) << 3) | Rn; 1219 } 1220 1221 /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands. 1222 uint32_t ARMMCCodeEmitter:: 1223 getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx, 1224 SmallVectorImpl<MCFixup> &Fixups, 1225 const MCSubtargetInfo &STI) const { 1226 const MCOperand MO = MI.getOperand(OpIdx); 1227 if (MO.isExpr()) 1228 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cp, Fixups, STI); 1229 return (MO.getImm() >> 2); 1230 } 1231 1232 /// getAddrMode5OpValue - Return encoding info for 'reg +/- (imm8 << 2)' operand. 1233 uint32_t ARMMCCodeEmitter:: 1234 getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx, 1235 SmallVectorImpl<MCFixup> &Fixups, 1236 const MCSubtargetInfo &STI) const { 1237 // {12-9} = reg 1238 // {8} = (U)nsigned (add == '1', sub == '0') 1239 // {7-0} = imm8 1240 unsigned Reg, Imm8; 1241 bool isAdd; 1242 // If The first operand isn't a register, we have a label reference. 1243 const MCOperand &MO = MI.getOperand(OpIdx); 1244 if (!MO.isReg()) { 1245 Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC. 1246 Imm8 = 0; 1247 isAdd = false; // 'U' bit is handled as part of the fixup. 1248 1249 assert(MO.isExpr() && "Unexpected machine operand type!"); 1250 const MCExpr *Expr = MO.getExpr(); 1251 MCFixupKind Kind; 1252 if (isThumb2(STI)) 1253 Kind = MCFixupKind(ARM::fixup_t2_pcrel_10); 1254 else 1255 Kind = MCFixupKind(ARM::fixup_arm_pcrel_10); 1256 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc())); 1257 1258 ++MCNumCPRelocations; 1259 } else { 1260 EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI); 1261 isAdd = ARM_AM::getAM5Op(Imm8) == ARM_AM::add; 1262 } 1263 1264 uint32_t Binary = ARM_AM::getAM5Offset(Imm8); 1265 // Immediate is always encoded as positive. The 'U' bit controls add vs sub. 1266 if (isAdd) 1267 Binary |= (1 << 8); 1268 Binary |= (Reg << 9); 1269 return Binary; 1270 } 1271 1272 /// getAddrMode5FP16OpValue - Return encoding info for 'reg +/- (imm8 << 1)' operand. 1273 uint32_t ARMMCCodeEmitter:: 1274 getAddrMode5FP16OpValue(const MCInst &MI, unsigned OpIdx, 1275 SmallVectorImpl<MCFixup> &Fixups, 1276 const MCSubtargetInfo &STI) const { 1277 // {12-9} = reg 1278 // {8} = (U)nsigned (add == '1', sub == '0') 1279 // {7-0} = imm8 1280 unsigned Reg, Imm8; 1281 bool isAdd; 1282 // If The first operand isn't a register, we have a label reference. 1283 const MCOperand &MO = MI.getOperand(OpIdx); 1284 if (!MO.isReg()) { 1285 Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC. 1286 Imm8 = 0; 1287 isAdd = false; // 'U' bit is handled as part of the fixup. 1288 1289 assert(MO.isExpr() && "Unexpected machine operand type!"); 1290 const MCExpr *Expr = MO.getExpr(); 1291 MCFixupKind Kind; 1292 if (isThumb2(STI)) 1293 Kind = MCFixupKind(ARM::fixup_t2_pcrel_9); 1294 else 1295 Kind = MCFixupKind(ARM::fixup_arm_pcrel_9); 1296 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc())); 1297 1298 ++MCNumCPRelocations; 1299 } else { 1300 EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI); 1301 isAdd = ARM_AM::getAM5Op(Imm8) == ARM_AM::add; 1302 } 1303 1304 uint32_t Binary = ARM_AM::getAM5Offset(Imm8); 1305 // Immediate is always encoded as positive. The 'U' bit controls add vs sub. 1306 if (isAdd) 1307 Binary |= (1 << 8); 1308 Binary |= (Reg << 9); 1309 return Binary; 1310 } 1311 1312 unsigned ARMMCCodeEmitter:: 1313 getSORegRegOpValue(const MCInst &MI, unsigned OpIdx, 1314 SmallVectorImpl<MCFixup> &Fixups, 1315 const MCSubtargetInfo &STI) const { 1316 // Sub-operands are [reg, reg, imm]. The first register is Rm, the reg to be 1317 // shifted. The second is Rs, the amount to shift by, and the third specifies 1318 // the type of the shift. 1319 // 1320 // {3-0} = Rm. 1321 // {4} = 1 1322 // {6-5} = type 1323 // {11-8} = Rs 1324 // {7} = 0 1325 1326 const MCOperand &MO = MI.getOperand(OpIdx); 1327 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); 1328 const MCOperand &MO2 = MI.getOperand(OpIdx + 2); 1329 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm()); 1330 1331 // Encode Rm. 1332 unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); 1333 1334 // Encode the shift opcode. 1335 unsigned SBits = 0; 1336 unsigned Rs = MO1.getReg(); 1337 if (Rs) { 1338 // Set shift operand (bit[7:4]). 1339 // LSL - 0001 1340 // LSR - 0011 1341 // ASR - 0101 1342 // ROR - 0111 1343 switch (SOpc) { 1344 default: llvm_unreachable("Unknown shift opc!"); 1345 case ARM_AM::lsl: SBits = 0x1; break; 1346 case ARM_AM::lsr: SBits = 0x3; break; 1347 case ARM_AM::asr: SBits = 0x5; break; 1348 case ARM_AM::ror: SBits = 0x7; break; 1349 } 1350 } 1351 1352 Binary |= SBits << 4; 1353 1354 // Encode the shift operation Rs. 1355 // Encode Rs bit[11:8]. 1356 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0); 1357 return Binary | (CTX.getRegisterInfo()->getEncodingValue(Rs) << ARMII::RegRsShift); 1358 } 1359 1360 unsigned ARMMCCodeEmitter:: 1361 getSORegImmOpValue(const MCInst &MI, unsigned OpIdx, 1362 SmallVectorImpl<MCFixup> &Fixups, 1363 const MCSubtargetInfo &STI) const { 1364 // Sub-operands are [reg, imm]. The first register is Rm, the reg to be 1365 // shifted. The second is the amount to shift by. 1366 // 1367 // {3-0} = Rm. 1368 // {4} = 0 1369 // {6-5} = type 1370 // {11-7} = imm 1371 1372 const MCOperand &MO = MI.getOperand(OpIdx); 1373 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); 1374 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm()); 1375 1376 // Encode Rm. 1377 unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); 1378 1379 // Encode the shift opcode. 1380 unsigned SBits = 0; 1381 1382 // Set shift operand (bit[6:4]). 1383 // LSL - 000 1384 // LSR - 010 1385 // ASR - 100 1386 // ROR - 110 1387 // RRX - 110 and bit[11:8] clear. 1388 switch (SOpc) { 1389 default: llvm_unreachable("Unknown shift opc!"); 1390 case ARM_AM::lsl: SBits = 0x0; break; 1391 case ARM_AM::lsr: SBits = 0x2; break; 1392 case ARM_AM::asr: SBits = 0x4; break; 1393 case ARM_AM::ror: SBits = 0x6; break; 1394 case ARM_AM::rrx: 1395 Binary |= 0x60; 1396 return Binary; 1397 } 1398 1399 // Encode shift_imm bit[11:7]. 1400 Binary |= SBits << 4; 1401 unsigned Offset = ARM_AM::getSORegOffset(MO1.getImm()); 1402 assert(Offset < 32 && "Offset must be in range 0-31!"); 1403 return Binary | (Offset << 7); 1404 } 1405 1406 1407 unsigned ARMMCCodeEmitter:: 1408 getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum, 1409 SmallVectorImpl<MCFixup> &Fixups, 1410 const MCSubtargetInfo &STI) const { 1411 const MCOperand &MO1 = MI.getOperand(OpNum); 1412 const MCOperand &MO2 = MI.getOperand(OpNum+1); 1413 const MCOperand &MO3 = MI.getOperand(OpNum+2); 1414 1415 // Encoded as [Rn, Rm, imm]. 1416 // FIXME: Needs fixup support. 1417 unsigned Value = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg()); 1418 Value <<= 4; 1419 Value |= CTX.getRegisterInfo()->getEncodingValue(MO2.getReg()); 1420 Value <<= 2; 1421 Value |= MO3.getImm(); 1422 1423 return Value; 1424 } 1425 1426 unsigned ARMMCCodeEmitter:: 1427 getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum, 1428 SmallVectorImpl<MCFixup> &Fixups, 1429 const MCSubtargetInfo &STI) const { 1430 const MCOperand &MO1 = MI.getOperand(OpNum); 1431 const MCOperand &MO2 = MI.getOperand(OpNum+1); 1432 1433 // FIXME: Needs fixup support. 1434 unsigned Value = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg()); 1435 1436 // Even though the immediate is 8 bits long, we need 9 bits in order 1437 // to represent the (inverse of the) sign bit. 1438 Value <<= 9; 1439 int32_t tmp = (int32_t)MO2.getImm(); 1440 if (tmp < 0) 1441 tmp = abs(tmp); 1442 else 1443 Value |= 256; // Set the ADD bit 1444 Value |= tmp & 255; 1445 return Value; 1446 } 1447 1448 unsigned ARMMCCodeEmitter:: 1449 getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum, 1450 SmallVectorImpl<MCFixup> &Fixups, 1451 const MCSubtargetInfo &STI) const { 1452 const MCOperand &MO1 = MI.getOperand(OpNum); 1453 1454 // FIXME: Needs fixup support. 1455 unsigned Value = 0; 1456 int32_t tmp = (int32_t)MO1.getImm(); 1457 if (tmp < 0) 1458 tmp = abs(tmp); 1459 else 1460 Value |= 256; // Set the ADD bit 1461 Value |= tmp & 255; 1462 return Value; 1463 } 1464 1465 unsigned ARMMCCodeEmitter:: 1466 getT2SORegOpValue(const MCInst &MI, unsigned OpIdx, 1467 SmallVectorImpl<MCFixup> &Fixups, 1468 const MCSubtargetInfo &STI) const { 1469 // Sub-operands are [reg, imm]. The first register is Rm, the reg to be 1470 // shifted. The second is the amount to shift by. 1471 // 1472 // {3-0} = Rm. 1473 // {4} = 0 1474 // {6-5} = type 1475 // {11-7} = imm 1476 1477 const MCOperand &MO = MI.getOperand(OpIdx); 1478 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); 1479 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm()); 1480 1481 // Encode Rm. 1482 unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); 1483 1484 // Encode the shift opcode. 1485 unsigned SBits = 0; 1486 // Set shift operand (bit[6:4]). 1487 // LSL - 000 1488 // LSR - 010 1489 // ASR - 100 1490 // ROR - 110 1491 switch (SOpc) { 1492 default: llvm_unreachable("Unknown shift opc!"); 1493 case ARM_AM::lsl: SBits = 0x0; break; 1494 case ARM_AM::lsr: SBits = 0x2; break; 1495 case ARM_AM::asr: SBits = 0x4; break; 1496 case ARM_AM::rrx: // FALLTHROUGH 1497 case ARM_AM::ror: SBits = 0x6; break; 1498 } 1499 1500 Binary |= SBits << 4; 1501 if (SOpc == ARM_AM::rrx) 1502 return Binary; 1503 1504 // Encode shift_imm bit[11:7]. 1505 return Binary | ARM_AM::getSORegOffset(MO1.getImm()) << 7; 1506 } 1507 1508 unsigned ARMMCCodeEmitter:: 1509 getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op, 1510 SmallVectorImpl<MCFixup> &Fixups, 1511 const MCSubtargetInfo &STI) const { 1512 // 10 bits. lower 5 bits are are the lsb of the mask, high five bits are the 1513 // msb of the mask. 1514 const MCOperand &MO = MI.getOperand(Op); 1515 uint32_t v = ~MO.getImm(); 1516 uint32_t lsb = countTrailingZeros(v); 1517 uint32_t msb = (32 - countLeadingZeros (v)) - 1; 1518 assert (v != 0 && lsb < 32 && msb < 32 && "Illegal bitfield mask!"); 1519 return lsb | (msb << 5); 1520 } 1521 1522 unsigned ARMMCCodeEmitter:: 1523 getRegisterListOpValue(const MCInst &MI, unsigned Op, 1524 SmallVectorImpl<MCFixup> &Fixups, 1525 const MCSubtargetInfo &STI) const { 1526 // VLDM/VSTM: 1527 // {12-8} = Vd 1528 // {7-0} = Number of registers 1529 // 1530 // LDM/STM: 1531 // {15-0} = Bitfield of GPRs. 1532 unsigned Reg = MI.getOperand(Op).getReg(); 1533 bool SPRRegs = ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg); 1534 bool DPRRegs = ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg); 1535 1536 unsigned Binary = 0; 1537 1538 if (SPRRegs || DPRRegs) { 1539 // VLDM/VSTM 1540 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg); 1541 unsigned NumRegs = (MI.getNumOperands() - Op) & 0xff; 1542 Binary |= (RegNo & 0x1f) << 8; 1543 if (SPRRegs) 1544 Binary |= NumRegs; 1545 else 1546 Binary |= NumRegs * 2; 1547 } else { 1548 for (unsigned I = Op, E = MI.getNumOperands(); I < E; ++I) { 1549 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(MI.getOperand(I).getReg()); 1550 Binary |= 1 << RegNo; 1551 } 1552 } 1553 1554 return Binary; 1555 } 1556 1557 /// getAddrMode6AddressOpValue - Encode an addrmode6 register number along 1558 /// with the alignment operand. 1559 unsigned ARMMCCodeEmitter:: 1560 getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op, 1561 SmallVectorImpl<MCFixup> &Fixups, 1562 const MCSubtargetInfo &STI) const { 1563 const MCOperand &Reg = MI.getOperand(Op); 1564 const MCOperand &Imm = MI.getOperand(Op + 1); 1565 1566 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg()); 1567 unsigned Align = 0; 1568 1569 switch (Imm.getImm()) { 1570 default: break; 1571 case 2: 1572 case 4: 1573 case 8: Align = 0x01; break; 1574 case 16: Align = 0x02; break; 1575 case 32: Align = 0x03; break; 1576 } 1577 1578 return RegNo | (Align << 4); 1579 } 1580 1581 /// getAddrMode6OneLane32AddressOpValue - Encode an addrmode6 register number 1582 /// along with the alignment operand for use in VST1 and VLD1 with size 32. 1583 unsigned ARMMCCodeEmitter:: 1584 getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op, 1585 SmallVectorImpl<MCFixup> &Fixups, 1586 const MCSubtargetInfo &STI) const { 1587 const MCOperand &Reg = MI.getOperand(Op); 1588 const MCOperand &Imm = MI.getOperand(Op + 1); 1589 1590 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg()); 1591 unsigned Align = 0; 1592 1593 switch (Imm.getImm()) { 1594 default: break; 1595 case 8: 1596 case 16: 1597 case 32: // Default '0' value for invalid alignments of 8, 16, 32 bytes. 1598 case 2: Align = 0x00; break; 1599 case 4: Align = 0x03; break; 1600 } 1601 1602 return RegNo | (Align << 4); 1603 } 1604 1605 1606 /// getAddrMode6DupAddressOpValue - Encode an addrmode6 register number and 1607 /// alignment operand for use in VLD-dup instructions. This is the same as 1608 /// getAddrMode6AddressOpValue except for the alignment encoding, which is 1609 /// different for VLD4-dup. 1610 unsigned ARMMCCodeEmitter:: 1611 getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op, 1612 SmallVectorImpl<MCFixup> &Fixups, 1613 const MCSubtargetInfo &STI) const { 1614 const MCOperand &Reg = MI.getOperand(Op); 1615 const MCOperand &Imm = MI.getOperand(Op + 1); 1616 1617 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg()); 1618 unsigned Align = 0; 1619 1620 switch (Imm.getImm()) { 1621 default: break; 1622 case 2: 1623 case 4: 1624 case 8: Align = 0x01; break; 1625 case 16: Align = 0x03; break; 1626 } 1627 1628 return RegNo | (Align << 4); 1629 } 1630 1631 unsigned ARMMCCodeEmitter:: 1632 getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op, 1633 SmallVectorImpl<MCFixup> &Fixups, 1634 const MCSubtargetInfo &STI) const { 1635 const MCOperand &MO = MI.getOperand(Op); 1636 if (MO.getReg() == 0) return 0x0D; 1637 return CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); 1638 } 1639 1640 unsigned ARMMCCodeEmitter:: 1641 getShiftRight8Imm(const MCInst &MI, unsigned Op, 1642 SmallVectorImpl<MCFixup> &Fixups, 1643 const MCSubtargetInfo &STI) const { 1644 return 8 - MI.getOperand(Op).getImm(); 1645 } 1646 1647 unsigned ARMMCCodeEmitter:: 1648 getShiftRight16Imm(const MCInst &MI, unsigned Op, 1649 SmallVectorImpl<MCFixup> &Fixups, 1650 const MCSubtargetInfo &STI) const { 1651 return 16 - MI.getOperand(Op).getImm(); 1652 } 1653 1654 unsigned ARMMCCodeEmitter:: 1655 getShiftRight32Imm(const MCInst &MI, unsigned Op, 1656 SmallVectorImpl<MCFixup> &Fixups, 1657 const MCSubtargetInfo &STI) const { 1658 return 32 - MI.getOperand(Op).getImm(); 1659 } 1660 1661 unsigned ARMMCCodeEmitter:: 1662 getShiftRight64Imm(const MCInst &MI, unsigned Op, 1663 SmallVectorImpl<MCFixup> &Fixups, 1664 const MCSubtargetInfo &STI) const { 1665 return 64 - MI.getOperand(Op).getImm(); 1666 } 1667 1668 void ARMMCCodeEmitter:: 1669 encodeInstruction(const MCInst &MI, raw_ostream &OS, 1670 SmallVectorImpl<MCFixup> &Fixups, 1671 const MCSubtargetInfo &STI) const { 1672 // Pseudo instructions don't get encoded. 1673 const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); 1674 uint64_t TSFlags = Desc.TSFlags; 1675 if ((TSFlags & ARMII::FormMask) == ARMII::Pseudo) 1676 return; 1677 1678 int Size; 1679 if (Desc.getSize() == 2 || Desc.getSize() == 4) 1680 Size = Desc.getSize(); 1681 else 1682 llvm_unreachable("Unexpected instruction size!"); 1683 1684 uint32_t Binary = getBinaryCodeForInstr(MI, Fixups, STI); 1685 // Thumb 32-bit wide instructions need to emit the high order halfword 1686 // first. 1687 if (isThumb(STI) && Size == 4) { 1688 EmitConstant(Binary >> 16, 2, OS); 1689 EmitConstant(Binary & 0xffff, 2, OS); 1690 } else 1691 EmitConstant(Binary, Size, OS); 1692 ++MCNumEmitted; // Keep track of the # of mi's emitted. 1693 } 1694 1695 #include "ARMGenMCCodeEmitter.inc" 1696
