Home | History | Annotate | Download | only in MCTargetDesc 
      1 //===-- MipsTargetStreamer.cpp - Mips Target Streamer Methods -------------===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file provides Mips specific target streamer methods.
     11 //
     12 //===----------------------------------------------------------------------===//
     13 
     14 #include "MipsTargetStreamer.h"
     15 #include "InstPrinter/MipsInstPrinter.h"
     16 #include "MCTargetDesc/MipsABIInfo.h"
     17 #include "MipsELFStreamer.h"
     18 #include "MipsMCExpr.h"
     19 #include "MipsMCTargetDesc.h"
     20 #include "MipsTargetObjectFile.h"
     21 #include "llvm/BinaryFormat/ELF.h"
     22 #include "llvm/MC/MCContext.h"
     23 #include "llvm/MC/MCSectionELF.h"
     24 #include "llvm/MC/MCSubtargetInfo.h"
     25 #include "llvm/MC/MCSymbolELF.h"
     26 #include "llvm/Support/CommandLine.h"
     27 #include "llvm/Support/ErrorHandling.h"
     28 #include "llvm/Support/FormattedStream.h"
     29 
     30 using namespace llvm;
     31 
     32 namespace {
     33 static cl::opt<bool> RoundSectionSizes(
     34     "mips-round-section-sizes", cl::init(false),
     35     cl::desc("Round section sizes up to the section alignment"), cl::Hidden);
     36 } // end anonymous namespace
     37 
     38 MipsTargetStreamer::MipsTargetStreamer(MCStreamer &S)
     39     : MCTargetStreamer(S), ModuleDirectiveAllowed(true) {
     40   GPRInfoSet = FPRInfoSet = FrameInfoSet = false;
     41 }
     42 void MipsTargetStreamer::emitDirectiveSetMicroMips() {}
     43 void MipsTargetStreamer::emitDirectiveSetNoMicroMips() {}
     44 void MipsTargetStreamer::setUsesMicroMips() {}
     45 void MipsTargetStreamer::emitDirectiveSetMips16() {}
     46 void MipsTargetStreamer::emitDirectiveSetNoMips16() { forbidModuleDirective(); }
     47 void MipsTargetStreamer::emitDirectiveSetReorder() { forbidModuleDirective(); }
     48 void MipsTargetStreamer::emitDirectiveSetNoReorder() {}
     49 void MipsTargetStreamer::emitDirectiveSetMacro() { forbidModuleDirective(); }
     50 void MipsTargetStreamer::emitDirectiveSetNoMacro() { forbidModuleDirective(); }
     51 void MipsTargetStreamer::emitDirectiveSetMsa() { forbidModuleDirective(); }
     52 void MipsTargetStreamer::emitDirectiveSetNoMsa() { forbidModuleDirective(); }
     53 void MipsTargetStreamer::emitDirectiveSetMt() {}
     54 void MipsTargetStreamer::emitDirectiveSetNoMt() { forbidModuleDirective(); }
     55 void MipsTargetStreamer::emitDirectiveSetCRC() {}
     56 void MipsTargetStreamer::emitDirectiveSetNoCRC() {}
     57 void MipsTargetStreamer::emitDirectiveSetVirt() {}
     58 void MipsTargetStreamer::emitDirectiveSetNoVirt() {}
     59 void MipsTargetStreamer::emitDirectiveSetGINV() {}
     60 void MipsTargetStreamer::emitDirectiveSetNoGINV() {}
     61 void MipsTargetStreamer::emitDirectiveSetAt() { forbidModuleDirective(); }
     62 void MipsTargetStreamer::emitDirectiveSetAtWithArg(unsigned RegNo) {
     63   forbidModuleDirective();
     64 }
     65 void MipsTargetStreamer::emitDirectiveSetNoAt() { forbidModuleDirective(); }
     66 void MipsTargetStreamer::emitDirectiveEnd(StringRef Name) {}
     67 void MipsTargetStreamer::emitDirectiveEnt(const MCSymbol &Symbol) {}
     68 void MipsTargetStreamer::emitDirectiveAbiCalls() {}
     69 void MipsTargetStreamer::emitDirectiveNaN2008() {}
     70 void MipsTargetStreamer::emitDirectiveNaNLegacy() {}
     71 void MipsTargetStreamer::emitDirectiveOptionPic0() {}
     72 void MipsTargetStreamer::emitDirectiveOptionPic2() {}
     73 void MipsTargetStreamer::emitDirectiveInsn() { forbidModuleDirective(); }
     74 void MipsTargetStreamer::emitFrame(unsigned StackReg, unsigned StackSize,
     75                                    unsigned ReturnReg) {}
     76 void MipsTargetStreamer::emitMask(unsigned CPUBitmask, int CPUTopSavedRegOff) {}
     77 void MipsTargetStreamer::emitFMask(unsigned FPUBitmask, int FPUTopSavedRegOff) {
     78 }
     79 void MipsTargetStreamer::emitDirectiveSetArch(StringRef Arch) {
     80   forbidModuleDirective();
     81 }
     82 void MipsTargetStreamer::emitDirectiveSetMips0() { forbidModuleDirective(); }
     83 void MipsTargetStreamer::emitDirectiveSetMips1() { forbidModuleDirective(); }
     84 void MipsTargetStreamer::emitDirectiveSetMips2() { forbidModuleDirective(); }
     85 void MipsTargetStreamer::emitDirectiveSetMips3() { forbidModuleDirective(); }
     86 void MipsTargetStreamer::emitDirectiveSetMips4() { forbidModuleDirective(); }
     87 void MipsTargetStreamer::emitDirectiveSetMips5() { forbidModuleDirective(); }
     88 void MipsTargetStreamer::emitDirectiveSetMips32() { forbidModuleDirective(); }
     89 void MipsTargetStreamer::emitDirectiveSetMips32R2() { forbidModuleDirective(); }
     90 void MipsTargetStreamer::emitDirectiveSetMips32R3() { forbidModuleDirective(); }
     91 void MipsTargetStreamer::emitDirectiveSetMips32R5() { forbidModuleDirective(); }
     92 void MipsTargetStreamer::emitDirectiveSetMips32R6() { forbidModuleDirective(); }
     93 void MipsTargetStreamer::emitDirectiveSetMips64() { forbidModuleDirective(); }
     94 void MipsTargetStreamer::emitDirectiveSetMips64R2() { forbidModuleDirective(); }
     95 void MipsTargetStreamer::emitDirectiveSetMips64R3() { forbidModuleDirective(); }
     96 void MipsTargetStreamer::emitDirectiveSetMips64R5() { forbidModuleDirective(); }
     97 void MipsTargetStreamer::emitDirectiveSetMips64R6() { forbidModuleDirective(); }
     98 void MipsTargetStreamer::emitDirectiveSetPop() { forbidModuleDirective(); }
     99 void MipsTargetStreamer::emitDirectiveSetPush() { forbidModuleDirective(); }
    100 void MipsTargetStreamer::emitDirectiveSetSoftFloat() {
    101   forbidModuleDirective();
    102 }
    103 void MipsTargetStreamer::emitDirectiveSetHardFloat() {
    104   forbidModuleDirective();
    105 }
    106 void MipsTargetStreamer::emitDirectiveSetDsp() { forbidModuleDirective(); }
    107 void MipsTargetStreamer::emitDirectiveSetDspr2() { forbidModuleDirective(); }
    108 void MipsTargetStreamer::emitDirectiveSetNoDsp() { forbidModuleDirective(); }
    109 void MipsTargetStreamer::emitDirectiveCpLoad(unsigned RegNo) {}
    110 bool MipsTargetStreamer::emitDirectiveCpRestore(
    111     int Offset, function_ref<unsigned()> GetATReg, SMLoc IDLoc,
    112     const MCSubtargetInfo *STI) {
    113   forbidModuleDirective();
    114   return true;
    115 }
    116 void MipsTargetStreamer::emitDirectiveCpsetup(unsigned RegNo, int RegOrOffset,
    117                                               const MCSymbol &Sym, bool IsReg) {
    118 }
    119 void MipsTargetStreamer::emitDirectiveCpreturn(unsigned SaveLocation,
    120                                                bool SaveLocationIsRegister) {}
    121 
    122 void MipsTargetStreamer::emitDirectiveModuleFP() {}
    123 
    124 void MipsTargetStreamer::emitDirectiveModuleOddSPReg() {
    125   if (!ABIFlagsSection.OddSPReg && !ABIFlagsSection.Is32BitABI)
    126     report_fatal_error("+nooddspreg is only valid for O32");
    127 }
    128 void MipsTargetStreamer::emitDirectiveModuleSoftFloat() {}
    129 void MipsTargetStreamer::emitDirectiveModuleHardFloat() {}
    130 void MipsTargetStreamer::emitDirectiveModuleMT() {}
    131 void MipsTargetStreamer::emitDirectiveModuleCRC() {}
    132 void MipsTargetStreamer::emitDirectiveModuleNoCRC() {}
    133 void MipsTargetStreamer::emitDirectiveModuleVirt() {}
    134 void MipsTargetStreamer::emitDirectiveModuleNoVirt() {}
    135 void MipsTargetStreamer::emitDirectiveModuleGINV() {}
    136 void MipsTargetStreamer::emitDirectiveModuleNoGINV() {}
    137 void MipsTargetStreamer::emitDirectiveSetFp(
    138     MipsABIFlagsSection::FpABIKind Value) {
    139   forbidModuleDirective();
    140 }
    141 void MipsTargetStreamer::emitDirectiveSetOddSPReg() { forbidModuleDirective(); }
    142 void MipsTargetStreamer::emitDirectiveSetNoOddSPReg() {
    143   forbidModuleDirective();
    144 }
    145 
    146 void MipsTargetStreamer::emitR(unsigned Opcode, unsigned Reg0, SMLoc IDLoc,
    147                                const MCSubtargetInfo *STI) {
    148   MCInst TmpInst;
    149   TmpInst.setOpcode(Opcode);
    150   TmpInst.addOperand(MCOperand::createReg(Reg0));
    151   TmpInst.setLoc(IDLoc);
    152   getStreamer().EmitInstruction(TmpInst, *STI);
    153 }
    154 
    155 void MipsTargetStreamer::emitRX(unsigned Opcode, unsigned Reg0, MCOperand Op1,
    156                                 SMLoc IDLoc, const MCSubtargetInfo *STI) {
    157   MCInst TmpInst;
    158   TmpInst.setOpcode(Opcode);
    159   TmpInst.addOperand(MCOperand::createReg(Reg0));
    160   TmpInst.addOperand(Op1);
    161   TmpInst.setLoc(IDLoc);
    162   getStreamer().EmitInstruction(TmpInst, *STI);
    163 }
    164 
    165 void MipsTargetStreamer::emitRI(unsigned Opcode, unsigned Reg0, int32_t Imm,
    166                                 SMLoc IDLoc, const MCSubtargetInfo *STI) {
    167   emitRX(Opcode, Reg0, MCOperand::createImm(Imm), IDLoc, STI);
    168 }
    169 
    170 void MipsTargetStreamer::emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1,
    171                                 SMLoc IDLoc, const MCSubtargetInfo *STI) {
    172   emitRX(Opcode, Reg0, MCOperand::createReg(Reg1), IDLoc, STI);
    173 }
    174 
    175 void MipsTargetStreamer::emitII(unsigned Opcode, int16_t Imm1, int16_t Imm2,
    176                                 SMLoc IDLoc, const MCSubtargetInfo *STI) {
    177   MCInst TmpInst;
    178   TmpInst.setOpcode(Opcode);
    179   TmpInst.addOperand(MCOperand::createImm(Imm1));
    180   TmpInst.addOperand(MCOperand::createImm(Imm2));
    181   TmpInst.setLoc(IDLoc);
    182   getStreamer().EmitInstruction(TmpInst, *STI);
    183 }
    184 
    185 void MipsTargetStreamer::emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1,
    186                                  MCOperand Op2, SMLoc IDLoc,
    187                                  const MCSubtargetInfo *STI) {
    188   MCInst TmpInst;
    189   TmpInst.setOpcode(Opcode);
    190   TmpInst.addOperand(MCOperand::createReg(Reg0));
    191   TmpInst.addOperand(MCOperand::createReg(Reg1));
    192   TmpInst.addOperand(Op2);
    193   TmpInst.setLoc(IDLoc);
    194   getStreamer().EmitInstruction(TmpInst, *STI);
    195 }
    196 
    197 void MipsTargetStreamer::emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1,
    198                                  unsigned Reg2, SMLoc IDLoc,
    199                                  const MCSubtargetInfo *STI) {
    200   emitRRX(Opcode, Reg0, Reg1, MCOperand::createReg(Reg2), IDLoc, STI);
    201 }
    202 
    203 void MipsTargetStreamer::emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1,
    204                                  int16_t Imm, SMLoc IDLoc,
    205                                  const MCSubtargetInfo *STI) {
    206   emitRRX(Opcode, Reg0, Reg1, MCOperand::createImm(Imm), IDLoc, STI);
    207 }
    208 
    209 void MipsTargetStreamer::emitRRIII(unsigned Opcode, unsigned Reg0,
    210                                    unsigned Reg1, int16_t Imm0, int16_t Imm1,
    211                                    int16_t Imm2, SMLoc IDLoc,
    212                                    const MCSubtargetInfo *STI) {
    213   MCInst TmpInst;
    214   TmpInst.setOpcode(Opcode);
    215   TmpInst.addOperand(MCOperand::createReg(Reg0));
    216   TmpInst.addOperand(MCOperand::createReg(Reg1));
    217   TmpInst.addOperand(MCOperand::createImm(Imm0));
    218   TmpInst.addOperand(MCOperand::createImm(Imm1));
    219   TmpInst.addOperand(MCOperand::createImm(Imm2));
    220   TmpInst.setLoc(IDLoc);
    221   getStreamer().EmitInstruction(TmpInst, *STI);
    222 }
    223 
    224 void MipsTargetStreamer::emitAddu(unsigned DstReg, unsigned SrcReg,
    225                                   unsigned TrgReg, bool Is64Bit,
    226                                   const MCSubtargetInfo *STI) {
    227   emitRRR(Is64Bit ? Mips::DADDu : Mips::ADDu, DstReg, SrcReg, TrgReg, SMLoc(),
    228           STI);
    229 }
    230 
    231 void MipsTargetStreamer::emitDSLL(unsigned DstReg, unsigned SrcReg,
    232                                   int16_t ShiftAmount, SMLoc IDLoc,
    233                                   const MCSubtargetInfo *STI) {
    234   if (ShiftAmount >= 32) {
    235     emitRRI(Mips::DSLL32, DstReg, SrcReg, ShiftAmount - 32, IDLoc, STI);
    236     return;
    237   }
    238 
    239   emitRRI(Mips::DSLL, DstReg, SrcReg, ShiftAmount, IDLoc, STI);
    240 }
    241 
    242 void MipsTargetStreamer::emitEmptyDelaySlot(bool hasShortDelaySlot, SMLoc IDLoc,
    243                                             const MCSubtargetInfo *STI) {
    244   if (hasShortDelaySlot)
    245     emitRR(Mips::MOVE16_MM, Mips::ZERO, Mips::ZERO, IDLoc, STI);
    246   else
    247     emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI);
    248 }
    249 
    250 void MipsTargetStreamer::emitNop(SMLoc IDLoc, const MCSubtargetInfo *STI) {
    251   emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI);
    252 }
    253 
    254 /// Emit the $gp restore operation for .cprestore.
    255 void MipsTargetStreamer::emitGPRestore(int Offset, SMLoc IDLoc,
    256                                        const MCSubtargetInfo *STI) {
    257   emitLoadWithImmOffset(Mips::LW, Mips::GP, Mips::SP, Offset, Mips::GP, IDLoc,
    258                         STI);
    259 }
    260 
    261 /// Emit a store instruction with an immediate offset.
    262 void MipsTargetStreamer::emitStoreWithImmOffset(
    263     unsigned Opcode, unsigned SrcReg, unsigned BaseReg, int64_t Offset,
    264     function_ref<unsigned()> GetATReg, SMLoc IDLoc,
    265     const MCSubtargetInfo *STI) {
    266   if (isInt<16>(Offset)) {
    267     emitRRI(Opcode, SrcReg, BaseReg, Offset, IDLoc, STI);
    268     return;
    269   }
    270 
    271   // sw $8, offset($8) => lui $at, %hi(offset)
    272   //                      add $at, $at, $8
    273   //                      sw $8, %lo(offset)($at)
    274 
    275   unsigned ATReg = GetATReg();
    276   if (!ATReg)
    277     return;
    278 
    279   unsigned LoOffset = Offset & 0x0000ffff;
    280   unsigned HiOffset = (Offset & 0xffff0000) >> 16;
    281 
    282   // If msb of LoOffset is 1(negative number) we must increment HiOffset
    283   // to account for the sign-extension of the low part.
    284   if (LoOffset & 0x8000)
    285     HiOffset++;
    286 
    287   // Generate the base address in ATReg.
    288   emitRI(Mips::LUi, ATReg, HiOffset, IDLoc, STI);
    289   if (BaseReg != Mips::ZERO)
    290     emitRRR(Mips::ADDu, ATReg, ATReg, BaseReg, IDLoc, STI);
    291   // Emit the store with the adjusted base and offset.
    292   emitRRI(Opcode, SrcReg, ATReg, LoOffset, IDLoc, STI);
    293 }
    294 
    295 /// Emit a store instruction with an symbol offset. Symbols are assumed to be
    296 /// out of range for a simm16 will be expanded to appropriate instructions.
    297 void MipsTargetStreamer::emitStoreWithSymOffset(
    298     unsigned Opcode, unsigned SrcReg, unsigned BaseReg, MCOperand &HiOperand,
    299     MCOperand &LoOperand, unsigned ATReg, SMLoc IDLoc,
    300     const MCSubtargetInfo *STI) {
    301   // sw $8, sym => lui $at, %hi(sym)
    302   //               sw $8, %lo(sym)($at)
    303 
    304   // Generate the base address in ATReg.
    305   emitRX(Mips::LUi, ATReg, HiOperand, IDLoc, STI);
    306   if (BaseReg != Mips::ZERO)
    307     emitRRR(Mips::ADDu, ATReg, ATReg, BaseReg, IDLoc, STI);
    308   // Emit the store with the adjusted base and offset.
    309   emitRRX(Opcode, SrcReg, ATReg, LoOperand, IDLoc, STI);
    310 }
    311 
    312 /// Emit a load instruction with an immediate offset. DstReg and TmpReg are
    313 /// permitted to be the same register iff DstReg is distinct from BaseReg and
    314 /// DstReg is a GPR. It is the callers responsibility to identify such cases
    315 /// and pass the appropriate register in TmpReg.
    316 void MipsTargetStreamer::emitLoadWithImmOffset(unsigned Opcode, unsigned DstReg,
    317                                                unsigned BaseReg, int64_t Offset,
    318                                                unsigned TmpReg, SMLoc IDLoc,
    319                                                const MCSubtargetInfo *STI) {
    320   if (isInt<16>(Offset)) {
    321     emitRRI(Opcode, DstReg, BaseReg, Offset, IDLoc, STI);
    322     return;
    323   }
    324 
    325   // 1) lw $8, offset($9) => lui $8, %hi(offset)
    326   //                         add $8, $8, $9
    327   //                         lw $8, %lo(offset)($9)
    328   // 2) lw $8, offset($8) => lui $at, %hi(offset)
    329   //                         add $at, $at, $8
    330   //                         lw $8, %lo(offset)($at)
    331 
    332   unsigned LoOffset = Offset & 0x0000ffff;
    333   unsigned HiOffset = (Offset & 0xffff0000) >> 16;
    334 
    335   // If msb of LoOffset is 1(negative number) we must increment HiOffset
    336   // to account for the sign-extension of the low part.
    337   if (LoOffset & 0x8000)
    338     HiOffset++;
    339 
    340   // Generate the base address in TmpReg.
    341   emitRI(Mips::LUi, TmpReg, HiOffset, IDLoc, STI);
    342   if (BaseReg != Mips::ZERO)
    343     emitRRR(Mips::ADDu, TmpReg, TmpReg, BaseReg, IDLoc, STI);
    344   // Emit the load with the adjusted base and offset.
    345   emitRRI(Opcode, DstReg, TmpReg, LoOffset, IDLoc, STI);
    346 }
    347 
    348 /// Emit a load instruction with an symbol offset. Symbols are assumed to be
    349 /// out of range for a simm16 will be expanded to appropriate instructions.
    350 /// DstReg and TmpReg are permitted to be the same register iff DstReg is a
    351 /// GPR. It is the callers responsibility to identify such cases and pass the
    352 /// appropriate register in TmpReg.
    353 void MipsTargetStreamer::emitLoadWithSymOffset(unsigned Opcode, unsigned DstReg,
    354                                                unsigned BaseReg,
    355                                                MCOperand &HiOperand,
    356                                                MCOperand &LoOperand,
    357                                                unsigned TmpReg, SMLoc IDLoc,
    358                                                const MCSubtargetInfo *STI) {
    359   // 1) lw $8, sym        => lui $8, %hi(sym)
    360   //                         lw $8, %lo(sym)($8)
    361   // 2) ldc1 $f0, sym     => lui $at, %hi(sym)
    362   //                         ldc1 $f0, %lo(sym)($at)
    363 
    364   // Generate the base address in TmpReg.
    365   emitRX(Mips::LUi, TmpReg, HiOperand, IDLoc, STI);
    366   if (BaseReg != Mips::ZERO)
    367     emitRRR(Mips::ADDu, TmpReg, TmpReg, BaseReg, IDLoc, STI);
    368   // Emit the load with the adjusted base and offset.
    369   emitRRX(Opcode, DstReg, TmpReg, LoOperand, IDLoc, STI);
    370 }
    371 
    372 MipsTargetAsmStreamer::MipsTargetAsmStreamer(MCStreamer &S,
    373                                              formatted_raw_ostream &OS)
    374     : MipsTargetStreamer(S), OS(OS) {}
    375 
    376 void MipsTargetAsmStreamer::emitDirectiveSetMicroMips() {
    377   OS << "\t.set\tmicromips\n";
    378   forbidModuleDirective();
    379 }
    380 
    381 void MipsTargetAsmStreamer::emitDirectiveSetNoMicroMips() {
    382   OS << "\t.set\tnomicromips\n";
    383   forbidModuleDirective();
    384 }
    385 
    386 void MipsTargetAsmStreamer::emitDirectiveSetMips16() {
    387   OS << "\t.set\tmips16\n";
    388   forbidModuleDirective();
    389 }
    390 
    391 void MipsTargetAsmStreamer::emitDirectiveSetNoMips16() {
    392   OS << "\t.set\tnomips16\n";
    393   MipsTargetStreamer::emitDirectiveSetNoMips16();
    394 }
    395 
    396 void MipsTargetAsmStreamer::emitDirectiveSetReorder() {
    397   OS << "\t.set\treorder\n";
    398   MipsTargetStreamer::emitDirectiveSetReorder();
    399 }
    400 
    401 void MipsTargetAsmStreamer::emitDirectiveSetNoReorder() {
    402   OS << "\t.set\tnoreorder\n";
    403   forbidModuleDirective();
    404 }
    405 
    406 void MipsTargetAsmStreamer::emitDirectiveSetMacro() {
    407   OS << "\t.set\tmacro\n";
    408   MipsTargetStreamer::emitDirectiveSetMacro();
    409 }
    410 
    411 void MipsTargetAsmStreamer::emitDirectiveSetNoMacro() {
    412   OS << "\t.set\tnomacro\n";
    413   MipsTargetStreamer::emitDirectiveSetNoMacro();
    414 }
    415 
    416 void MipsTargetAsmStreamer::emitDirectiveSetMsa() {
    417   OS << "\t.set\tmsa\n";
    418   MipsTargetStreamer::emitDirectiveSetMsa();
    419 }
    420 
    421 void MipsTargetAsmStreamer::emitDirectiveSetNoMsa() {
    422   OS << "\t.set\tnomsa\n";
    423   MipsTargetStreamer::emitDirectiveSetNoMsa();
    424 }
    425 
    426 void MipsTargetAsmStreamer::emitDirectiveSetMt() {
    427   OS << "\t.set\tmt\n";
    428   MipsTargetStreamer::emitDirectiveSetMt();
    429 }
    430 
    431 void MipsTargetAsmStreamer::emitDirectiveSetNoMt() {
    432   OS << "\t.set\tnomt\n";
    433   MipsTargetStreamer::emitDirectiveSetNoMt();
    434 }
    435 
    436 void MipsTargetAsmStreamer::emitDirectiveSetCRC() {
    437   OS << "\t.set\tcrc\n";
    438   MipsTargetStreamer::emitDirectiveSetCRC();
    439 }
    440 
    441 void MipsTargetAsmStreamer::emitDirectiveSetNoCRC() {
    442   OS << "\t.set\tnocrc\n";
    443   MipsTargetStreamer::emitDirectiveSetNoCRC();
    444 }
    445 
    446 void MipsTargetAsmStreamer::emitDirectiveSetVirt() {
    447   OS << "\t.set\tvirt\n";
    448   MipsTargetStreamer::emitDirectiveSetVirt();
    449 }
    450 
    451 void MipsTargetAsmStreamer::emitDirectiveSetNoVirt() {
    452   OS << "\t.set\tnovirt\n";
    453   MipsTargetStreamer::emitDirectiveSetNoVirt();
    454 }
    455 
    456 void MipsTargetAsmStreamer::emitDirectiveSetGINV() {
    457   OS << "\t.set\tginv\n";
    458   MipsTargetStreamer::emitDirectiveSetGINV();
    459 }
    460 
    461 void MipsTargetAsmStreamer::emitDirectiveSetNoGINV() {
    462   OS << "\t.set\tnoginv\n";
    463   MipsTargetStreamer::emitDirectiveSetNoGINV();
    464 }
    465 
    466 void MipsTargetAsmStreamer::emitDirectiveSetAt() {
    467   OS << "\t.set\tat\n";
    468   MipsTargetStreamer::emitDirectiveSetAt();
    469 }
    470 
    471 void MipsTargetAsmStreamer::emitDirectiveSetAtWithArg(unsigned RegNo) {
    472   OS << "\t.set\tat=$" << Twine(RegNo) << "\n";
    473   MipsTargetStreamer::emitDirectiveSetAtWithArg(RegNo);
    474 }
    475 
    476 void MipsTargetAsmStreamer::emitDirectiveSetNoAt() {
    477   OS << "\t.set\tnoat\n";
    478   MipsTargetStreamer::emitDirectiveSetNoAt();
    479 }
    480 
    481 void MipsTargetAsmStreamer::emitDirectiveEnd(StringRef Name) {
    482   OS << "\t.end\t" << Name << '\n';
    483 }
    484 
    485 void MipsTargetAsmStreamer::emitDirectiveEnt(const MCSymbol &Symbol) {
    486   OS << "\t.ent\t" << Symbol.getName() << '\n';
    487 }
    488 
    489 void MipsTargetAsmStreamer::emitDirectiveAbiCalls() { OS << "\t.abicalls\n"; }
    490 
    491 void MipsTargetAsmStreamer::emitDirectiveNaN2008() { OS << "\t.nan\t2008\n"; }
    492 
    493 void MipsTargetAsmStreamer::emitDirectiveNaNLegacy() {
    494   OS << "\t.nan\tlegacy\n";
    495 }
    496 
    497 void MipsTargetAsmStreamer::emitDirectiveOptionPic0() {
    498   OS << "\t.option\tpic0\n";
    499 }
    500 
    501 void MipsTargetAsmStreamer::emitDirectiveOptionPic2() {
    502   OS << "\t.option\tpic2\n";
    503 }
    504 
    505 void MipsTargetAsmStreamer::emitDirectiveInsn() {
    506   MipsTargetStreamer::emitDirectiveInsn();
    507   OS << "\t.insn\n";
    508 }
    509 
    510 void MipsTargetAsmStreamer::emitFrame(unsigned StackReg, unsigned StackSize,
    511                                       unsigned ReturnReg) {
    512   OS << "\t.frame\t$"
    513      << StringRef(MipsInstPrinter::getRegisterName(StackReg)).lower() << ","
    514      << StackSize << ",$"
    515      << StringRef(MipsInstPrinter::getRegisterName(ReturnReg)).lower() << '\n';
    516 }
    517 
    518 void MipsTargetAsmStreamer::emitDirectiveSetArch(StringRef Arch) {
    519   OS << "\t.set arch=" << Arch << "\n";
    520   MipsTargetStreamer::emitDirectiveSetArch(Arch);
    521 }
    522 
    523 void MipsTargetAsmStreamer::emitDirectiveSetMips0() {
    524   OS << "\t.set\tmips0\n";
    525   MipsTargetStreamer::emitDirectiveSetMips0();
    526 }
    527 
    528 void MipsTargetAsmStreamer::emitDirectiveSetMips1() {
    529   OS << "\t.set\tmips1\n";
    530   MipsTargetStreamer::emitDirectiveSetMips1();
    531 }
    532 
    533 void MipsTargetAsmStreamer::emitDirectiveSetMips2() {
    534   OS << "\t.set\tmips2\n";
    535   MipsTargetStreamer::emitDirectiveSetMips2();
    536 }
    537 
    538 void MipsTargetAsmStreamer::emitDirectiveSetMips3() {
    539   OS << "\t.set\tmips3\n";
    540   MipsTargetStreamer::emitDirectiveSetMips3();
    541 }
    542 
    543 void MipsTargetAsmStreamer::emitDirectiveSetMips4() {
    544   OS << "\t.set\tmips4\n";
    545   MipsTargetStreamer::emitDirectiveSetMips4();
    546 }
    547 
    548 void MipsTargetAsmStreamer::emitDirectiveSetMips5() {
    549   OS << "\t.set\tmips5\n";
    550   MipsTargetStreamer::emitDirectiveSetMips5();
    551 }
    552 
    553 void MipsTargetAsmStreamer::emitDirectiveSetMips32() {
    554   OS << "\t.set\tmips32\n";
    555   MipsTargetStreamer::emitDirectiveSetMips32();
    556 }
    557 
    558 void MipsTargetAsmStreamer::emitDirectiveSetMips32R2() {
    559   OS << "\t.set\tmips32r2\n";
    560   MipsTargetStreamer::emitDirectiveSetMips32R2();
    561 }
    562 
    563 void MipsTargetAsmStreamer::emitDirectiveSetMips32R3() {
    564   OS << "\t.set\tmips32r3\n";
    565   MipsTargetStreamer::emitDirectiveSetMips32R3();
    566 }
    567 
    568 void MipsTargetAsmStreamer::emitDirectiveSetMips32R5() {
    569   OS << "\t.set\tmips32r5\n";
    570   MipsTargetStreamer::emitDirectiveSetMips32R5();
    571 }
    572 
    573 void MipsTargetAsmStreamer::emitDirectiveSetMips32R6() {
    574   OS << "\t.set\tmips32r6\n";
    575   MipsTargetStreamer::emitDirectiveSetMips32R6();
    576 }
    577 
    578 void MipsTargetAsmStreamer::emitDirectiveSetMips64() {
    579   OS << "\t.set\tmips64\n";
    580   MipsTargetStreamer::emitDirectiveSetMips64();
    581 }
    582 
    583 void MipsTargetAsmStreamer::emitDirectiveSetMips64R2() {
    584   OS << "\t.set\tmips64r2\n";
    585   MipsTargetStreamer::emitDirectiveSetMips64R2();
    586 }
    587 
    588 void MipsTargetAsmStreamer::emitDirectiveSetMips64R3() {
    589   OS << "\t.set\tmips64r3\n";
    590   MipsTargetStreamer::emitDirectiveSetMips64R3();
    591 }
    592 
    593 void MipsTargetAsmStreamer::emitDirectiveSetMips64R5() {
    594   OS << "\t.set\tmips64r5\n";
    595   MipsTargetStreamer::emitDirectiveSetMips64R5();
    596 }
    597 
    598 void MipsTargetAsmStreamer::emitDirectiveSetMips64R6() {
    599   OS << "\t.set\tmips64r6\n";
    600   MipsTargetStreamer::emitDirectiveSetMips64R6();
    601 }
    602 
    603 void MipsTargetAsmStreamer::emitDirectiveSetDsp() {
    604   OS << "\t.set\tdsp\n";
    605   MipsTargetStreamer::emitDirectiveSetDsp();
    606 }
    607 
    608 void MipsTargetAsmStreamer::emitDirectiveSetDspr2() {
    609   OS << "\t.set\tdspr2\n";
    610   MipsTargetStreamer::emitDirectiveSetDspr2();
    611 }
    612 
    613 void MipsTargetAsmStreamer::emitDirectiveSetNoDsp() {
    614   OS << "\t.set\tnodsp\n";
    615   MipsTargetStreamer::emitDirectiveSetNoDsp();
    616 }
    617 
    618 void MipsTargetAsmStreamer::emitDirectiveSetPop() {
    619   OS << "\t.set\tpop\n";
    620   MipsTargetStreamer::emitDirectiveSetPop();
    621 }
    622 
    623 void MipsTargetAsmStreamer::emitDirectiveSetPush() {
    624  OS << "\t.set\tpush\n";
    625  MipsTargetStreamer::emitDirectiveSetPush();
    626 }
    627 
    628 void MipsTargetAsmStreamer::emitDirectiveSetSoftFloat() {
    629   OS << "\t.set\tsoftfloat\n";
    630   MipsTargetStreamer::emitDirectiveSetSoftFloat();
    631 }
    632 
    633 void MipsTargetAsmStreamer::emitDirectiveSetHardFloat() {
    634   OS << "\t.set\thardfloat\n";
    635   MipsTargetStreamer::emitDirectiveSetHardFloat();
    636 }
    637 
    638 // Print a 32 bit hex number with all numbers.
    639 static void printHex32(unsigned Value, raw_ostream &OS) {
    640   OS << "0x";
    641   for (int i = 7; i >= 0; i--)
    642     OS.write_hex((Value & (0xF << (i * 4))) >> (i * 4));
    643 }
    644 
    645 void MipsTargetAsmStreamer::emitMask(unsigned CPUBitmask,
    646                                      int CPUTopSavedRegOff) {
    647   OS << "\t.mask \t";
    648   printHex32(CPUBitmask, OS);
    649   OS << ',' << CPUTopSavedRegOff << '\n';
    650 }
    651 
    652 void MipsTargetAsmStreamer::emitFMask(unsigned FPUBitmask,
    653                                       int FPUTopSavedRegOff) {
    654   OS << "\t.fmask\t";
    655   printHex32(FPUBitmask, OS);
    656   OS << "," << FPUTopSavedRegOff << '\n';
    657 }
    658 
    659 void MipsTargetAsmStreamer::emitDirectiveCpLoad(unsigned RegNo) {
    660   OS << "\t.cpload\t$"
    661      << StringRef(MipsInstPrinter::getRegisterName(RegNo)).lower() << "\n";
    662   forbidModuleDirective();
    663 }
    664 
    665 bool MipsTargetAsmStreamer::emitDirectiveCpRestore(
    666     int Offset, function_ref<unsigned()> GetATReg, SMLoc IDLoc,
    667     const MCSubtargetInfo *STI) {
    668   MipsTargetStreamer::emitDirectiveCpRestore(Offset, GetATReg, IDLoc, STI);
    669   OS << "\t.cprestore\t" << Offset << "\n";
    670   return true;
    671 }
    672 
    673 void MipsTargetAsmStreamer::emitDirectiveCpsetup(unsigned RegNo,
    674                                                  int RegOrOffset,
    675                                                  const MCSymbol &Sym,
    676                                                  bool IsReg) {
    677   OS << "\t.cpsetup\t$"
    678      << StringRef(MipsInstPrinter::getRegisterName(RegNo)).lower() << ", ";
    679 
    680   if (IsReg)
    681     OS << "$"
    682        << StringRef(MipsInstPrinter::getRegisterName(RegOrOffset)).lower();
    683   else
    684     OS << RegOrOffset;
    685 
    686   OS << ", ";
    687 
    688   OS << Sym.getName();
    689   forbidModuleDirective();
    690 }
    691 
    692 void MipsTargetAsmStreamer::emitDirectiveCpreturn(unsigned SaveLocation,
    693                                                   bool SaveLocationIsRegister) {
    694   OS << "\t.cpreturn";
    695   forbidModuleDirective();
    696 }
    697 
    698 void MipsTargetAsmStreamer::emitDirectiveModuleFP() {
    699   OS << "\t.module\tfp=";
    700   OS << ABIFlagsSection.getFpABIString(ABIFlagsSection.getFpABI()) << "\n";
    701 }
    702 
    703 void MipsTargetAsmStreamer::emitDirectiveSetFp(
    704     MipsABIFlagsSection::FpABIKind Value) {
    705   MipsTargetStreamer::emitDirectiveSetFp(Value);
    706 
    707   OS << "\t.set\tfp=";
    708   OS << ABIFlagsSection.getFpABIString(Value) << "\n";
    709 }
    710 
    711 void MipsTargetAsmStreamer::emitDirectiveModuleOddSPReg() {
    712   MipsTargetStreamer::emitDirectiveModuleOddSPReg();
    713 
    714   OS << "\t.module\t" << (ABIFlagsSection.OddSPReg ? "" : "no") << "oddspreg\n";
    715 }
    716 
    717 void MipsTargetAsmStreamer::emitDirectiveSetOddSPReg() {
    718   MipsTargetStreamer::emitDirectiveSetOddSPReg();
    719   OS << "\t.set\toddspreg\n";
    720 }
    721 
    722 void MipsTargetAsmStreamer::emitDirectiveSetNoOddSPReg() {
    723   MipsTargetStreamer::emitDirectiveSetNoOddSPReg();
    724   OS << "\t.set\tnooddspreg\n";
    725 }
    726 
    727 void MipsTargetAsmStreamer::emitDirectiveModuleSoftFloat() {
    728   OS << "\t.module\tsoftfloat\n";
    729 }
    730 
    731 void MipsTargetAsmStreamer::emitDirectiveModuleHardFloat() {
    732   OS << "\t.module\thardfloat\n";
    733 }
    734 
    735 void MipsTargetAsmStreamer::emitDirectiveModuleMT() {
    736   OS << "\t.module\tmt\n";
    737 }
    738 
    739 void MipsTargetAsmStreamer::emitDirectiveModuleCRC() {
    740   OS << "\t.module\tcrc\n";
    741 }
    742 
    743 void MipsTargetAsmStreamer::emitDirectiveModuleNoCRC() {
    744   OS << "\t.module\tnocrc\n";
    745 }
    746 
    747 void MipsTargetAsmStreamer::emitDirectiveModuleVirt() {
    748   OS << "\t.module\tvirt\n";
    749 }
    750 
    751 void MipsTargetAsmStreamer::emitDirectiveModuleNoVirt() {
    752   OS << "\t.module\tnovirt\n";
    753 }
    754 
    755 void MipsTargetAsmStreamer::emitDirectiveModuleGINV() {
    756   OS << "\t.module\tginv\n";
    757 }
    758 
    759 void MipsTargetAsmStreamer::emitDirectiveModuleNoGINV() {
    760   OS << "\t.module\tnoginv\n";
    761 }
    762 
    763 // This part is for ELF object output.
    764 MipsTargetELFStreamer::MipsTargetELFStreamer(MCStreamer &S,
    765                                              const MCSubtargetInfo &STI)
    766     : MipsTargetStreamer(S), MicroMipsEnabled(false), STI(STI) {
    767   MCAssembler &MCA = getStreamer().getAssembler();
    768 
    769   // It's possible that MCObjectFileInfo isn't fully initialized at this point
    770   // due to an initialization order problem where LLVMTargetMachine creates the
    771   // target streamer before TargetLoweringObjectFile calls
    772   // InitializeMCObjectFileInfo. There doesn't seem to be a single place that
    773   // covers all cases so this statement covers most cases and direct object
    774   // emission must call setPic() once MCObjectFileInfo has been initialized. The
    775   // cases we don't handle here are covered by MipsAsmPrinter.
    776   Pic = MCA.getContext().getObjectFileInfo()->isPositionIndependent();
    777 
    778   const FeatureBitset &Features = STI.getFeatureBits();
    779 
    780   // Set the header flags that we can in the constructor.
    781   // FIXME: This is a fairly terrible hack. We set the rest
    782   // of these in the destructor. The problem here is two-fold:
    783   //
    784   // a: Some of the eflags can be set/reset by directives.
    785   // b: There aren't any usage paths that initialize the ABI
    786   //    pointer until after we initialize either an assembler
    787   //    or the target machine.
    788   // We can fix this by making the target streamer construct
    789   // the ABI, but this is fraught with wide ranging dependency
    790   // issues as well.
    791   unsigned EFlags = MCA.getELFHeaderEFlags();
    792 
    793   // FIXME: Fix a dependency issue by instantiating the ABI object to some
    794   // default based off the triple. The triple doesn't describe the target
    795   // fully, but any external user of the API that uses the MCTargetStreamer
    796   // would otherwise crash on assertion failure.
    797 
    798   ABI = MipsABIInfo(
    799       STI.getTargetTriple().getArch() == Triple::ArchType::mipsel ||
    800               STI.getTargetTriple().getArch() == Triple::ArchType::mips
    801           ? MipsABIInfo::O32()
    802           : MipsABIInfo::N64());
    803 
    804   // Architecture
    805   if (Features[Mips::FeatureMips64r6])
    806     EFlags |= ELF::EF_MIPS_ARCH_64R6;
    807   else if (Features[Mips::FeatureMips64r2] ||
    808            Features[Mips::FeatureMips64r3] ||
    809            Features[Mips::FeatureMips64r5])
    810     EFlags |= ELF::EF_MIPS_ARCH_64R2;
    811   else if (Features[Mips::FeatureMips64])
    812     EFlags |= ELF::EF_MIPS_ARCH_64;
    813   else if (Features[Mips::FeatureMips5])
    814     EFlags |= ELF::EF_MIPS_ARCH_5;
    815   else if (Features[Mips::FeatureMips4])
    816     EFlags |= ELF::EF_MIPS_ARCH_4;
    817   else if (Features[Mips::FeatureMips3])
    818     EFlags |= ELF::EF_MIPS_ARCH_3;
    819   else if (Features[Mips::FeatureMips32r6])
    820     EFlags |= ELF::EF_MIPS_ARCH_32R6;
    821   else if (Features[Mips::FeatureMips32r2] ||
    822            Features[Mips::FeatureMips32r3] ||
    823            Features[Mips::FeatureMips32r5])
    824     EFlags |= ELF::EF_MIPS_ARCH_32R2;
    825   else if (Features[Mips::FeatureMips32])
    826     EFlags |= ELF::EF_MIPS_ARCH_32;
    827   else if (Features[Mips::FeatureMips2])
    828     EFlags |= ELF::EF_MIPS_ARCH_2;
    829   else
    830     EFlags |= ELF::EF_MIPS_ARCH_1;
    831 
    832   // Machine
    833   if (Features[Mips::FeatureCnMips])
    834     EFlags |= ELF::EF_MIPS_MACH_OCTEON;
    835 
    836   // Other options.
    837   if (Features[Mips::FeatureNaN2008])
    838     EFlags |= ELF::EF_MIPS_NAN2008;
    839 
    840   MCA.setELFHeaderEFlags(EFlags);
    841 }
    842 
    843 void MipsTargetELFStreamer::emitLabel(MCSymbol *S) {
    844   auto *Symbol = cast<MCSymbolELF>(S);
    845   getStreamer().getAssembler().registerSymbol(*Symbol);
    846   uint8_t Type = Symbol->getType();
    847   if (Type != ELF::STT_FUNC)
    848     return;
    849 
    850   if (isMicroMipsEnabled())
    851     Symbol->setOther(ELF::STO_MIPS_MICROMIPS);
    852 }
    853 
    854 void MipsTargetELFStreamer::finish() {
    855   MCAssembler &MCA = getStreamer().getAssembler();
    856   const MCObjectFileInfo &OFI = *MCA.getContext().getObjectFileInfo();
    857 
    858   // .bss, .text and .data are always at least 16-byte aligned.
    859   MCSection &TextSection = *OFI.getTextSection();
    860   MCA.registerSection(TextSection);
    861   MCSection &DataSection = *OFI.getDataSection();
    862   MCA.registerSection(DataSection);
    863   MCSection &BSSSection = *OFI.getBSSSection();
    864   MCA.registerSection(BSSSection);
    865 
    866   TextSection.setAlignment(std::max(16u, TextSection.getAlignment()));
    867   DataSection.setAlignment(std::max(16u, DataSection.getAlignment()));
    868   BSSSection.setAlignment(std::max(16u, BSSSection.getAlignment()));
    869 
    870   if (RoundSectionSizes) {
    871     // Make sections sizes a multiple of the alignment. This is useful for
    872     // verifying the output of IAS against the output of other assemblers but
    873     // it's not necessary to produce a correct object and increases section
    874     // size.
    875     MCStreamer &OS = getStreamer();
    876     for (MCSection &S : MCA) {
    877       MCSectionELF &Section = static_cast<MCSectionELF &>(S);
    878 
    879       unsigned Alignment = Section.getAlignment();
    880       if (Alignment) {
    881         OS.SwitchSection(&Section);
    882         if (Section.UseCodeAlign())
    883           OS.EmitCodeAlignment(Alignment, Alignment);
    884         else
    885           OS.EmitValueToAlignment(Alignment, 0, 1, Alignment);
    886       }
    887     }
    888   }
    889 
    890   const FeatureBitset &Features = STI.getFeatureBits();
    891 
    892   // Update e_header flags. See the FIXME and comment above in
    893   // the constructor for a full rundown on this.
    894   unsigned EFlags = MCA.getELFHeaderEFlags();
    895 
    896   // ABI
    897   // N64 does not require any ABI bits.
    898   if (getABI().IsO32())
    899     EFlags |= ELF::EF_MIPS_ABI_O32;
    900   else if (getABI().IsN32())
    901     EFlags |= ELF::EF_MIPS_ABI2;
    902 
    903   if (Features[Mips::FeatureGP64Bit]) {
    904     if (getABI().IsO32())
    905       EFlags |= ELF::EF_MIPS_32BITMODE; /* Compatibility Mode */
    906   } else if (Features[Mips::FeatureMips64r2] || Features[Mips::FeatureMips64])
    907     EFlags |= ELF::EF_MIPS_32BITMODE;
    908 
    909   // -mplt is not implemented but we should act as if it was
    910   // given.
    911   if (!Features[Mips::FeatureNoABICalls])
    912     EFlags |= ELF::EF_MIPS_CPIC;
    913 
    914   if (Pic)
    915     EFlags |= ELF::EF_MIPS_PIC | ELF::EF_MIPS_CPIC;
    916 
    917   MCA.setELFHeaderEFlags(EFlags);
    918 
    919   // Emit all the option records.
    920   // At the moment we are only emitting .Mips.options (ODK_REGINFO) and
    921   // .reginfo.
    922   MipsELFStreamer &MEF = static_cast<MipsELFStreamer &>(Streamer);
    923   MEF.EmitMipsOptionRecords();
    924 
    925   emitMipsAbiFlags();
    926 }
    927 
    928 void MipsTargetELFStreamer::emitAssignment(MCSymbol *S, const MCExpr *Value) {
    929   auto *Symbol = cast<MCSymbolELF>(S);
    930   // If on rhs is micromips symbol then mark Symbol as microMips.
    931   if (Value->getKind() != MCExpr::SymbolRef)
    932     return;
    933   const auto &RhsSym = cast<MCSymbolELF>(
    934       static_cast<const MCSymbolRefExpr *>(Value)->getSymbol());
    935 
    936   if (!(RhsSym.getOther() & ELF::STO_MIPS_MICROMIPS))
    937     return;
    938 
    939   Symbol->setOther(ELF::STO_MIPS_MICROMIPS);
    940 }
    941 
    942 MCELFStreamer &MipsTargetELFStreamer::getStreamer() {
    943   return static_cast<MCELFStreamer &>(Streamer);
    944 }
    945 
    946 void MipsTargetELFStreamer::emitDirectiveSetMicroMips() {
    947   MicroMipsEnabled = true;
    948   forbidModuleDirective();
    949 }
    950 
    951 void MipsTargetELFStreamer::emitDirectiveSetNoMicroMips() {
    952   MicroMipsEnabled = false;
    953   forbidModuleDirective();
    954 }
    955 
    956 void MipsTargetELFStreamer::setUsesMicroMips() {
    957   MCAssembler &MCA = getStreamer().getAssembler();
    958   unsigned Flags = MCA.getELFHeaderEFlags();
    959   Flags |= ELF::EF_MIPS_MICROMIPS;
    960   MCA.setELFHeaderEFlags(Flags);
    961 }
    962 
    963 void MipsTargetELFStreamer::emitDirectiveSetMips16() {
    964   MCAssembler &MCA = getStreamer().getAssembler();
    965   unsigned Flags = MCA.getELFHeaderEFlags();
    966   Flags |= ELF::EF_MIPS_ARCH_ASE_M16;
    967   MCA.setELFHeaderEFlags(Flags);
    968   forbidModuleDirective();
    969 }
    970 
    971 void MipsTargetELFStreamer::emitDirectiveSetNoReorder() {
    972   MCAssembler &MCA = getStreamer().getAssembler();
    973   unsigned Flags = MCA.getELFHeaderEFlags();
    974   Flags |= ELF::EF_MIPS_NOREORDER;
    975   MCA.setELFHeaderEFlags(Flags);
    976   forbidModuleDirective();
    977 }
    978 
    979 void MipsTargetELFStreamer::emitDirectiveEnd(StringRef Name) {
    980   MCAssembler &MCA = getStreamer().getAssembler();
    981   MCContext &Context = MCA.getContext();
    982   MCStreamer &OS = getStreamer();
    983 
    984   MCSectionELF *Sec = Context.getELFSection(".pdr", ELF::SHT_PROGBITS, 0);
    985 
    986   MCSymbol *Sym = Context.getOrCreateSymbol(Name);
    987   const MCSymbolRefExpr *ExprRef =
    988       MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, Context);
    989 
    990   MCA.registerSection(*Sec);
    991   Sec->setAlignment(4);
    992 
    993   OS.PushSection();
    994 
    995   OS.SwitchSection(Sec);
    996 
    997   OS.EmitValueImpl(ExprRef, 4);
    998 
    999   OS.EmitIntValue(GPRInfoSet ? GPRBitMask : 0, 4); // reg_mask
   1000   OS.EmitIntValue(GPRInfoSet ? GPROffset : 0, 4);  // reg_offset
   1001 
   1002   OS.EmitIntValue(FPRInfoSet ? FPRBitMask : 0, 4); // fpreg_mask
   1003   OS.EmitIntValue(FPRInfoSet ? FPROffset : 0, 4);  // fpreg_offset
   1004 
   1005   OS.EmitIntValue(FrameInfoSet ? FrameOffset : 0, 4); // frame_offset
   1006   OS.EmitIntValue(FrameInfoSet ? FrameReg : 0, 4);    // frame_reg
   1007   OS.EmitIntValue(FrameInfoSet ? ReturnReg : 0, 4);   // return_reg
   1008 
   1009   // The .end directive marks the end of a procedure. Invalidate
   1010   // the information gathered up until this point.
   1011   GPRInfoSet = FPRInfoSet = FrameInfoSet = false;
   1012 
   1013   OS.PopSection();
   1014 
   1015   // .end also implicitly sets the size.
   1016   MCSymbol *CurPCSym = Context.createTempSymbol();
   1017   OS.EmitLabel(CurPCSym);
   1018   const MCExpr *Size = MCBinaryExpr::createSub(
   1019       MCSymbolRefExpr::create(CurPCSym, MCSymbolRefExpr::VK_None, Context),
   1020       ExprRef, Context);
   1021 
   1022   // The ELFObjectWriter can determine the absolute size as it has access to
   1023   // the layout information of the assembly file, so a size expression rather
   1024   // than an absolute value is ok here.
   1025   static_cast<MCSymbolELF *>(Sym)->setSize(Size);
   1026 }
   1027 
   1028 void MipsTargetELFStreamer::emitDirectiveEnt(const MCSymbol &Symbol) {
   1029   GPRInfoSet = FPRInfoSet = FrameInfoSet = false;
   1030 
   1031   // .ent also acts like an implicit '.type symbol, STT_FUNC'
   1032   static_cast<const MCSymbolELF &>(Symbol).setType(ELF::STT_FUNC);
   1033 }
   1034 
   1035 void MipsTargetELFStreamer::emitDirectiveAbiCalls() {
   1036   MCAssembler &MCA = getStreamer().getAssembler();
   1037   unsigned Flags = MCA.getELFHeaderEFlags();
   1038   Flags |= ELF::EF_MIPS_CPIC | ELF::EF_MIPS_PIC;
   1039   MCA.setELFHeaderEFlags(Flags);
   1040 }
   1041 
   1042 void MipsTargetELFStreamer::emitDirectiveNaN2008() {
   1043   MCAssembler &MCA = getStreamer().getAssembler();
   1044   unsigned Flags = MCA.getELFHeaderEFlags();
   1045   Flags |= ELF::EF_MIPS_NAN2008;
   1046   MCA.setELFHeaderEFlags(Flags);
   1047 }
   1048 
   1049 void MipsTargetELFStreamer::emitDirectiveNaNLegacy() {
   1050   MCAssembler &MCA = getStreamer().getAssembler();
   1051   unsigned Flags = MCA.getELFHeaderEFlags();
   1052   Flags &= ~ELF::EF_MIPS_NAN2008;
   1053   MCA.setELFHeaderEFlags(Flags);
   1054 }
   1055 
   1056 void MipsTargetELFStreamer::emitDirectiveOptionPic0() {
   1057   MCAssembler &MCA = getStreamer().getAssembler();
   1058   unsigned Flags = MCA.getELFHeaderEFlags();
   1059   // This option overrides other PIC options like -KPIC.
   1060   Pic = false;
   1061   Flags &= ~ELF::EF_MIPS_PIC;
   1062   MCA.setELFHeaderEFlags(Flags);
   1063 }
   1064 
   1065 void MipsTargetELFStreamer::emitDirectiveOptionPic2() {
   1066   MCAssembler &MCA = getStreamer().getAssembler();
   1067   unsigned Flags = MCA.getELFHeaderEFlags();
   1068   Pic = true;
   1069   // NOTE: We are following the GAS behaviour here which means the directive
   1070   // 'pic2' also sets the CPIC bit in the ELF header. This is different from
   1071   // what is stated in the SYSV ABI which consider the bits EF_MIPS_PIC and
   1072   // EF_MIPS_CPIC to be mutually exclusive.
   1073   Flags |= ELF::EF_MIPS_PIC | ELF::EF_MIPS_CPIC;
   1074   MCA.setELFHeaderEFlags(Flags);
   1075 }
   1076 
   1077 void MipsTargetELFStreamer::emitDirectiveInsn() {
   1078   MipsTargetStreamer::emitDirectiveInsn();
   1079   MipsELFStreamer &MEF = static_cast<MipsELFStreamer &>(Streamer);
   1080   MEF.createPendingLabelRelocs();
   1081 }
   1082 
   1083 void MipsTargetELFStreamer::emitFrame(unsigned StackReg, unsigned StackSize,
   1084                                       unsigned ReturnReg_) {
   1085   MCContext &Context = getStreamer().getAssembler().getContext();
   1086   const MCRegisterInfo *RegInfo = Context.getRegisterInfo();
   1087 
   1088   FrameInfoSet = true;
   1089   FrameReg = RegInfo->getEncodingValue(StackReg);
   1090   FrameOffset = StackSize;
   1091   ReturnReg = RegInfo->getEncodingValue(ReturnReg_);
   1092 }
   1093 
   1094 void MipsTargetELFStreamer::emitMask(unsigned CPUBitmask,
   1095                                      int CPUTopSavedRegOff) {
   1096   GPRInfoSet = true;
   1097   GPRBitMask = CPUBitmask;
   1098   GPROffset = CPUTopSavedRegOff;
   1099 }
   1100 
   1101 void MipsTargetELFStreamer::emitFMask(unsigned FPUBitmask,
   1102                                       int FPUTopSavedRegOff) {
   1103   FPRInfoSet = true;
   1104   FPRBitMask = FPUBitmask;
   1105   FPROffset = FPUTopSavedRegOff;
   1106 }
   1107 
   1108 void MipsTargetELFStreamer::emitDirectiveCpLoad(unsigned RegNo) {
   1109   // .cpload $reg
   1110   // This directive expands to:
   1111   // lui   $gp, %hi(_gp_disp)
   1112   // addui $gp, $gp, %lo(_gp_disp)
   1113   // addu  $gp, $gp, $reg
   1114   // when support for position independent code is enabled.
   1115   if (!Pic || (getABI().IsN32() || getABI().IsN64()))
   1116     return;
   1117 
   1118   // There's a GNU extension controlled by -mno-shared that allows
   1119   // locally-binding symbols to be accessed using absolute addresses.
   1120   // This is currently not supported. When supported -mno-shared makes
   1121   // .cpload expand to:
   1122   //   lui     $gp, %hi(__gnu_local_gp)
   1123   //   addiu   $gp, $gp, %lo(__gnu_local_gp)
   1124 
   1125   StringRef SymName("_gp_disp");
   1126   MCAssembler &MCA = getStreamer().getAssembler();
   1127   MCSymbol *GP_Disp = MCA.getContext().getOrCreateSymbol(SymName);
   1128   MCA.registerSymbol(*GP_Disp);
   1129 
   1130   MCInst TmpInst;
   1131   TmpInst.setOpcode(Mips::LUi);
   1132   TmpInst.addOperand(MCOperand::createReg(Mips::GP));
   1133   const MCExpr *HiSym = MipsMCExpr::create(
   1134       MipsMCExpr::MEK_HI,
   1135       MCSymbolRefExpr::create("_gp_disp", MCSymbolRefExpr::VK_None,
   1136                               MCA.getContext()),
   1137       MCA.getContext());
   1138   TmpInst.addOperand(MCOperand::createExpr(HiSym));
   1139   getStreamer().EmitInstruction(TmpInst, STI);
   1140 
   1141   TmpInst.clear();
   1142 
   1143   TmpInst.setOpcode(Mips::ADDiu);
   1144   TmpInst.addOperand(MCOperand::createReg(Mips::GP));
   1145   TmpInst.addOperand(MCOperand::createReg(Mips::GP));
   1146   const MCExpr *LoSym = MipsMCExpr::create(
   1147       MipsMCExpr::MEK_LO,
   1148       MCSymbolRefExpr::create("_gp_disp", MCSymbolRefExpr::VK_None,
   1149                               MCA.getContext()),
   1150       MCA.getContext());
   1151   TmpInst.addOperand(MCOperand::createExpr(LoSym));
   1152   getStreamer().EmitInstruction(TmpInst, STI);
   1153 
   1154   TmpInst.clear();
   1155 
   1156   TmpInst.setOpcode(Mips::ADDu);
   1157   TmpInst.addOperand(MCOperand::createReg(Mips::GP));
   1158   TmpInst.addOperand(MCOperand::createReg(Mips::GP));
   1159   TmpInst.addOperand(MCOperand::createReg(RegNo));
   1160   getStreamer().EmitInstruction(TmpInst, STI);
   1161 
   1162   forbidModuleDirective();
   1163 }
   1164 
   1165 bool MipsTargetELFStreamer::emitDirectiveCpRestore(
   1166     int Offset, function_ref<unsigned()> GetATReg, SMLoc IDLoc,
   1167     const MCSubtargetInfo *STI) {
   1168   MipsTargetStreamer::emitDirectiveCpRestore(Offset, GetATReg, IDLoc, STI);
   1169   // .cprestore offset
   1170   // When PIC mode is enabled and the O32 ABI is used, this directive expands
   1171   // to:
   1172   //    sw $gp, offset($sp)
   1173   // and adds a corresponding LW after every JAL.
   1174 
   1175   // Note that .cprestore is ignored if used with the N32 and N64 ABIs or if it
   1176   // is used in non-PIC mode.
   1177   if (!Pic || (getABI().IsN32() || getABI().IsN64()))
   1178     return true;
   1179 
   1180   // Store the $gp on the stack.
   1181   emitStoreWithImmOffset(Mips::SW, Mips::GP, Mips::SP, Offset, GetATReg, IDLoc,
   1182                          STI);
   1183   return true;
   1184 }
   1185 
   1186 void MipsTargetELFStreamer::emitDirectiveCpsetup(unsigned RegNo,
   1187                                                  int RegOrOffset,
   1188                                                  const MCSymbol &Sym,
   1189                                                  bool IsReg) {
   1190   // Only N32 and N64 emit anything for .cpsetup iff PIC is set.
   1191   if (!Pic || !(getABI().IsN32() || getABI().IsN64()))
   1192     return;
   1193 
   1194   forbidModuleDirective();
   1195 
   1196   MCAssembler &MCA = getStreamer().getAssembler();
   1197   MCInst Inst;
   1198 
   1199   // Either store the old $gp in a register or on the stack
   1200   if (IsReg) {
   1201     // move $save, $gpreg
   1202     emitRRR(Mips::OR64, RegOrOffset, Mips::GP, Mips::ZERO, SMLoc(), &STI);
   1203   } else {
   1204     // sd $gpreg, offset($sp)
   1205     emitRRI(Mips::SD, Mips::GP, Mips::SP, RegOrOffset, SMLoc(), &STI);
   1206   }
   1207 
   1208   if (getABI().IsN32()) {
   1209     MCSymbol *GPSym = MCA.getContext().getOrCreateSymbol("__gnu_local_gp");
   1210     const MipsMCExpr *HiExpr = MipsMCExpr::create(
   1211         MipsMCExpr::MEK_HI, MCSymbolRefExpr::create(GPSym, MCA.getContext()),
   1212         MCA.getContext());
   1213     const MipsMCExpr *LoExpr = MipsMCExpr::create(
   1214         MipsMCExpr::MEK_LO, MCSymbolRefExpr::create(GPSym, MCA.getContext()),
   1215         MCA.getContext());
   1216 
   1217     // lui $gp, %hi(__gnu_local_gp)
   1218     emitRX(Mips::LUi, Mips::GP, MCOperand::createExpr(HiExpr), SMLoc(), &STI);
   1219 
   1220     // addiu  $gp, $gp, %lo(__gnu_local_gp)
   1221     emitRRX(Mips::ADDiu, Mips::GP, Mips::GP, MCOperand::createExpr(LoExpr),
   1222             SMLoc(), &STI);
   1223 
   1224     return;
   1225   }
   1226 
   1227   const MipsMCExpr *HiExpr = MipsMCExpr::createGpOff(
   1228       MipsMCExpr::MEK_HI, MCSymbolRefExpr::create(&Sym, MCA.getContext()),
   1229       MCA.getContext());
   1230   const MipsMCExpr *LoExpr = MipsMCExpr::createGpOff(
   1231       MipsMCExpr::MEK_LO, MCSymbolRefExpr::create(&Sym, MCA.getContext()),
   1232       MCA.getContext());
   1233 
   1234   // lui $gp, %hi(%neg(%gp_rel(funcSym)))
   1235   emitRX(Mips::LUi, Mips::GP, MCOperand::createExpr(HiExpr), SMLoc(), &STI);
   1236 
   1237   // addiu  $gp, $gp, %lo(%neg(%gp_rel(funcSym)))
   1238   emitRRX(Mips::ADDiu, Mips::GP, Mips::GP, MCOperand::createExpr(LoExpr),
   1239           SMLoc(), &STI);
   1240 
   1241   // daddu  $gp, $gp, $funcreg
   1242   emitRRR(Mips::DADDu, Mips::GP, Mips::GP, RegNo, SMLoc(), &STI);
   1243 }
   1244 
   1245 void MipsTargetELFStreamer::emitDirectiveCpreturn(unsigned SaveLocation,
   1246                                                   bool SaveLocationIsRegister) {
   1247   // Only N32 and N64 emit anything for .cpreturn iff PIC is set.
   1248   if (!Pic || !(getABI().IsN32() || getABI().IsN64()))
   1249     return;
   1250 
   1251   MCInst Inst;
   1252   // Either restore the old $gp from a register or on the stack
   1253   if (SaveLocationIsRegister) {
   1254     Inst.setOpcode(Mips::OR);
   1255     Inst.addOperand(MCOperand::createReg(Mips::GP));
   1256     Inst.addOperand(MCOperand::createReg(SaveLocation));
   1257     Inst.addOperand(MCOperand::createReg(Mips::ZERO));
   1258   } else {
   1259     Inst.setOpcode(Mips::LD);
   1260     Inst.addOperand(MCOperand::createReg(Mips::GP));
   1261     Inst.addOperand(MCOperand::createReg(Mips::SP));
   1262     Inst.addOperand(MCOperand::createImm(SaveLocation));
   1263   }
   1264   getStreamer().EmitInstruction(Inst, STI);
   1265 
   1266   forbidModuleDirective();
   1267 }
   1268 
   1269 void MipsTargetELFStreamer::emitMipsAbiFlags() {
   1270   MCAssembler &MCA = getStreamer().getAssembler();
   1271   MCContext &Context = MCA.getContext();
   1272   MCStreamer &OS = getStreamer();
   1273   MCSectionELF *Sec = Context.getELFSection(
   1274       ".MIPS.abiflags", ELF::SHT_MIPS_ABIFLAGS, ELF::SHF_ALLOC, 24, "");
   1275   MCA.registerSection(*Sec);
   1276   Sec->setAlignment(8);
   1277   OS.SwitchSection(Sec);
   1278 
   1279   OS << ABIFlagsSection;
   1280 }
   1281