1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2014-2015 Freescale Semiconductor 4 */ 5 6 #include <common.h> 7 #include <fsl_immap.h> 8 #include <fsl_ifc.h> 9 #include <ahci.h> 10 #include <scsi.h> 11 #include <asm/arch/fsl_serdes.h> 12 #include <asm/arch/soc.h> 13 #include <asm/io.h> 14 #include <asm/global_data.h> 15 #include <asm/arch-fsl-layerscape/config.h> 16 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS 17 #include <fsl_csu.h> 18 #endif 19 #ifdef CONFIG_SYS_FSL_DDR 20 #include <fsl_ddr_sdram.h> 21 #include <fsl_ddr.h> 22 #endif 23 #ifdef CONFIG_CHAIN_OF_TRUST 24 #include <fsl_validate.h> 25 #endif 26 #include <fsl_immap.h> 27 28 bool soc_has_dp_ddr(void) 29 { 30 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 31 u32 svr = gur_in32(&gur->svr); 32 33 /* LS2085A, LS2088A, LS2048A has DP_DDR */ 34 if ((SVR_SOC_VER(svr) == SVR_LS2085A) || 35 (SVR_SOC_VER(svr) == SVR_LS2088A) || 36 (SVR_SOC_VER(svr) == SVR_LS2048A)) 37 return true; 38 39 return false; 40 } 41 42 bool soc_has_aiop(void) 43 { 44 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 45 u32 svr = gur_in32(&gur->svr); 46 47 /* LS2085A has AIOP */ 48 if (SVR_SOC_VER(svr) == SVR_LS2085A) 49 return true; 50 51 return false; 52 } 53 54 static inline void set_usb_txvreftune(u32 __iomem *scfg, u32 offset) 55 { 56 scfg_clrsetbits32(scfg + offset / 4, 57 0xF << 6, 58 SCFG_USB_TXVREFTUNE << 6); 59 } 60 61 static void erratum_a009008(void) 62 { 63 #ifdef CONFIG_SYS_FSL_ERRATUM_A009008 64 u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE; 65 66 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \ 67 defined(CONFIG_ARCH_LS1012A) 68 set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB1); 69 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) 70 set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB2); 71 set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB3); 72 #endif 73 #elif defined(CONFIG_ARCH_LS2080A) 74 set_usb_txvreftune(scfg, SCFG_USB3PRM1CR); 75 #endif 76 #endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */ 77 } 78 79 static inline void set_usb_sqrxtune(u32 __iomem *scfg, u32 offset) 80 { 81 scfg_clrbits32(scfg + offset / 4, 82 SCFG_USB_SQRXTUNE_MASK << 23); 83 } 84 85 static void erratum_a009798(void) 86 { 87 #ifdef CONFIG_SYS_FSL_ERRATUM_A009798 88 u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE; 89 90 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \ 91 defined(CONFIG_ARCH_LS1012A) 92 set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB1); 93 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) 94 set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB2); 95 set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB3); 96 #endif 97 #elif defined(CONFIG_ARCH_LS2080A) 98 set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR); 99 #endif 100 #endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */ 101 } 102 103 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \ 104 defined(CONFIG_ARCH_LS1012A) 105 static inline void set_usb_pcstxswingfull(u32 __iomem *scfg, u32 offset) 106 { 107 scfg_clrsetbits32(scfg + offset / 4, 108 0x7F << 9, 109 SCFG_USB_PCSTXSWINGFULL << 9); 110 } 111 #endif 112 113 static void erratum_a008997(void) 114 { 115 #ifdef CONFIG_SYS_FSL_ERRATUM_A008997 116 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \ 117 defined(CONFIG_ARCH_LS1012A) 118 u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE; 119 120 set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB1); 121 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) 122 set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB2); 123 set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB3); 124 #endif 125 #endif 126 #endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */ 127 } 128 129 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \ 130 defined(CONFIG_ARCH_LS1012A) 131 132 #define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy) \ 133 out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \ 134 out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2); \ 135 out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3); \ 136 out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4) 137 138 #elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) 139 140 #define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy) \ 141 out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \ 142 out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2); \ 143 out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3); \ 144 out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4) 145 146 #endif 147 148 static void erratum_a009007(void) 149 { 150 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \ 151 defined(CONFIG_ARCH_LS1012A) 152 void __iomem *usb_phy = (void __iomem *)SCFG_USB_PHY1; 153 154 PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy); 155 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) 156 usb_phy = (void __iomem *)SCFG_USB_PHY2; 157 PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy); 158 159 usb_phy = (void __iomem *)SCFG_USB_PHY3; 160 PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy); 161 #endif 162 #elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) 163 void __iomem *dcsr = (void __iomem *)DCSR_BASE; 164 165 PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY1); 166 PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY2); 167 #endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */ 168 } 169 170 #if defined(CONFIG_FSL_LSCH3) 171 /* 172 * This erratum requires setting a value to eddrtqcr1 to 173 * optimal the DDR performance. 174 */ 175 static void erratum_a008336(void) 176 { 177 #ifdef CONFIG_SYS_FSL_ERRATUM_A008336 178 u32 *eddrtqcr1; 179 180 #ifdef CONFIG_SYS_FSL_DCSR_DDR_ADDR 181 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800; 182 if (fsl_ddr_get_version(0) == 0x50200) 183 out_le32(eddrtqcr1, 0x63b30002); 184 #endif 185 #ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR 186 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800; 187 if (fsl_ddr_get_version(0) == 0x50200) 188 out_le32(eddrtqcr1, 0x63b30002); 189 #endif 190 #endif 191 } 192 193 /* 194 * This erratum requires a register write before being Memory 195 * controller 3 being enabled. 196 */ 197 static void erratum_a008514(void) 198 { 199 #ifdef CONFIG_SYS_FSL_ERRATUM_A008514 200 u32 *eddrtqcr1; 201 202 #ifdef CONFIG_SYS_FSL_DCSR_DDR3_ADDR 203 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800; 204 out_le32(eddrtqcr1, 0x63b20002); 205 #endif 206 #endif 207 } 208 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635 209 #define PLATFORM_CYCLE_ENV_VAR "a009635_interval_val" 210 211 static unsigned long get_internval_val_mhz(void) 212 { 213 char *interval = env_get(PLATFORM_CYCLE_ENV_VAR); 214 /* 215 * interval is the number of platform cycles(MHz) between 216 * wake up events generated by EPU. 217 */ 218 ulong interval_mhz = get_bus_freq(0) / (1000 * 1000); 219 220 if (interval) 221 interval_mhz = simple_strtoul(interval, NULL, 10); 222 223 return interval_mhz; 224 } 225 226 void erratum_a009635(void) 227 { 228 u32 val; 229 unsigned long interval_mhz = get_internval_val_mhz(); 230 231 if (!interval_mhz) 232 return; 233 234 val = in_le32(DCSR_CGACRE5); 235 writel(val | 0x00000200, DCSR_CGACRE5); 236 237 val = in_le32(EPU_EPCMPR5); 238 writel(interval_mhz, EPU_EPCMPR5); 239 val = in_le32(EPU_EPCCR5); 240 writel(val | 0x82820000, EPU_EPCCR5); 241 val = in_le32(EPU_EPSMCR5); 242 writel(val | 0x002f0000, EPU_EPSMCR5); 243 val = in_le32(EPU_EPECR5); 244 writel(val | 0x20000000, EPU_EPECR5); 245 val = in_le32(EPU_EPGCR); 246 writel(val | 0x80000000, EPU_EPGCR); 247 } 248 #endif /* CONFIG_SYS_FSL_ERRATUM_A009635 */ 249 250 static void erratum_rcw_src(void) 251 { 252 #if defined(CONFIG_SPL) && defined(CONFIG_NAND_BOOT) 253 u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE; 254 u32 __iomem *dcfg_dcsr = (u32 __iomem *)DCFG_DCSR_BASE; 255 u32 val; 256 257 val = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4); 258 val &= ~DCFG_PORSR1_RCW_SRC; 259 val |= DCFG_PORSR1_RCW_SRC_NOR; 260 out_le32(dcfg_dcsr + DCFG_DCSR_PORCR1 / 4, val); 261 #endif 262 } 263 264 #define I2C_DEBUG_REG 0x6 265 #define I2C_GLITCH_EN 0x8 266 /* 267 * This erratum requires setting glitch_en bit to enable 268 * digital glitch filter to improve clock stability. 269 */ 270 #ifdef CONFIG_SYS_FSL_ERRATUM_A009203 271 static void erratum_a009203(void) 272 { 273 #ifdef CONFIG_SYS_I2C 274 u8 __iomem *ptr; 275 #ifdef I2C1_BASE_ADDR 276 ptr = (u8 __iomem *)(I2C1_BASE_ADDR + I2C_DEBUG_REG); 277 278 writeb(I2C_GLITCH_EN, ptr); 279 #endif 280 #ifdef I2C2_BASE_ADDR 281 ptr = (u8 __iomem *)(I2C2_BASE_ADDR + I2C_DEBUG_REG); 282 283 writeb(I2C_GLITCH_EN, ptr); 284 #endif 285 #ifdef I2C3_BASE_ADDR 286 ptr = (u8 __iomem *)(I2C3_BASE_ADDR + I2C_DEBUG_REG); 287 288 writeb(I2C_GLITCH_EN, ptr); 289 #endif 290 #ifdef I2C4_BASE_ADDR 291 ptr = (u8 __iomem *)(I2C4_BASE_ADDR + I2C_DEBUG_REG); 292 293 writeb(I2C_GLITCH_EN, ptr); 294 #endif 295 #endif 296 } 297 #endif 298 299 void bypass_smmu(void) 300 { 301 u32 val; 302 val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); 303 out_le32(SMMU_SCR0, val); 304 val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); 305 out_le32(SMMU_NSCR0, val); 306 } 307 void fsl_lsch3_early_init_f(void) 308 { 309 erratum_rcw_src(); 310 #ifdef CONFIG_FSL_IFC 311 init_early_memctl_regs(); /* tighten IFC timing */ 312 #endif 313 #ifdef CONFIG_SYS_FSL_ERRATUM_A009203 314 erratum_a009203(); 315 #endif 316 erratum_a008514(); 317 erratum_a008336(); 318 erratum_a009008(); 319 erratum_a009798(); 320 erratum_a008997(); 321 erratum_a009007(); 322 #ifdef CONFIG_CHAIN_OF_TRUST 323 /* In case of Secure Boot, the IBR configures the SMMU 324 * to allow only Secure transactions. 325 * SMMU must be reset in bypass mode. 326 * Set the ClientPD bit and Clear the USFCFG Bit 327 */ 328 if (fsl_check_boot_mode_secure() == 1) 329 bypass_smmu(); 330 #endif 331 } 332 333 #ifdef CONFIG_SCSI_AHCI_PLAT 334 int sata_init(void) 335 { 336 struct ccsr_ahci __iomem *ccsr_ahci; 337 338 #ifdef CONFIG_SYS_SATA2 339 ccsr_ahci = (void *)CONFIG_SYS_SATA2; 340 out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); 341 out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY2_CFG); 342 out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY3_CFG); 343 out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); 344 out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG); 345 #endif 346 347 #ifdef CONFIG_SYS_SATA1 348 ccsr_ahci = (void *)CONFIG_SYS_SATA1; 349 out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); 350 out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY2_CFG); 351 out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY3_CFG); 352 out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); 353 out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG); 354 355 ahci_init((void __iomem *)CONFIG_SYS_SATA1); 356 scsi_scan(false); 357 #endif 358 359 return 0; 360 } 361 #endif 362 363 /* Get VDD in the unit mV from voltage ID */ 364 int get_core_volt_from_fuse(void) 365 { 366 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 367 int vdd; 368 u32 fusesr; 369 u8 vid; 370 371 /* get the voltage ID from fuse status register */ 372 fusesr = in_le32(&gur->dcfg_fusesr); 373 debug("%s: fusesr = 0x%x\n", __func__, fusesr); 374 vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT) & 375 FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK; 376 if ((vid == 0) || (vid == FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK)) { 377 vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT) & 378 FSL_CHASSIS3_DCFG_FUSESR_VID_MASK; 379 } 380 debug("%s: VID = 0x%x\n", __func__, vid); 381 switch (vid) { 382 case 0x00: /* VID isn't supported */ 383 vdd = -EINVAL; 384 debug("%s: The VID feature is not supported\n", __func__); 385 break; 386 case 0x08: /* 0.9V silicon */ 387 vdd = 900; 388 break; 389 case 0x10: /* 1.0V silicon */ 390 vdd = 1000; 391 break; 392 default: /* Other core voltage */ 393 vdd = -EINVAL; 394 debug("%s: The VID(%x) isn't supported\n", __func__, vid); 395 break; 396 } 397 debug("%s: The required minimum volt of CORE is %dmV\n", __func__, vdd); 398 399 return vdd; 400 } 401 402 #elif defined(CONFIG_FSL_LSCH2) 403 #ifdef CONFIG_SCSI_AHCI_PLAT 404 int sata_init(void) 405 { 406 struct ccsr_ahci __iomem *ccsr_ahci = (void *)CONFIG_SYS_SATA; 407 408 /* Disable SATA ECC */ 409 out_le32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + 0x520, 0x80000000); 410 out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); 411 out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY2_CFG); 412 out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY3_CFG); 413 out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); 414 out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG); 415 416 ahci_init((void __iomem *)CONFIG_SYS_SATA); 417 scsi_scan(false); 418 419 return 0; 420 } 421 #endif 422 423 static void erratum_a009929(void) 424 { 425 #ifdef CONFIG_SYS_FSL_ERRATUM_A009929 426 struct ccsr_gur *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; 427 u32 __iomem *dcsr_cop_ccp = (void *)CONFIG_SYS_DCSR_COP_CCP_ADDR; 428 u32 rstrqmr1 = gur_in32(&gur->rstrqmr1); 429 430 rstrqmr1 |= 0x00000400; 431 gur_out32(&gur->rstrqmr1, rstrqmr1); 432 writel(0x01000000, dcsr_cop_ccp); 433 #endif 434 } 435 436 /* 437 * This erratum requires setting a value to eddrtqcr1 to optimal 438 * the DDR performance. The eddrtqcr1 register is in SCFG space 439 * of LS1043A and the offset is 0x157_020c. 440 */ 441 #if defined(CONFIG_SYS_FSL_ERRATUM_A009660) \ 442 && defined(CONFIG_SYS_FSL_ERRATUM_A008514) 443 #error A009660 and A008514 can not be both enabled. 444 #endif 445 446 static void erratum_a009660(void) 447 { 448 #ifdef CONFIG_SYS_FSL_ERRATUM_A009660 449 u32 *eddrtqcr1 = (void *)CONFIG_SYS_FSL_SCFG_ADDR + 0x20c; 450 out_be32(eddrtqcr1, 0x63b20042); 451 #endif 452 } 453 454 static void erratum_a008850_early(void) 455 { 456 #ifdef CONFIG_SYS_FSL_ERRATUM_A008850 457 /* part 1 of 2 */ 458 struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR + 459 CONFIG_SYS_CCI400_OFFSET); 460 struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; 461 462 /* Skip if running at lower exception level */ 463 if (current_el() < 3) 464 return; 465 466 /* disables propagation of barrier transactions to DDRC from CCI400 */ 467 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER); 468 469 /* disable the re-ordering in DDRC */ 470 ddr_out32(&ddr->eor, DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS); 471 #endif 472 } 473 474 void erratum_a008850_post(void) 475 { 476 #ifdef CONFIG_SYS_FSL_ERRATUM_A008850 477 /* part 2 of 2 */ 478 struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR + 479 CONFIG_SYS_CCI400_OFFSET); 480 struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; 481 u32 tmp; 482 483 /* Skip if running at lower exception level */ 484 if (current_el() < 3) 485 return; 486 487 /* enable propagation of barrier transactions to DDRC from CCI400 */ 488 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); 489 490 /* enable the re-ordering in DDRC */ 491 tmp = ddr_in32(&ddr->eor); 492 tmp &= ~(DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS); 493 ddr_out32(&ddr->eor, tmp); 494 #endif 495 } 496 497 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315 498 void erratum_a010315(void) 499 { 500 int i; 501 502 for (i = PCIE1; i <= PCIE4; i++) 503 if (!is_serdes_configured(i)) { 504 debug("PCIe%d: disabled all R/W permission!\n", i); 505 set_pcie_ns_access(i, 0); 506 } 507 } 508 #endif 509 510 static void erratum_a010539(void) 511 { 512 #if defined(CONFIG_SYS_FSL_ERRATUM_A010539) && defined(CONFIG_QSPI_BOOT) 513 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 514 u32 porsr1; 515 516 porsr1 = in_be32(&gur->porsr1); 517 porsr1 &= ~FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK; 518 out_be32((void *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1), 519 porsr1); 520 out_be32((void *)(CONFIG_SYS_FSL_SCFG_ADDR + 0x1a8), 0xffffffff); 521 #endif 522 } 523 524 /* Get VDD in the unit mV from voltage ID */ 525 int get_core_volt_from_fuse(void) 526 { 527 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 528 int vdd; 529 u32 fusesr; 530 u8 vid; 531 532 fusesr = in_be32(&gur->dcfg_fusesr); 533 debug("%s: fusesr = 0x%x\n", __func__, fusesr); 534 vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT) & 535 FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK; 536 if ((vid == 0) || (vid == FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK)) { 537 vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT) & 538 FSL_CHASSIS2_DCFG_FUSESR_VID_MASK; 539 } 540 debug("%s: VID = 0x%x\n", __func__, vid); 541 switch (vid) { 542 case 0x00: /* VID isn't supported */ 543 vdd = -EINVAL; 544 debug("%s: The VID feature is not supported\n", __func__); 545 break; 546 case 0x08: /* 0.9V silicon */ 547 vdd = 900; 548 break; 549 case 0x10: /* 1.0V silicon */ 550 vdd = 1000; 551 break; 552 default: /* Other core voltage */ 553 vdd = -EINVAL; 554 printf("%s: The VID(%x) isn't supported\n", __func__, vid); 555 break; 556 } 557 debug("%s: The required minimum volt of CORE is %dmV\n", __func__, vdd); 558 559 return vdd; 560 } 561 562 __weak int board_switch_core_volt(u32 vdd) 563 { 564 return 0; 565 } 566 567 static int setup_core_volt(u32 vdd) 568 { 569 return board_setup_core_volt(vdd); 570 } 571 572 #ifdef CONFIG_SYS_FSL_DDR 573 static void ddr_enable_0v9_volt(bool en) 574 { 575 struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; 576 u32 tmp; 577 578 tmp = ddr_in32(&ddr->ddr_cdr1); 579 580 if (en) 581 tmp |= DDR_CDR1_V0PT9_EN; 582 else 583 tmp &= ~DDR_CDR1_V0PT9_EN; 584 585 ddr_out32(&ddr->ddr_cdr1, tmp); 586 } 587 #endif 588 589 int setup_chip_volt(void) 590 { 591 int vdd; 592 593 vdd = get_core_volt_from_fuse(); 594 /* Nothing to do for silicons doesn't support VID */ 595 if (vdd < 0) 596 return vdd; 597 598 if (setup_core_volt(vdd)) 599 printf("%s: Switch core VDD to %dmV failed\n", __func__, vdd); 600 #ifdef CONFIG_SYS_HAS_SERDES 601 if (setup_serdes_volt(vdd)) 602 printf("%s: Switch SVDD to %dmV failed\n", __func__, vdd); 603 #endif 604 605 #ifdef CONFIG_SYS_FSL_DDR 606 if (vdd == 900) 607 ddr_enable_0v9_volt(true); 608 #endif 609 610 return 0; 611 } 612 613 #ifdef CONFIG_FSL_PFE 614 void init_pfe_scfg_dcfg_regs(void) 615 { 616 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; 617 u32 ecccr2; 618 619 out_be32(&scfg->pfeasbcr, 620 in_be32(&scfg->pfeasbcr) | SCFG_PFEASBCR_AWCACHE0); 621 out_be32(&scfg->pfebsbcr, 622 in_be32(&scfg->pfebsbcr) | SCFG_PFEASBCR_AWCACHE0); 623 624 /* CCI-400 QoS settings for PFE */ 625 out_be32(&scfg->wr_qos1, (unsigned int)(SCFG_WR_QOS1_PFE1_QOS 626 | SCFG_WR_QOS1_PFE2_QOS)); 627 out_be32(&scfg->rd_qos1, (unsigned int)(SCFG_RD_QOS1_PFE1_QOS 628 | SCFG_RD_QOS1_PFE2_QOS)); 629 630 ecccr2 = in_be32(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2); 631 out_be32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2, 632 ecccr2 | (unsigned int)DISABLE_PFE_ECC); 633 } 634 #endif 635 636 void fsl_lsch2_early_init_f(void) 637 { 638 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR + 639 CONFIG_SYS_CCI400_OFFSET); 640 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; 641 642 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS 643 enable_layerscape_ns_access(); 644 #endif 645 646 #ifdef CONFIG_FSL_IFC 647 init_early_memctl_regs(); /* tighten IFC timing */ 648 #endif 649 650 #if defined(CONFIG_FSL_QSPI) && !defined(CONFIG_QSPI_BOOT) 651 out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL); 652 #endif 653 /* Make SEC reads and writes snoopable */ 654 setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP | 655 SCFG_SNPCNFGCR_SECWRSNP | 656 SCFG_SNPCNFGCR_SATARDSNP | 657 SCFG_SNPCNFGCR_SATAWRSNP); 658 659 /* 660 * Enable snoop requests and DVM message requests for 661 * Slave insterface S4 (A53 core cluster) 662 */ 663 if (current_el() == 3) { 664 out_le32(&cci->slave[4].snoop_ctrl, 665 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); 666 } 667 668 /* Erratum */ 669 erratum_a008850_early(); /* part 1 of 2 */ 670 erratum_a009929(); 671 erratum_a009660(); 672 erratum_a010539(); 673 erratum_a009008(); 674 erratum_a009798(); 675 erratum_a008997(); 676 erratum_a009007(); 677 } 678 #endif 679 680 #ifdef CONFIG_QSPI_AHB_INIT 681 /* Enable 4bytes address support and fast read */ 682 int qspi_ahb_init(void) 683 { 684 u32 *qspi_lut, lut_key, *qspi_key; 685 686 qspi_key = (void *)SYS_FSL_QSPI_ADDR + 0x300; 687 qspi_lut = (void *)SYS_FSL_QSPI_ADDR + 0x310; 688 689 lut_key = in_be32(qspi_key); 690 691 if (lut_key == 0x5af05af0) { 692 /* That means the register is BE */ 693 out_be32(qspi_key, 0x5af05af0); 694 /* Unlock the lut table */ 695 out_be32(qspi_key + 1, 0x00000002); 696 out_be32(qspi_lut, 0x0820040c); 697 out_be32(qspi_lut + 1, 0x1c080c08); 698 out_be32(qspi_lut + 2, 0x00002400); 699 /* Lock the lut table */ 700 out_be32(qspi_key, 0x5af05af0); 701 out_be32(qspi_key + 1, 0x00000001); 702 } else { 703 /* That means the register is LE */ 704 out_le32(qspi_key, 0x5af05af0); 705 /* Unlock the lut table */ 706 out_le32(qspi_key + 1, 0x00000002); 707 out_le32(qspi_lut, 0x0820040c); 708 out_le32(qspi_lut + 1, 0x1c080c08); 709 out_le32(qspi_lut + 2, 0x00002400); 710 /* Lock the lut table */ 711 out_le32(qspi_key, 0x5af05af0); 712 out_le32(qspi_key + 1, 0x00000001); 713 } 714 715 return 0; 716 } 717 #endif 718 719 #ifdef CONFIG_BOARD_LATE_INIT 720 int board_late_init(void) 721 { 722 #ifdef CONFIG_SCSI_AHCI_PLAT 723 sata_init(); 724 #endif 725 #ifdef CONFIG_CHAIN_OF_TRUST 726 fsl_setenv_chain_of_trust(); 727 #endif 728 #ifdef CONFIG_QSPI_AHB_INIT 729 qspi_ahb_init(); 730 #endif 731 732 return 0; 733 } 734 #endif 735
