1 /* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining 5 * a copy of this software and associated documentation files (the 6 * "Software"), to deal in the Software without restriction, including 7 * without limitation the rights to use, copy, modify, merge, publish, 8 * distribute, sub license, and/or sell copies of the Software, and to 9 * permit persons to whom the Software is furnished to do so, subject to 10 * the following conditions: 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 13 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 14 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 15 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS 16 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 17 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 */ 25 26 #ifndef AC_SURFACE_H 27 #define AC_SURFACE_H 28 29 #include <stdint.h> 30 31 #include "amd_family.h" 32 33 #ifdef __cplusplus 34 extern "C" { 35 #endif 36 37 /* Forward declarations. */ 38 typedef void* ADDR_HANDLE; 39 40 struct amdgpu_gpu_info; 41 struct radeon_info; 42 43 #define RADEON_SURF_MAX_LEVELS 15 44 45 enum radeon_surf_mode { 46 RADEON_SURF_MODE_LINEAR_ALIGNED = 1, 47 RADEON_SURF_MODE_1D = 2, 48 RADEON_SURF_MODE_2D = 3, 49 }; 50 51 /* These are defined exactly like GB_TILE_MODEn.MICRO_TILE_MODE_NEW. */ 52 enum radeon_micro_mode { 53 RADEON_MICRO_MODE_DISPLAY = 0, 54 RADEON_MICRO_MODE_THIN = 1, 55 RADEON_MICRO_MODE_DEPTH = 2, 56 RADEON_MICRO_MODE_ROTATED = 3, 57 }; 58 59 /* the first 16 bits are reserved for libdrm_radeon, don't use them */ 60 #define RADEON_SURF_SCANOUT (1 << 16) 61 #define RADEON_SURF_ZBUFFER (1 << 17) 62 #define RADEON_SURF_SBUFFER (1 << 18) 63 #define RADEON_SURF_Z_OR_SBUFFER (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER) 64 /* bits 19 and 20 are reserved for libdrm_radeon, don't use them */ 65 #define RADEON_SURF_FMASK (1 << 21) 66 #define RADEON_SURF_DISABLE_DCC (1 << 22) 67 #define RADEON_SURF_TC_COMPATIBLE_HTILE (1 << 23) 68 #define RADEON_SURF_IMPORTED (1 << 24) 69 #define RADEON_SURF_OPTIMIZE_FOR_SPACE (1 << 25) 70 #define RADEON_SURF_SHAREABLE (1 << 26) 71 72 struct legacy_surf_level { 73 uint64_t offset; 74 uint32_t slice_size_dw; /* in dwords; max = 4GB / 4. */ 75 uint32_t dcc_offset; /* relative offset within DCC mip tree */ 76 uint32_t dcc_fast_clear_size; 77 unsigned nblk_x:15; 78 unsigned nblk_y:15; 79 enum radeon_surf_mode mode:2; 80 }; 81 82 struct legacy_surf_layout { 83 unsigned bankw:4; /* max 8 */ 84 unsigned bankh:4; /* max 8 */ 85 unsigned mtilea:4; /* max 8 */ 86 unsigned tile_split:13; /* max 4K */ 87 unsigned stencil_tile_split:13; /* max 4K */ 88 unsigned pipe_config:5; /* max 17 */ 89 unsigned num_banks:5; /* max 16 */ 90 unsigned macro_tile_index:4; /* max 15 */ 91 92 /* Whether the depth miptree or stencil miptree as used by the DB are 93 * adjusted from their TC compatible form to ensure depth/stencil 94 * compatibility. If either is true, the corresponding plane cannot be 95 * sampled from. 96 */ 97 unsigned depth_adjusted:1; 98 unsigned stencil_adjusted:1; 99 100 struct legacy_surf_level level[RADEON_SURF_MAX_LEVELS]; 101 struct legacy_surf_level stencil_level[RADEON_SURF_MAX_LEVELS]; 102 uint8_t tiling_index[RADEON_SURF_MAX_LEVELS]; 103 uint8_t stencil_tiling_index[RADEON_SURF_MAX_LEVELS]; 104 }; 105 106 /* Same as addrlib - AddrResourceType. */ 107 enum gfx9_resource_type { 108 RADEON_RESOURCE_1D = 0, 109 RADEON_RESOURCE_2D, 110 RADEON_RESOURCE_3D, 111 }; 112 113 struct gfx9_surf_flags { 114 uint16_t swizzle_mode; /* tile mode */ 115 uint16_t epitch; /* (pitch - 1) or (height - 1) */ 116 }; 117 118 struct gfx9_surf_meta_flags { 119 unsigned rb_aligned:1; /* optimal for RBs */ 120 unsigned pipe_aligned:1; /* optimal for TC */ 121 }; 122 123 struct gfx9_surf_layout { 124 struct gfx9_surf_flags surf; /* color or depth surface */ 125 struct gfx9_surf_flags fmask; /* not added to surf_size */ 126 struct gfx9_surf_flags stencil; /* added to surf_size, use stencil_offset */ 127 128 struct gfx9_surf_meta_flags dcc; /* metadata of color */ 129 struct gfx9_surf_meta_flags htile; /* metadata of depth and stencil */ 130 struct gfx9_surf_meta_flags cmask; /* metadata of fmask */ 131 132 enum gfx9_resource_type resource_type; /* 1D, 2D or 3D */ 133 uint16_t surf_pitch; /* in blocks */ 134 uint16_t surf_height; 135 136 uint64_t surf_offset; /* 0 unless imported with an offset */ 137 /* The size of the 2D plane containing all mipmap levels. */ 138 uint64_t surf_slice_size; 139 /* Mipmap level offset within the slice in bytes. Only valid for LINEAR. */ 140 uint32_t offset[RADEON_SURF_MAX_LEVELS]; 141 142 uint16_t dcc_pitch_max; /* (mip chain pitch - 1) */ 143 144 uint64_t stencil_offset; /* separate stencil */ 145 uint64_t fmask_size; 146 uint64_t cmask_size; 147 148 uint32_t fmask_alignment; 149 uint32_t cmask_alignment; 150 }; 151 152 struct radeon_surf { 153 /* Format properties. */ 154 unsigned blk_w:4; 155 unsigned blk_h:4; 156 unsigned bpe:5; 157 /* Number of mipmap levels where DCC is enabled starting from level 0. 158 * Non-zero levels may be disabled due to alignment constraints, but not 159 * the first level. 160 */ 161 unsigned num_dcc_levels:4; 162 unsigned is_linear:1; 163 unsigned has_stencil:1; 164 /* This might be true even if micro_tile_mode isn't displayable or rotated. */ 165 unsigned is_displayable:1; 166 /* Displayable, thin, depth, rotated. AKA D,S,Z,R swizzle modes. */ 167 unsigned micro_tile_mode:3; 168 uint32_t flags; 169 170 /* These are return values. Some of them can be set by the caller, but 171 * they will be treated as hints (e.g. bankw, bankh) and might be 172 * changed by the calculator. 173 */ 174 175 /* Tile swizzle can be OR'd with low bits of the BASE_256B address. 176 * The value is the same for all mipmap levels. Supported tile modes: 177 * - GFX6: Only macro tiling. 178 * - GFX9: Only *_X swizzle modes. Level 0 must not be in the mip tail. 179 * 180 * Only these surfaces are allowed to set it: 181 * - color (if it doesn't have to be displayable) 182 * - DCC (same tile swizzle as color) 183 * - FMASK 184 * - CMASK if it's TC-compatible or if the gen is GFX9 185 * - depth/stencil if HTILE is not TC-compatible and if the gen is not GFX9 186 */ 187 uint8_t tile_swizzle; 188 189 uint64_t surf_size; 190 /* DCC and HTILE are very small. */ 191 uint32_t dcc_size; 192 uint32_t htile_size; 193 194 uint32_t htile_slice_size; 195 196 uint32_t surf_alignment; 197 uint32_t dcc_alignment; 198 uint32_t htile_alignment; 199 200 union { 201 /* R600-VI return values. 202 * 203 * Some of them can be set by the caller if certain parameters are 204 * desirable. The allocator will try to obey them. 205 */ 206 struct legacy_surf_layout legacy; 207 208 /* GFX9+ return values. */ 209 struct gfx9_surf_layout gfx9; 210 } u; 211 }; 212 213 struct ac_surf_info { 214 uint32_t width; 215 uint32_t height; 216 uint32_t depth; 217 uint8_t samples; 218 uint8_t levels; 219 uint16_t array_size; 220 uint32_t *surf_index; /* Set a monotonic counter for tile swizzling. */ 221 }; 222 223 struct ac_surf_config { 224 struct ac_surf_info info; 225 unsigned is_3d : 1; 226 unsigned is_cube : 1; 227 }; 228 229 ADDR_HANDLE amdgpu_addr_create(const struct radeon_info *info, 230 const struct amdgpu_gpu_info *amdinfo, 231 uint64_t *max_alignment); 232 233 int ac_compute_surface(ADDR_HANDLE addrlib, const struct radeon_info *info, 234 const struct ac_surf_config * config, 235 enum radeon_surf_mode mode, 236 struct radeon_surf *surf); 237 238 #ifdef __cplusplus 239 } 240 #endif 241 242 #endif /* AC_SURFACE_H */ 243
