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      1 // Copyright 2013 the V8 project authors. All rights reserved.
      2 // Use of this source code is governed by a BSD-style license that can be
      3 // found in the LICENSE file.
      4 
      5 #ifndef V8_ARM64_CONSTANTS_ARM64_H_
      6 #define V8_ARM64_CONSTANTS_ARM64_H_
      7 
      8 #include "src/base/macros.h"
      9 #include "src/globals.h"
     10 
     11 // Assert that this is an LP64 system.
     12 STATIC_ASSERT(sizeof(int) == sizeof(int32_t));
     13 STATIC_ASSERT(sizeof(long) == sizeof(int64_t));    // NOLINT(runtime/int)
     14 STATIC_ASSERT(sizeof(void *) == sizeof(int64_t));
     15 STATIC_ASSERT(sizeof(1) == sizeof(int32_t));
     16 STATIC_ASSERT(sizeof(1L) == sizeof(int64_t));
     17 
     18 
     19 // Get the standard printf format macros for C99 stdint types.
     20 #ifndef __STDC_FORMAT_MACROS
     21 #define __STDC_FORMAT_MACROS
     22 #endif
     23 #include <inttypes.h>
     24 
     25 
     26 namespace v8 {
     27 namespace internal {
     28 
     29 constexpr size_t kMaxPCRelativeCodeRangeInMB = 128;
     30 
     31 constexpr uint8_t kInstrSize = 4;
     32 constexpr uint8_t kInstrSizeLog2 = 2;
     33 constexpr size_t kLoadLiteralScaleLog2 = 2;
     34 constexpr size_t kMaxLoadLiteralRange = 1 * MB;
     35 
     36 const int kNumberOfRegisters = 32;
     37 const int kNumberOfVRegisters = 32;
     38 // Callee saved registers are x19-x30(lr).
     39 const int kNumberOfCalleeSavedRegisters = 11;
     40 const int kFirstCalleeSavedRegisterIndex = 19;
     41 // Callee saved FP registers are d8-d15.
     42 const int kNumberOfCalleeSavedVRegisters = 8;
     43 const int kFirstCalleeSavedVRegisterIndex = 8;
     44 // Callee saved registers with no specific purpose in JS are x19-x25.
     45 const size_t kJSCalleeSavedRegList = 0x03f80000;
     46 const int kWRegSizeInBits = 32;
     47 const int kWRegSizeInBitsLog2 = 5;
     48 const int kWRegSize = kWRegSizeInBits >> 3;
     49 const int kWRegSizeLog2 = kWRegSizeInBitsLog2 - 3;
     50 const int kXRegSizeInBits = 64;
     51 const int kXRegSizeInBitsLog2 = 6;
     52 const int kXRegSize = kXRegSizeInBits >> 3;
     53 const int kXRegSizeLog2 = kXRegSizeInBitsLog2 - 3;
     54 const int kSRegSizeInBits = 32;
     55 const int kSRegSizeInBitsLog2 = 5;
     56 const int kSRegSize = kSRegSizeInBits >> 3;
     57 const int kSRegSizeLog2 = kSRegSizeInBitsLog2 - 3;
     58 const int kDRegSizeInBits = 64;
     59 const int kDRegSizeInBitsLog2 = 6;
     60 const int kDRegSize = kDRegSizeInBits >> 3;
     61 const int kDRegSizeLog2 = kDRegSizeInBitsLog2 - 3;
     62 const int kDRegSizeInBytesLog2 = kDRegSizeInBitsLog2 - 3;
     63 const int kBRegSizeInBits = 8;
     64 const int kBRegSize = kBRegSizeInBits >> 3;
     65 const int kHRegSizeInBits = 16;
     66 const int kHRegSize = kHRegSizeInBits >> 3;
     67 const int kQRegSizeInBits = 128;
     68 const int kQRegSizeInBitsLog2 = 7;
     69 const int kQRegSize = kQRegSizeInBits >> 3;
     70 const int kQRegSizeLog2 = kQRegSizeInBitsLog2 - 3;
     71 const int kVRegSizeInBits = kQRegSizeInBits;
     72 const int kVRegSize = kVRegSizeInBits >> 3;
     73 const int64_t kWRegMask = 0x00000000ffffffffL;
     74 const int64_t kXRegMask = 0xffffffffffffffffL;
     75 const int64_t kSRegMask = 0x00000000ffffffffL;
     76 const int64_t kDRegMask = 0xffffffffffffffffL;
     77 // TODO(all) check if the expression below works on all compilers or if it
     78 // triggers an overflow error.
     79 const int64_t kDSignBit = 63;
     80 const int64_t kDSignMask = 0x1L << kDSignBit;
     81 const int64_t kSSignBit = 31;
     82 const int64_t kSSignMask = 0x1L << kSSignBit;
     83 const int64_t kXSignBit = 63;
     84 const int64_t kXSignMask = 0x1L << kXSignBit;
     85 const int64_t kWSignBit = 31;
     86 const int64_t kWSignMask = 0x1L << kWSignBit;
     87 const int64_t kDQuietNanBit = 51;
     88 const int64_t kDQuietNanMask = 0x1L << kDQuietNanBit;
     89 const int64_t kSQuietNanBit = 22;
     90 const int64_t kSQuietNanMask = 0x1L << kSQuietNanBit;
     91 const int64_t kByteMask = 0xffL;
     92 const int64_t kHalfWordMask = 0xffffL;
     93 const int64_t kWordMask = 0xffffffffL;
     94 const uint64_t kXMaxUInt = 0xffffffffffffffffUL;
     95 const uint64_t kWMaxUInt = 0xffffffffUL;
     96 const int64_t kXMaxInt = 0x7fffffffffffffffL;
     97 const int64_t kXMinInt = 0x8000000000000000L;
     98 const int32_t kWMaxInt = 0x7fffffff;
     99 const int32_t kWMinInt = 0x80000000;
    100 const int kIp0Code = 16;
    101 const int kIp1Code = 17;
    102 const int kFramePointerRegCode = 29;
    103 const int kLinkRegCode = 30;
    104 const int kZeroRegCode = 31;
    105 const int kSPRegInternalCode = 63;
    106 const unsigned kRegCodeMask = 0x1f;
    107 const unsigned kShiftAmountWRegMask = 0x1f;
    108 const unsigned kShiftAmountXRegMask = 0x3f;
    109 // Standard machine types defined by AAPCS64.
    110 const unsigned kByteSize = 8;
    111 const unsigned kByteSizeInBytes = kByteSize >> 3;
    112 const unsigned kHalfWordSize = 16;
    113 const unsigned kHalfWordSizeLog2 = 4;
    114 const unsigned kHalfWordSizeInBytes = kHalfWordSize >> 3;
    115 const unsigned kHalfWordSizeInBytesLog2 = kHalfWordSizeLog2 - 3;
    116 const unsigned kWordSize = 32;
    117 const unsigned kWordSizeLog2 = 5;
    118 const unsigned kWordSizeInBytes = kWordSize >> 3;
    119 const unsigned kWordSizeInBytesLog2 = kWordSizeLog2 - 3;
    120 const unsigned kDoubleWordSize = 64;
    121 const unsigned kDoubleWordSizeInBytes = kDoubleWordSize >> 3;
    122 const unsigned kQuadWordSize = 128;
    123 const unsigned kQuadWordSizeInBytes = kQuadWordSize >> 3;
    124 const int kMaxLanesPerVector = 16;
    125 
    126 const unsigned kAddressTagOffset = 56;
    127 const unsigned kAddressTagWidth = 8;
    128 const uint64_t kAddressTagMask = ((UINT64_C(1) << kAddressTagWidth) - 1)
    129                                  << kAddressTagOffset;
    130 static_assert(kAddressTagMask == UINT64_C(0xff00000000000000),
    131               "AddressTagMask must represent most-significant eight bits.");
    132 
    133 // AArch64 floating-point specifics. These match IEEE-754.
    134 const unsigned kDoubleMantissaBits = 52;
    135 const unsigned kDoubleExponentBits = 11;
    136 const unsigned kDoubleExponentBias = 1023;
    137 const unsigned kFloatMantissaBits = 23;
    138 const unsigned kFloatExponentBits = 8;
    139 const unsigned kFloatExponentBias = 127;
    140 const unsigned kFloat16MantissaBits = 10;
    141 const unsigned kFloat16ExponentBits = 5;
    142 const unsigned kFloat16ExponentBias = 15;
    143 
    144 // Actual value of root register is offset from the root array's start
    145 // to take advantage of negative displacement values.
    146 // TODO(sigurds): Choose best value.
    147 constexpr int kRootRegisterBias = 256;
    148 
    149 typedef uint16_t float16;
    150 
    151 #define INSTRUCTION_FIELDS_LIST(V_)                     \
    152   /* Register fields */                                 \
    153   V_(Rd, 4, 0, Bits)    /* Destination register.     */ \
    154   V_(Rn, 9, 5, Bits)    /* First source register.    */ \
    155   V_(Rm, 20, 16, Bits)  /* Second source register.   */ \
    156   V_(Ra, 14, 10, Bits)  /* Third source register.    */ \
    157   V_(Rt, 4, 0, Bits)    /* Load dest / store source. */ \
    158   V_(Rt2, 14, 10, Bits) /* Load second dest /        */ \
    159                         /* store second source.      */ \
    160   V_(Rs, 20, 16, Bits)  /* Store-exclusive status    */ \
    161   V_(PrefetchMode, 4, 0, Bits)                          \
    162                                                         \
    163   /* Common bits */                                     \
    164   V_(SixtyFourBits, 31, 31, Bits)                       \
    165   V_(FlagsUpdate, 29, 29, Bits)                         \
    166                                                         \
    167   /* PC relative addressing */                          \
    168   V_(ImmPCRelHi, 23, 5, SignedBits)                     \
    169   V_(ImmPCRelLo, 30, 29, Bits)                          \
    170                                                         \
    171   /* Add/subtract/logical shift register */             \
    172   V_(ShiftDP, 23, 22, Bits)                             \
    173   V_(ImmDPShift, 15, 10, Bits)                          \
    174                                                         \
    175   /* Add/subtract immediate */                          \
    176   V_(ImmAddSub, 21, 10, Bits)                           \
    177   V_(ShiftAddSub, 23, 22, Bits)                         \
    178                                                         \
    179   /* Add/subtract extend */                             \
    180   V_(ImmExtendShift, 12, 10, Bits)                      \
    181   V_(ExtendMode, 15, 13, Bits)                          \
    182                                                         \
    183   /* Move wide */                                       \
    184   V_(ImmMoveWide, 20, 5, Bits)                          \
    185   V_(ShiftMoveWide, 22, 21, Bits)                       \
    186                                                         \
    187   /* Logical immediate, bitfield and extract */         \
    188   V_(BitN, 22, 22, Bits)                                \
    189   V_(ImmRotate, 21, 16, Bits)                           \
    190   V_(ImmSetBits, 15, 10, Bits)                          \
    191   V_(ImmR, 21, 16, Bits)                                \
    192   V_(ImmS, 15, 10, Bits)                                \
    193                                                         \
    194   /* Test and branch immediate */                       \
    195   V_(ImmTestBranch, 18, 5, SignedBits)                  \
    196   V_(ImmTestBranchBit40, 23, 19, Bits)                  \
    197   V_(ImmTestBranchBit5, 31, 31, Bits)                   \
    198                                                         \
    199   /* Conditionals */                                    \
    200   V_(Condition, 15, 12, Bits)                           \
    201   V_(ConditionBranch, 3, 0, Bits)                       \
    202   V_(Nzcv, 3, 0, Bits)                                  \
    203   V_(ImmCondCmp, 20, 16, Bits)                          \
    204   V_(ImmCondBranch, 23, 5, SignedBits)                  \
    205                                                         \
    206   /* Floating point */                                  \
    207   V_(FPType, 23, 22, Bits)                              \
    208   V_(ImmFP, 20, 13, Bits)                               \
    209   V_(FPScale, 15, 10, Bits)                             \
    210                                                         \
    211   /* Load Store */                                      \
    212   V_(ImmLS, 20, 12, SignedBits)                         \
    213   V_(ImmLSUnsigned, 21, 10, Bits)                       \
    214   V_(ImmLSPair, 21, 15, SignedBits)                     \
    215   V_(ImmShiftLS, 12, 12, Bits)                          \
    216   V_(LSOpc, 23, 22, Bits)                               \
    217   V_(LSVector, 26, 26, Bits)                            \
    218   V_(LSSize, 31, 30, Bits)                              \
    219                                                         \
    220   /* NEON generic fields */                             \
    221   V_(NEONQ, 30, 30, Bits)                               \
    222   V_(NEONSize, 23, 22, Bits)                            \
    223   V_(NEONLSSize, 11, 10, Bits)                          \
    224   V_(NEONS, 12, 12, Bits)                               \
    225   V_(NEONL, 21, 21, Bits)                               \
    226   V_(NEONM, 20, 20, Bits)                               \
    227   V_(NEONH, 11, 11, Bits)                               \
    228   V_(ImmNEONExt, 14, 11, Bits)                          \
    229   V_(ImmNEON5, 20, 16, Bits)                            \
    230   V_(ImmNEON4, 14, 11, Bits)                            \
    231                                                         \
    232   /* Other immediates */                                \
    233   V_(ImmUncondBranch, 25, 0, SignedBits)                \
    234   V_(ImmCmpBranch, 23, 5, SignedBits)                   \
    235   V_(ImmLLiteral, 23, 5, SignedBits)                    \
    236   V_(ImmException, 20, 5, Bits)                         \
    237   V_(ImmHint, 11, 5, Bits)                              \
    238   V_(ImmBarrierDomain, 11, 10, Bits)                    \
    239   V_(ImmBarrierType, 9, 8, Bits)                        \
    240                                                         \
    241   /* System (MRS, MSR) */                               \
    242   V_(ImmSystemRegister, 19, 5, Bits)                    \
    243   V_(SysO0, 19, 19, Bits)                               \
    244   V_(SysOp1, 18, 16, Bits)                              \
    245   V_(SysOp2, 7, 5, Bits)                                \
    246   V_(CRn, 15, 12, Bits)                                 \
    247   V_(CRm, 11, 8, Bits)                                  \
    248                                                         \
    249   /* Load-/store-exclusive */                           \
    250   V_(LoadStoreXLoad, 22, 22, Bits)                      \
    251   V_(LoadStoreXNotExclusive, 23, 23, Bits)              \
    252   V_(LoadStoreXAcquireRelease, 15, 15, Bits)            \
    253   V_(LoadStoreXSizeLog2, 31, 30, Bits)                  \
    254   V_(LoadStoreXPair, 21, 21, Bits)                      \
    255                                                         \
    256   /* NEON load/store */                                 \
    257   V_(NEONLoad, 22, 22, Bits)                            \
    258                                                         \
    259   /* NEON Modified Immediate fields */                  \
    260   V_(ImmNEONabc, 18, 16, Bits)                          \
    261   V_(ImmNEONdefgh, 9, 5, Bits)                          \
    262   V_(NEONModImmOp, 29, 29, Bits)                        \
    263   V_(NEONCmode, 15, 12, Bits)                           \
    264                                                         \
    265   /* NEON Shift Immediate fields */                     \
    266   V_(ImmNEONImmhImmb, 22, 16, Bits)                     \
    267   V_(ImmNEONImmh, 22, 19, Bits)                         \
    268   V_(ImmNEONImmb, 18, 16, Bits)
    269 
    270 #define SYSTEM_REGISTER_FIELDS_LIST(V_, M_)                                    \
    271 /* NZCV */                                                                     \
    272 V_(Flags, 31, 28, Bits, uint32_t)                                              \
    273 V_(N,     31, 31, Bits, bool)                                                  \
    274 V_(Z,     30, 30, Bits, bool)                                                  \
    275 V_(C,     29, 29, Bits, bool)                                                  \
    276 V_(V,     28, 28, Bits, uint32_t)                                              \
    277 M_(NZCV, Flags_mask)                                                           \
    278                                                                                \
    279 /* FPCR */                                                                     \
    280 V_(AHP,   26, 26, Bits, bool)                                                  \
    281 V_(DN,    25, 25, Bits, bool)                                                  \
    282 V_(FZ,    24, 24, Bits, bool)                                                  \
    283 V_(RMode, 23, 22, Bits, FPRounding)                                            \
    284 M_(FPCR, AHP_mask | DN_mask | FZ_mask | RMode_mask)
    285 
    286 
    287 // Fields offsets.
    288 #define DECLARE_FIELDS_OFFSETS(Name, HighBit, LowBit, unused_1, unused_2)      \
    289   const int Name##_offset = LowBit;                                            \
    290   const int Name##_width = HighBit - LowBit + 1;                               \
    291   const uint32_t Name##_mask = ((1 << Name##_width) - 1) << LowBit;
    292 #define DECLARE_INSTRUCTION_FIELDS_OFFSETS(Name, HighBit, LowBit, unused_1)    \
    293   DECLARE_FIELDS_OFFSETS(Name, HighBit, LowBit, unused_1, unused_2)
    294 #define NOTHING(A, B)
    295 INSTRUCTION_FIELDS_LIST(DECLARE_INSTRUCTION_FIELDS_OFFSETS)
    296 SYSTEM_REGISTER_FIELDS_LIST(DECLARE_FIELDS_OFFSETS, NOTHING)
    297 #undef NOTHING
    298 #undef DECLARE_FIELDS_OFFSETS
    299 #undef DECLARE_INSTRUCTION_FIELDS_OFFSETS
    300 
    301 // ImmPCRel is a compound field (not present in INSTRUCTION_FIELDS_LIST), formed
    302 // from ImmPCRelLo and ImmPCRelHi.
    303 const int ImmPCRel_mask = ImmPCRelLo_mask | ImmPCRelHi_mask;
    304 
    305 // Condition codes.
    306 enum Condition {
    307   eq = 0,
    308   ne = 1,
    309   hs = 2, cs = hs,
    310   lo = 3, cc = lo,
    311   mi = 4,
    312   pl = 5,
    313   vs = 6,
    314   vc = 7,
    315   hi = 8,
    316   ls = 9,
    317   ge = 10,
    318   lt = 11,
    319   gt = 12,
    320   le = 13,
    321   al = 14,
    322   nv = 15  // Behaves as always/al.
    323 };
    324 
    325 inline Condition NegateCondition(Condition cond) {
    326   // Conditions al and nv behave identically, as "always true". They can't be
    327   // inverted, because there is no never condition.
    328   DCHECK((cond != al) && (cond != nv));
    329   return static_cast<Condition>(cond ^ 1);
    330 }
    331 
    332 enum FlagsUpdate {
    333   SetFlags   = 1,
    334   LeaveFlags = 0
    335 };
    336 
    337 enum StatusFlags {
    338   NoFlag    = 0,
    339 
    340   // Derive the flag combinations from the system register bit descriptions.
    341   NFlag     = N_mask,
    342   ZFlag     = Z_mask,
    343   CFlag     = C_mask,
    344   VFlag     = V_mask,
    345   NZFlag    = NFlag | ZFlag,
    346   NCFlag    = NFlag | CFlag,
    347   NVFlag    = NFlag | VFlag,
    348   ZCFlag    = ZFlag | CFlag,
    349   ZVFlag    = ZFlag | VFlag,
    350   CVFlag    = CFlag | VFlag,
    351   NZCFlag   = NFlag | ZFlag | CFlag,
    352   NZVFlag   = NFlag | ZFlag | VFlag,
    353   NCVFlag   = NFlag | CFlag | VFlag,
    354   ZCVFlag   = ZFlag | CFlag | VFlag,
    355   NZCVFlag  = NFlag | ZFlag | CFlag | VFlag,
    356 
    357   // Floating-point comparison results.
    358   FPEqualFlag       = ZCFlag,
    359   FPLessThanFlag    = NFlag,
    360   FPGreaterThanFlag = CFlag,
    361   FPUnorderedFlag   = CVFlag
    362 };
    363 
    364 enum Shift {
    365   NO_SHIFT = -1,
    366   LSL = 0x0,
    367   LSR = 0x1,
    368   ASR = 0x2,
    369   ROR = 0x3,
    370   MSL = 0x4
    371 };
    372 
    373 enum Extend {
    374   NO_EXTEND = -1,
    375   UXTB      = 0,
    376   UXTH      = 1,
    377   UXTW      = 2,
    378   UXTX      = 3,
    379   SXTB      = 4,
    380   SXTH      = 5,
    381   SXTW      = 6,
    382   SXTX      = 7
    383 };
    384 
    385 enum SystemHint {
    386   NOP = 0,
    387   YIELD = 1,
    388   WFE = 2,
    389   WFI = 3,
    390   SEV = 4,
    391   SEVL = 5,
    392   CSDB = 20
    393 };
    394 
    395 enum BarrierDomain {
    396   OuterShareable = 0,
    397   NonShareable   = 1,
    398   InnerShareable = 2,
    399   FullSystem     = 3
    400 };
    401 
    402 enum BarrierType {
    403   BarrierOther  = 0,
    404   BarrierReads  = 1,
    405   BarrierWrites = 2,
    406   BarrierAll    = 3
    407 };
    408 
    409 // System/special register names.
    410 // This information is not encoded as one field but as the concatenation of
    411 // multiple fields (Op0<0>, Op1, Crn, Crm, Op2).
    412 enum SystemRegister {
    413   NZCV = ((0x1 << SysO0_offset) |
    414           (0x3 << SysOp1_offset) |
    415           (0x4 << CRn_offset) |
    416           (0x2 << CRm_offset) |
    417           (0x0 << SysOp2_offset)) >> ImmSystemRegister_offset,
    418   FPCR = ((0x1 << SysO0_offset) |
    419           (0x3 << SysOp1_offset) |
    420           (0x4 << CRn_offset) |
    421           (0x4 << CRm_offset) |
    422           (0x0 << SysOp2_offset)) >> ImmSystemRegister_offset
    423 };
    424 
    425 // Instruction enumerations.
    426 //
    427 // These are the masks that define a class of instructions, and the list of
    428 // instructions within each class. Each enumeration has a Fixed, FMask and
    429 // Mask value.
    430 //
    431 // Fixed: The fixed bits in this instruction class.
    432 // FMask: The mask used to extract the fixed bits in the class.
    433 // Mask:  The mask used to identify the instructions within a class.
    434 //
    435 // The enumerations can be used like this:
    436 //
    437 // DCHECK(instr->Mask(PCRelAddressingFMask) == PCRelAddressingFixed);
    438 // switch(instr->Mask(PCRelAddressingMask)) {
    439 //   case ADR:  Format("adr 'Xd, 'AddrPCRelByte"); break;
    440 //   case ADRP: Format("adrp 'Xd, 'AddrPCRelPage"); break;
    441 //   default:   printf("Unknown instruction\n");
    442 // }
    443 
    444 // Used to corrupt encodings by setting all bits when orred. Although currently
    445 // unallocated in AArch64, this encoding is not guaranteed to be undefined
    446 // indefinitely.
    447 const uint32_t kUnallocatedInstruction = 0xffffffff;
    448 
    449 // Generic fields.
    450 enum GenericInstrField {
    451   SixtyFourBits        = 0x80000000,
    452   ThirtyTwoBits        = 0x00000000,
    453   FP32                 = 0x00000000,
    454   FP64                 = 0x00400000
    455 };
    456 
    457 enum NEONFormatField {
    458   NEONFormatFieldMask = 0x40C00000,
    459   NEON_Q = 0x40000000,
    460   NEON_8B = 0x00000000,
    461   NEON_16B = NEON_8B | NEON_Q,
    462   NEON_4H = 0x00400000,
    463   NEON_8H = NEON_4H | NEON_Q,
    464   NEON_2S = 0x00800000,
    465   NEON_4S = NEON_2S | NEON_Q,
    466   NEON_1D = 0x00C00000,
    467   NEON_2D = 0x00C00000 | NEON_Q
    468 };
    469 
    470 enum NEONFPFormatField {
    471   NEONFPFormatFieldMask = 0x40400000,
    472   NEON_FP_2S = FP32,
    473   NEON_FP_4S = FP32 | NEON_Q,
    474   NEON_FP_2D = FP64 | NEON_Q
    475 };
    476 
    477 enum NEONLSFormatField {
    478   NEONLSFormatFieldMask = 0x40000C00,
    479   LS_NEON_8B = 0x00000000,
    480   LS_NEON_16B = LS_NEON_8B | NEON_Q,
    481   LS_NEON_4H = 0x00000400,
    482   LS_NEON_8H = LS_NEON_4H | NEON_Q,
    483   LS_NEON_2S = 0x00000800,
    484   LS_NEON_4S = LS_NEON_2S | NEON_Q,
    485   LS_NEON_1D = 0x00000C00,
    486   LS_NEON_2D = LS_NEON_1D | NEON_Q
    487 };
    488 
    489 enum NEONScalarFormatField {
    490   NEONScalarFormatFieldMask = 0x00C00000,
    491   NEONScalar = 0x10000000,
    492   NEON_B = 0x00000000,
    493   NEON_H = 0x00400000,
    494   NEON_S = 0x00800000,
    495   NEON_D = 0x00C00000
    496 };
    497 
    498 // PC relative addressing.
    499 enum PCRelAddressingOp {
    500   PCRelAddressingFixed = 0x10000000,
    501   PCRelAddressingFMask = 0x1F000000,
    502   PCRelAddressingMask  = 0x9F000000,
    503   ADR                  = PCRelAddressingFixed | 0x00000000,
    504   ADRP                 = PCRelAddressingFixed | 0x80000000
    505 };
    506 
    507 // Add/sub (immediate, shifted and extended.)
    508 const int kSFOffset = 31;
    509 enum AddSubOp {
    510   AddSubOpMask      = 0x60000000,
    511   AddSubSetFlagsBit = 0x20000000,
    512   ADD               = 0x00000000,
    513   ADDS              = ADD | AddSubSetFlagsBit,
    514   SUB               = 0x40000000,
    515   SUBS              = SUB | AddSubSetFlagsBit
    516 };
    517 
    518 #define ADD_SUB_OP_LIST(V)  \
    519   V(ADD),                   \
    520   V(ADDS),                  \
    521   V(SUB),                   \
    522   V(SUBS)
    523 
    524 enum AddSubImmediateOp {
    525   AddSubImmediateFixed = 0x11000000,
    526   AddSubImmediateFMask = 0x1F000000,
    527   AddSubImmediateMask  = 0xFF000000,
    528   #define ADD_SUB_IMMEDIATE(A)           \
    529   A##_w_imm = AddSubImmediateFixed | A,  \
    530   A##_x_imm = AddSubImmediateFixed | A | SixtyFourBits
    531   ADD_SUB_OP_LIST(ADD_SUB_IMMEDIATE)
    532   #undef ADD_SUB_IMMEDIATE
    533 };
    534 
    535 enum AddSubShiftedOp {
    536   AddSubShiftedFixed   = 0x0B000000,
    537   AddSubShiftedFMask   = 0x1F200000,
    538   AddSubShiftedMask    = 0xFF200000,
    539   #define ADD_SUB_SHIFTED(A)             \
    540   A##_w_shift = AddSubShiftedFixed | A,  \
    541   A##_x_shift = AddSubShiftedFixed | A | SixtyFourBits
    542   ADD_SUB_OP_LIST(ADD_SUB_SHIFTED)
    543   #undef ADD_SUB_SHIFTED
    544 };
    545 
    546 enum AddSubExtendedOp {
    547   AddSubExtendedFixed  = 0x0B200000,
    548   AddSubExtendedFMask  = 0x1F200000,
    549   AddSubExtendedMask   = 0xFFE00000,
    550   #define ADD_SUB_EXTENDED(A)           \
    551   A##_w_ext = AddSubExtendedFixed | A,  \
    552   A##_x_ext = AddSubExtendedFixed | A | SixtyFourBits
    553   ADD_SUB_OP_LIST(ADD_SUB_EXTENDED)
    554   #undef ADD_SUB_EXTENDED
    555 };
    556 
    557 // Add/sub with carry.
    558 enum AddSubWithCarryOp {
    559   AddSubWithCarryFixed = 0x1A000000,
    560   AddSubWithCarryFMask = 0x1FE00000,
    561   AddSubWithCarryMask  = 0xFFE0FC00,
    562   ADC_w                = AddSubWithCarryFixed | ADD,
    563   ADC_x                = AddSubWithCarryFixed | ADD | SixtyFourBits,
    564   ADC                  = ADC_w,
    565   ADCS_w               = AddSubWithCarryFixed | ADDS,
    566   ADCS_x               = AddSubWithCarryFixed | ADDS | SixtyFourBits,
    567   SBC_w                = AddSubWithCarryFixed | SUB,
    568   SBC_x                = AddSubWithCarryFixed | SUB | SixtyFourBits,
    569   SBC                  = SBC_w,
    570   SBCS_w               = AddSubWithCarryFixed | SUBS,
    571   SBCS_x               = AddSubWithCarryFixed | SUBS | SixtyFourBits
    572 };
    573 
    574 
    575 // Logical (immediate and shifted register).
    576 enum LogicalOp {
    577   LogicalOpMask = 0x60200000,
    578   NOT   = 0x00200000,
    579   AND   = 0x00000000,
    580   BIC   = AND | NOT,
    581   ORR   = 0x20000000,
    582   ORN   = ORR | NOT,
    583   EOR   = 0x40000000,
    584   EON   = EOR | NOT,
    585   ANDS  = 0x60000000,
    586   BICS  = ANDS | NOT
    587 };
    588 
    589 // Logical immediate.
    590 enum LogicalImmediateOp {
    591   LogicalImmediateFixed = 0x12000000,
    592   LogicalImmediateFMask = 0x1F800000,
    593   LogicalImmediateMask  = 0xFF800000,
    594   AND_w_imm   = LogicalImmediateFixed | AND,
    595   AND_x_imm   = LogicalImmediateFixed | AND | SixtyFourBits,
    596   ORR_w_imm   = LogicalImmediateFixed | ORR,
    597   ORR_x_imm   = LogicalImmediateFixed | ORR | SixtyFourBits,
    598   EOR_w_imm   = LogicalImmediateFixed | EOR,
    599   EOR_x_imm   = LogicalImmediateFixed | EOR | SixtyFourBits,
    600   ANDS_w_imm  = LogicalImmediateFixed | ANDS,
    601   ANDS_x_imm  = LogicalImmediateFixed | ANDS | SixtyFourBits
    602 };
    603 
    604 // Logical shifted register.
    605 enum LogicalShiftedOp {
    606   LogicalShiftedFixed = 0x0A000000,
    607   LogicalShiftedFMask = 0x1F000000,
    608   LogicalShiftedMask  = 0xFF200000,
    609   AND_w               = LogicalShiftedFixed | AND,
    610   AND_x               = LogicalShiftedFixed | AND | SixtyFourBits,
    611   AND_shift           = AND_w,
    612   BIC_w               = LogicalShiftedFixed | BIC,
    613   BIC_x               = LogicalShiftedFixed | BIC | SixtyFourBits,
    614   BIC_shift           = BIC_w,
    615   ORR_w               = LogicalShiftedFixed | ORR,
    616   ORR_x               = LogicalShiftedFixed | ORR | SixtyFourBits,
    617   ORR_shift           = ORR_w,
    618   ORN_w               = LogicalShiftedFixed | ORN,
    619   ORN_x               = LogicalShiftedFixed | ORN | SixtyFourBits,
    620   ORN_shift           = ORN_w,
    621   EOR_w               = LogicalShiftedFixed | EOR,
    622   EOR_x               = LogicalShiftedFixed | EOR | SixtyFourBits,
    623   EOR_shift           = EOR_w,
    624   EON_w               = LogicalShiftedFixed | EON,
    625   EON_x               = LogicalShiftedFixed | EON | SixtyFourBits,
    626   EON_shift           = EON_w,
    627   ANDS_w              = LogicalShiftedFixed | ANDS,
    628   ANDS_x              = LogicalShiftedFixed | ANDS | SixtyFourBits,
    629   ANDS_shift          = ANDS_w,
    630   BICS_w              = LogicalShiftedFixed | BICS,
    631   BICS_x              = LogicalShiftedFixed | BICS | SixtyFourBits,
    632   BICS_shift          = BICS_w
    633 };
    634 
    635 // Move wide immediate.
    636 enum MoveWideImmediateOp {
    637   MoveWideImmediateFixed = 0x12800000,
    638   MoveWideImmediateFMask = 0x1F800000,
    639   MoveWideImmediateMask  = 0xFF800000,
    640   MOVN                   = 0x00000000,
    641   MOVZ                   = 0x40000000,
    642   MOVK                   = 0x60000000,
    643   MOVN_w                 = MoveWideImmediateFixed | MOVN,
    644   MOVN_x                 = MoveWideImmediateFixed | MOVN | SixtyFourBits,
    645   MOVZ_w                 = MoveWideImmediateFixed | MOVZ,
    646   MOVZ_x                 = MoveWideImmediateFixed | MOVZ | SixtyFourBits,
    647   MOVK_w                 = MoveWideImmediateFixed | MOVK,
    648   MOVK_x                 = MoveWideImmediateFixed | MOVK | SixtyFourBits
    649 };
    650 
    651 // Bitfield.
    652 const int kBitfieldNOffset = 22;
    653 enum BitfieldOp {
    654   BitfieldFixed = 0x13000000,
    655   BitfieldFMask = 0x1F800000,
    656   BitfieldMask  = 0xFF800000,
    657   SBFM_w        = BitfieldFixed | 0x00000000,
    658   SBFM_x        = BitfieldFixed | 0x80000000,
    659   SBFM          = SBFM_w,
    660   BFM_w         = BitfieldFixed | 0x20000000,
    661   BFM_x         = BitfieldFixed | 0xA0000000,
    662   BFM           = BFM_w,
    663   UBFM_w        = BitfieldFixed | 0x40000000,
    664   UBFM_x        = BitfieldFixed | 0xC0000000,
    665   UBFM          = UBFM_w
    666   // Bitfield N field.
    667 };
    668 
    669 // Extract.
    670 enum ExtractOp {
    671   ExtractFixed = 0x13800000,
    672   ExtractFMask = 0x1F800000,
    673   ExtractMask  = 0xFFA00000,
    674   EXTR_w       = ExtractFixed | 0x00000000,
    675   EXTR_x       = ExtractFixed | 0x80000000,
    676   EXTR         = EXTR_w
    677 };
    678 
    679 // Unconditional branch.
    680 enum UnconditionalBranchOp {
    681   UnconditionalBranchFixed = 0x14000000,
    682   UnconditionalBranchFMask = 0x7C000000,
    683   UnconditionalBranchMask  = 0xFC000000,
    684   B                        = UnconditionalBranchFixed | 0x00000000,
    685   BL                       = UnconditionalBranchFixed | 0x80000000
    686 };
    687 
    688 // Unconditional branch to register.
    689 enum UnconditionalBranchToRegisterOp {
    690   UnconditionalBranchToRegisterFixed = 0xD6000000,
    691   UnconditionalBranchToRegisterFMask = 0xFE000000,
    692   UnconditionalBranchToRegisterMask  = 0xFFFFFC1F,
    693   BR      = UnconditionalBranchToRegisterFixed | 0x001F0000,
    694   BLR     = UnconditionalBranchToRegisterFixed | 0x003F0000,
    695   RET     = UnconditionalBranchToRegisterFixed | 0x005F0000
    696 };
    697 
    698 // Compare and branch.
    699 enum CompareBranchOp {
    700   CompareBranchFixed = 0x34000000,
    701   CompareBranchFMask = 0x7E000000,
    702   CompareBranchMask  = 0xFF000000,
    703   CBZ_w              = CompareBranchFixed | 0x00000000,
    704   CBZ_x              = CompareBranchFixed | 0x80000000,
    705   CBZ                = CBZ_w,
    706   CBNZ_w             = CompareBranchFixed | 0x01000000,
    707   CBNZ_x             = CompareBranchFixed | 0x81000000,
    708   CBNZ               = CBNZ_w
    709 };
    710 
    711 // Test and branch.
    712 enum TestBranchOp {
    713   TestBranchFixed = 0x36000000,
    714   TestBranchFMask = 0x7E000000,
    715   TestBranchMask  = 0x7F000000,
    716   TBZ             = TestBranchFixed | 0x00000000,
    717   TBNZ            = TestBranchFixed | 0x01000000
    718 };
    719 
    720 // Conditional branch.
    721 enum ConditionalBranchOp {
    722   ConditionalBranchFixed = 0x54000000,
    723   ConditionalBranchFMask = 0xFE000000,
    724   ConditionalBranchMask  = 0xFF000010,
    725   B_cond                 = ConditionalBranchFixed | 0x00000000
    726 };
    727 
    728 // System.
    729 // System instruction encoding is complicated because some instructions use op
    730 // and CR fields to encode parameters. To handle this cleanly, the system
    731 // instructions are split into more than one enum.
    732 
    733 enum SystemOp {
    734   SystemFixed = 0xD5000000,
    735   SystemFMask = 0xFFC00000
    736 };
    737 
    738 enum SystemSysRegOp {
    739   SystemSysRegFixed = 0xD5100000,
    740   SystemSysRegFMask = 0xFFD00000,
    741   SystemSysRegMask  = 0xFFF00000,
    742   MRS               = SystemSysRegFixed | 0x00200000,
    743   MSR               = SystemSysRegFixed | 0x00000000
    744 };
    745 
    746 enum SystemHintOp {
    747   SystemHintFixed = 0xD503201F,
    748   SystemHintFMask = 0xFFFFF01F,
    749   SystemHintMask  = 0xFFFFF01F,
    750   HINT            = SystemHintFixed | 0x00000000
    751 };
    752 
    753 // Exception.
    754 enum ExceptionOp {
    755   ExceptionFixed = 0xD4000000,
    756   ExceptionFMask = 0xFF000000,
    757   ExceptionMask  = 0xFFE0001F,
    758   HLT            = ExceptionFixed | 0x00400000,
    759   BRK            = ExceptionFixed | 0x00200000,
    760   SVC            = ExceptionFixed | 0x00000001,
    761   HVC            = ExceptionFixed | 0x00000002,
    762   SMC            = ExceptionFixed | 0x00000003,
    763   DCPS1          = ExceptionFixed | 0x00A00001,
    764   DCPS2          = ExceptionFixed | 0x00A00002,
    765   DCPS3          = ExceptionFixed | 0x00A00003
    766 };
    767 // Code used to spot hlt instructions that should not be hit.
    768 const int kHltBadCode = 0xbad;
    769 
    770 enum MemBarrierOp {
    771   MemBarrierFixed = 0xD503309F,
    772   MemBarrierFMask = 0xFFFFF09F,
    773   MemBarrierMask  = 0xFFFFF0FF,
    774   DSB             = MemBarrierFixed | 0x00000000,
    775   DMB             = MemBarrierFixed | 0x00000020,
    776   ISB             = MemBarrierFixed | 0x00000040
    777 };
    778 
    779 // Any load or store (including pair).
    780 enum LoadStoreAnyOp {
    781   LoadStoreAnyFMask = 0x0a000000,
    782   LoadStoreAnyFixed = 0x08000000
    783 };
    784 
    785 // Any load pair or store pair.
    786 enum LoadStorePairAnyOp {
    787   LoadStorePairAnyFMask = 0x3a000000,
    788   LoadStorePairAnyFixed = 0x28000000
    789 };
    790 
    791 #define LOAD_STORE_PAIR_OP_LIST(V)                                         \
    792   V(STP, w, 0x00000000)                                                    \
    793   , V(LDP, w, 0x00400000), V(LDPSW, x, 0x40400000), V(STP, x, 0x80000000), \
    794       V(LDP, x, 0x80400000), V(STP, s, 0x04000000), V(LDP, s, 0x04400000), \
    795       V(STP, d, 0x44000000), V(LDP, d, 0x44400000), V(STP, q, 0x84000000), \
    796       V(LDP, q, 0x84400000)
    797 
    798 // Load/store pair (post, pre and offset.)
    799 enum LoadStorePairOp {
    800   LoadStorePairMask = 0xC4400000,
    801   LoadStorePairLBit = 1 << 22,
    802   #define LOAD_STORE_PAIR(A, B, C) \
    803   A##_##B = C
    804   LOAD_STORE_PAIR_OP_LIST(LOAD_STORE_PAIR)
    805   #undef LOAD_STORE_PAIR
    806 };
    807 
    808 enum LoadStorePairPostIndexOp {
    809   LoadStorePairPostIndexFixed = 0x28800000,
    810   LoadStorePairPostIndexFMask = 0x3B800000,
    811   LoadStorePairPostIndexMask  = 0xFFC00000,
    812   #define LOAD_STORE_PAIR_POST_INDEX(A, B, C)  \
    813   A##_##B##_post = LoadStorePairPostIndexFixed | A##_##B
    814   LOAD_STORE_PAIR_OP_LIST(LOAD_STORE_PAIR_POST_INDEX)
    815   #undef LOAD_STORE_PAIR_POST_INDEX
    816 };
    817 
    818 enum LoadStorePairPreIndexOp {
    819   LoadStorePairPreIndexFixed = 0x29800000,
    820   LoadStorePairPreIndexFMask = 0x3B800000,
    821   LoadStorePairPreIndexMask  = 0xFFC00000,
    822   #define LOAD_STORE_PAIR_PRE_INDEX(A, B, C)  \
    823   A##_##B##_pre = LoadStorePairPreIndexFixed | A##_##B
    824   LOAD_STORE_PAIR_OP_LIST(LOAD_STORE_PAIR_PRE_INDEX)
    825   #undef LOAD_STORE_PAIR_PRE_INDEX
    826 };
    827 
    828 enum LoadStorePairOffsetOp {
    829   LoadStorePairOffsetFixed = 0x29000000,
    830   LoadStorePairOffsetFMask = 0x3B800000,
    831   LoadStorePairOffsetMask  = 0xFFC00000,
    832   #define LOAD_STORE_PAIR_OFFSET(A, B, C)  \
    833   A##_##B##_off = LoadStorePairOffsetFixed | A##_##B
    834   LOAD_STORE_PAIR_OP_LIST(LOAD_STORE_PAIR_OFFSET)
    835   #undef LOAD_STORE_PAIR_OFFSET
    836 };
    837 
    838 // Load literal.
    839 enum LoadLiteralOp {
    840   LoadLiteralFixed = 0x18000000,
    841   LoadLiteralFMask = 0x3B000000,
    842   LoadLiteralMask  = 0xFF000000,
    843   LDR_w_lit        = LoadLiteralFixed | 0x00000000,
    844   LDR_x_lit        = LoadLiteralFixed | 0x40000000,
    845   LDRSW_x_lit      = LoadLiteralFixed | 0x80000000,
    846   PRFM_lit         = LoadLiteralFixed | 0xC0000000,
    847   LDR_s_lit        = LoadLiteralFixed | 0x04000000,
    848   LDR_d_lit        = LoadLiteralFixed | 0x44000000
    849 };
    850 
    851 // clang-format off
    852 
    853 #define LOAD_STORE_OP_LIST(V)  \
    854   V(ST, RB, w,  0x00000000),   \
    855   V(ST, RH, w,  0x40000000),   \
    856   V(ST, R, w,   0x80000000),   \
    857   V(ST, R, x,   0xC0000000),   \
    858   V(LD, RB, w,  0x00400000),   \
    859   V(LD, RH, w,  0x40400000),   \
    860   V(LD, R, w,   0x80400000),   \
    861   V(LD, R, x,   0xC0400000),   \
    862   V(LD, RSB, x, 0x00800000),   \
    863   V(LD, RSH, x, 0x40800000),   \
    864   V(LD, RSW, x, 0x80800000),   \
    865   V(LD, RSB, w, 0x00C00000),   \
    866   V(LD, RSH, w, 0x40C00000),   \
    867   V(ST, R, b,   0x04000000),   \
    868   V(ST, R, h,   0x44000000),   \
    869   V(ST, R, s,   0x84000000),   \
    870   V(ST, R, d,   0xC4000000),   \
    871   V(ST, R, q,   0x04800000),   \
    872   V(LD, R, b,   0x04400000),   \
    873   V(LD, R, h,   0x44400000),   \
    874   V(LD, R, s,   0x84400000),   \
    875   V(LD, R, d,   0xC4400000),   \
    876   V(LD, R, q,   0x04C00000)
    877 
    878 // clang-format on
    879 
    880 // Load/store unscaled offset.
    881 enum LoadStoreUnscaledOffsetOp {
    882   LoadStoreUnscaledOffsetFixed = 0x38000000,
    883   LoadStoreUnscaledOffsetFMask = 0x3B200C00,
    884   LoadStoreUnscaledOffsetMask  = 0xFFE00C00,
    885   #define LOAD_STORE_UNSCALED(A, B, C, D)  \
    886   A##U##B##_##C = LoadStoreUnscaledOffsetFixed | D
    887   LOAD_STORE_OP_LIST(LOAD_STORE_UNSCALED)
    888   #undef LOAD_STORE_UNSCALED
    889 };
    890 
    891 // Load/store (post, pre, offset and unsigned.)
    892 enum LoadStoreOp {
    893   LoadStoreMask = 0xC4C00000,
    894 #define LOAD_STORE(A, B, C, D) A##B##_##C = D
    895   LOAD_STORE_OP_LIST(LOAD_STORE),
    896 #undef LOAD_STORE
    897   PRFM = 0xC0800000
    898 };
    899 
    900 // Load/store post index.
    901 enum LoadStorePostIndex {
    902   LoadStorePostIndexFixed = 0x38000400,
    903   LoadStorePostIndexFMask = 0x3B200C00,
    904   LoadStorePostIndexMask  = 0xFFE00C00,
    905   #define LOAD_STORE_POST_INDEX(A, B, C, D)  \
    906   A##B##_##C##_post = LoadStorePostIndexFixed | D
    907   LOAD_STORE_OP_LIST(LOAD_STORE_POST_INDEX)
    908   #undef LOAD_STORE_POST_INDEX
    909 };
    910 
    911 // Load/store pre index.
    912 enum LoadStorePreIndex {
    913   LoadStorePreIndexFixed = 0x38000C00,
    914   LoadStorePreIndexFMask = 0x3B200C00,
    915   LoadStorePreIndexMask  = 0xFFE00C00,
    916   #define LOAD_STORE_PRE_INDEX(A, B, C, D)  \
    917   A##B##_##C##_pre = LoadStorePreIndexFixed | D
    918   LOAD_STORE_OP_LIST(LOAD_STORE_PRE_INDEX)
    919   #undef LOAD_STORE_PRE_INDEX
    920 };
    921 
    922 // Load/store unsigned offset.
    923 enum LoadStoreUnsignedOffset {
    924   LoadStoreUnsignedOffsetFixed = 0x39000000,
    925   LoadStoreUnsignedOffsetFMask = 0x3B000000,
    926   LoadStoreUnsignedOffsetMask  = 0xFFC00000,
    927   PRFM_unsigned                = LoadStoreUnsignedOffsetFixed | PRFM,
    928   #define LOAD_STORE_UNSIGNED_OFFSET(A, B, C, D) \
    929   A##B##_##C##_unsigned = LoadStoreUnsignedOffsetFixed | D
    930   LOAD_STORE_OP_LIST(LOAD_STORE_UNSIGNED_OFFSET)
    931   #undef LOAD_STORE_UNSIGNED_OFFSET
    932 };
    933 
    934 // Load/store register offset.
    935 enum LoadStoreRegisterOffset {
    936   LoadStoreRegisterOffsetFixed = 0x38200800,
    937   LoadStoreRegisterOffsetFMask = 0x3B200C00,
    938   LoadStoreRegisterOffsetMask  = 0xFFE00C00,
    939   PRFM_reg                     = LoadStoreRegisterOffsetFixed | PRFM,
    940   #define LOAD_STORE_REGISTER_OFFSET(A, B, C, D) \
    941   A##B##_##C##_reg = LoadStoreRegisterOffsetFixed | D
    942   LOAD_STORE_OP_LIST(LOAD_STORE_REGISTER_OFFSET)
    943   #undef LOAD_STORE_REGISTER_OFFSET
    944 };
    945 
    946 // Load/store acquire/release.
    947 enum LoadStoreAcquireReleaseOp {
    948   LoadStoreAcquireReleaseFixed = 0x08000000,
    949   LoadStoreAcquireReleaseFMask = 0x3F000000,
    950   LoadStoreAcquireReleaseMask = 0xCFC08000,
    951   STLXR_b = LoadStoreAcquireReleaseFixed | 0x00008000,
    952   LDAXR_b = LoadStoreAcquireReleaseFixed | 0x00408000,
    953   STLR_b  = LoadStoreAcquireReleaseFixed | 0x00808000,
    954   LDAR_b  = LoadStoreAcquireReleaseFixed | 0x00C08000,
    955   STLXR_h = LoadStoreAcquireReleaseFixed | 0x40008000,
    956   LDAXR_h = LoadStoreAcquireReleaseFixed | 0x40408000,
    957   STLR_h  = LoadStoreAcquireReleaseFixed | 0x40808000,
    958   LDAR_h  = LoadStoreAcquireReleaseFixed | 0x40C08000,
    959   STLXR_w = LoadStoreAcquireReleaseFixed | 0x80008000,
    960   LDAXR_w = LoadStoreAcquireReleaseFixed | 0x80408000,
    961   STLR_w  = LoadStoreAcquireReleaseFixed | 0x80808000,
    962   LDAR_w  = LoadStoreAcquireReleaseFixed | 0x80C08000,
    963   STLXR_x = LoadStoreAcquireReleaseFixed | 0xC0008000,
    964   LDAXR_x = LoadStoreAcquireReleaseFixed | 0xC0408000,
    965   STLR_x  = LoadStoreAcquireReleaseFixed | 0xC0808000,
    966   LDAR_x  = LoadStoreAcquireReleaseFixed | 0xC0C08000,
    967 };
    968 
    969 // Conditional compare.
    970 enum ConditionalCompareOp {
    971   ConditionalCompareMask = 0x60000000,
    972   CCMN                   = 0x20000000,
    973   CCMP                   = 0x60000000
    974 };
    975 
    976 // Conditional compare register.
    977 enum ConditionalCompareRegisterOp {
    978   ConditionalCompareRegisterFixed = 0x1A400000,
    979   ConditionalCompareRegisterFMask = 0x1FE00800,
    980   ConditionalCompareRegisterMask  = 0xFFE00C10,
    981   CCMN_w = ConditionalCompareRegisterFixed | CCMN,
    982   CCMN_x = ConditionalCompareRegisterFixed | SixtyFourBits | CCMN,
    983   CCMP_w = ConditionalCompareRegisterFixed | CCMP,
    984   CCMP_x = ConditionalCompareRegisterFixed | SixtyFourBits | CCMP
    985 };
    986 
    987 // Conditional compare immediate.
    988 enum ConditionalCompareImmediateOp {
    989   ConditionalCompareImmediateFixed = 0x1A400800,
    990   ConditionalCompareImmediateFMask = 0x1FE00800,
    991   ConditionalCompareImmediateMask  = 0xFFE00C10,
    992   CCMN_w_imm = ConditionalCompareImmediateFixed | CCMN,
    993   CCMN_x_imm = ConditionalCompareImmediateFixed | SixtyFourBits | CCMN,
    994   CCMP_w_imm = ConditionalCompareImmediateFixed | CCMP,
    995   CCMP_x_imm = ConditionalCompareImmediateFixed | SixtyFourBits | CCMP
    996 };
    997 
    998 // Conditional select.
    999 enum ConditionalSelectOp {
   1000   ConditionalSelectFixed = 0x1A800000,
   1001   ConditionalSelectFMask = 0x1FE00000,
   1002   ConditionalSelectMask  = 0xFFE00C00,
   1003   CSEL_w                 = ConditionalSelectFixed | 0x00000000,
   1004   CSEL_x                 = ConditionalSelectFixed | 0x80000000,
   1005   CSEL                   = CSEL_w,
   1006   CSINC_w                = ConditionalSelectFixed | 0x00000400,
   1007   CSINC_x                = ConditionalSelectFixed | 0x80000400,
   1008   CSINC                  = CSINC_w,
   1009   CSINV_w                = ConditionalSelectFixed | 0x40000000,
   1010   CSINV_x                = ConditionalSelectFixed | 0xC0000000,
   1011   CSINV                  = CSINV_w,
   1012   CSNEG_w                = ConditionalSelectFixed | 0x40000400,
   1013   CSNEG_x                = ConditionalSelectFixed | 0xC0000400,
   1014   CSNEG                  = CSNEG_w
   1015 };
   1016 
   1017 // Data processing 1 source.
   1018 enum DataProcessing1SourceOp {
   1019   DataProcessing1SourceFixed = 0x5AC00000,
   1020   DataProcessing1SourceFMask = 0x5FE00000,
   1021   DataProcessing1SourceMask  = 0xFFFFFC00,
   1022   RBIT    = DataProcessing1SourceFixed | 0x00000000,
   1023   RBIT_w  = RBIT,
   1024   RBIT_x  = RBIT | SixtyFourBits,
   1025   REV16   = DataProcessing1SourceFixed | 0x00000400,
   1026   REV16_w = REV16,
   1027   REV16_x = REV16 | SixtyFourBits,
   1028   REV     = DataProcessing1SourceFixed | 0x00000800,
   1029   REV_w   = REV,
   1030   REV32_x = REV | SixtyFourBits,
   1031   REV_x   = DataProcessing1SourceFixed | SixtyFourBits | 0x00000C00,
   1032   CLZ     = DataProcessing1SourceFixed | 0x00001000,
   1033   CLZ_w   = CLZ,
   1034   CLZ_x   = CLZ | SixtyFourBits,
   1035   CLS     = DataProcessing1SourceFixed | 0x00001400,
   1036   CLS_w   = CLS,
   1037   CLS_x   = CLS | SixtyFourBits
   1038 };
   1039 
   1040 // Data processing 2 source.
   1041 enum DataProcessing2SourceOp {
   1042   DataProcessing2SourceFixed = 0x1AC00000,
   1043   DataProcessing2SourceFMask = 0x5FE00000,
   1044   DataProcessing2SourceMask  = 0xFFE0FC00,
   1045   UDIV_w  = DataProcessing2SourceFixed | 0x00000800,
   1046   UDIV_x  = DataProcessing2SourceFixed | 0x80000800,
   1047   UDIV    = UDIV_w,
   1048   SDIV_w  = DataProcessing2SourceFixed | 0x00000C00,
   1049   SDIV_x  = DataProcessing2SourceFixed | 0x80000C00,
   1050   SDIV    = SDIV_w,
   1051   LSLV_w  = DataProcessing2SourceFixed | 0x00002000,
   1052   LSLV_x  = DataProcessing2SourceFixed | 0x80002000,
   1053   LSLV    = LSLV_w,
   1054   LSRV_w  = DataProcessing2SourceFixed | 0x00002400,
   1055   LSRV_x  = DataProcessing2SourceFixed | 0x80002400,
   1056   LSRV    = LSRV_w,
   1057   ASRV_w  = DataProcessing2SourceFixed | 0x00002800,
   1058   ASRV_x  = DataProcessing2SourceFixed | 0x80002800,
   1059   ASRV    = ASRV_w,
   1060   RORV_w  = DataProcessing2SourceFixed | 0x00002C00,
   1061   RORV_x  = DataProcessing2SourceFixed | 0x80002C00,
   1062   RORV    = RORV_w,
   1063   CRC32B  = DataProcessing2SourceFixed | 0x00004000,
   1064   CRC32H  = DataProcessing2SourceFixed | 0x00004400,
   1065   CRC32W  = DataProcessing2SourceFixed | 0x00004800,
   1066   CRC32X  = DataProcessing2SourceFixed | SixtyFourBits | 0x00004C00,
   1067   CRC32CB = DataProcessing2SourceFixed | 0x00005000,
   1068   CRC32CH = DataProcessing2SourceFixed | 0x00005400,
   1069   CRC32CW = DataProcessing2SourceFixed | 0x00005800,
   1070   CRC32CX = DataProcessing2SourceFixed | SixtyFourBits | 0x00005C00
   1071 };
   1072 
   1073 // Data processing 3 source.
   1074 enum DataProcessing3SourceOp {
   1075   DataProcessing3SourceFixed = 0x1B000000,
   1076   DataProcessing3SourceFMask = 0x1F000000,
   1077   DataProcessing3SourceMask  = 0xFFE08000,
   1078   MADD_w                     = DataProcessing3SourceFixed | 0x00000000,
   1079   MADD_x                     = DataProcessing3SourceFixed | 0x80000000,
   1080   MADD                       = MADD_w,
   1081   MSUB_w                     = DataProcessing3SourceFixed | 0x00008000,
   1082   MSUB_x                     = DataProcessing3SourceFixed | 0x80008000,
   1083   MSUB                       = MSUB_w,
   1084   SMADDL_x                   = DataProcessing3SourceFixed | 0x80200000,
   1085   SMSUBL_x                   = DataProcessing3SourceFixed | 0x80208000,
   1086   SMULH_x                    = DataProcessing3SourceFixed | 0x80400000,
   1087   UMADDL_x                   = DataProcessing3SourceFixed | 0x80A00000,
   1088   UMSUBL_x                   = DataProcessing3SourceFixed | 0x80A08000,
   1089   UMULH_x                    = DataProcessing3SourceFixed | 0x80C00000
   1090 };
   1091 
   1092 // Floating point compare.
   1093 enum FPCompareOp {
   1094   FPCompareFixed = 0x1E202000,
   1095   FPCompareFMask = 0x5F203C00,
   1096   FPCompareMask  = 0xFFE0FC1F,
   1097   FCMP_s         = FPCompareFixed | 0x00000000,
   1098   FCMP_d         = FPCompareFixed | FP64 | 0x00000000,
   1099   FCMP           = FCMP_s,
   1100   FCMP_s_zero    = FPCompareFixed | 0x00000008,
   1101   FCMP_d_zero    = FPCompareFixed | FP64 | 0x00000008,
   1102   FCMP_zero      = FCMP_s_zero,
   1103   FCMPE_s        = FPCompareFixed | 0x00000010,
   1104   FCMPE_d        = FPCompareFixed | FP64 | 0x00000010,
   1105   FCMPE_s_zero   = FPCompareFixed | 0x00000018,
   1106   FCMPE_d_zero   = FPCompareFixed | FP64 | 0x00000018
   1107 };
   1108 
   1109 // Floating point conditional compare.
   1110 enum FPConditionalCompareOp {
   1111   FPConditionalCompareFixed = 0x1E200400,
   1112   FPConditionalCompareFMask = 0x5F200C00,
   1113   FPConditionalCompareMask  = 0xFFE00C10,
   1114   FCCMP_s                   = FPConditionalCompareFixed | 0x00000000,
   1115   FCCMP_d                   = FPConditionalCompareFixed | FP64 | 0x00000000,
   1116   FCCMP                     = FCCMP_s,
   1117   FCCMPE_s                  = FPConditionalCompareFixed | 0x00000010,
   1118   FCCMPE_d                  = FPConditionalCompareFixed | FP64 | 0x00000010,
   1119   FCCMPE                    = FCCMPE_s
   1120 };
   1121 
   1122 // Floating point conditional select.
   1123 enum FPConditionalSelectOp {
   1124   FPConditionalSelectFixed = 0x1E200C00,
   1125   FPConditionalSelectFMask = 0x5F200C00,
   1126   FPConditionalSelectMask  = 0xFFE00C00,
   1127   FCSEL_s                  = FPConditionalSelectFixed | 0x00000000,
   1128   FCSEL_d                  = FPConditionalSelectFixed | FP64 | 0x00000000,
   1129   FCSEL                    = FCSEL_s
   1130 };
   1131 
   1132 // Floating point immediate.
   1133 enum FPImmediateOp {
   1134   FPImmediateFixed = 0x1E201000,
   1135   FPImmediateFMask = 0x5F201C00,
   1136   FPImmediateMask  = 0xFFE01C00,
   1137   FMOV_s_imm       = FPImmediateFixed | 0x00000000,
   1138   FMOV_d_imm       = FPImmediateFixed | FP64 | 0x00000000
   1139 };
   1140 
   1141 // Floating point data processing 1 source.
   1142 enum FPDataProcessing1SourceOp {
   1143   FPDataProcessing1SourceFixed = 0x1E204000,
   1144   FPDataProcessing1SourceFMask = 0x5F207C00,
   1145   FPDataProcessing1SourceMask = 0xFFFFFC00,
   1146   FMOV_s = FPDataProcessing1SourceFixed | 0x00000000,
   1147   FMOV_d = FPDataProcessing1SourceFixed | FP64 | 0x00000000,
   1148   FMOV = FMOV_s,
   1149   FABS_s = FPDataProcessing1SourceFixed | 0x00008000,
   1150   FABS_d = FPDataProcessing1SourceFixed | FP64 | 0x00008000,
   1151   FABS = FABS_s,
   1152   FNEG_s = FPDataProcessing1SourceFixed | 0x00010000,
   1153   FNEG_d = FPDataProcessing1SourceFixed | FP64 | 0x00010000,
   1154   FNEG = FNEG_s,
   1155   FSQRT_s = FPDataProcessing1SourceFixed | 0x00018000,
   1156   FSQRT_d = FPDataProcessing1SourceFixed | FP64 | 0x00018000,
   1157   FSQRT = FSQRT_s,
   1158   FCVT_ds = FPDataProcessing1SourceFixed | 0x00028000,
   1159   FCVT_sd = FPDataProcessing1SourceFixed | FP64 | 0x00020000,
   1160   FCVT_hs = FPDataProcessing1SourceFixed | 0x00038000,
   1161   FCVT_hd = FPDataProcessing1SourceFixed | FP64 | 0x00038000,
   1162   FCVT_sh = FPDataProcessing1SourceFixed | 0x00C20000,
   1163   FCVT_dh = FPDataProcessing1SourceFixed | 0x00C28000,
   1164   FRINTN_s = FPDataProcessing1SourceFixed | 0x00040000,
   1165   FRINTN_d = FPDataProcessing1SourceFixed | FP64 | 0x00040000,
   1166   FRINTN = FRINTN_s,
   1167   FRINTP_s = FPDataProcessing1SourceFixed | 0x00048000,
   1168   FRINTP_d = FPDataProcessing1SourceFixed | FP64 | 0x00048000,
   1169   FRINTP = FRINTP_s,
   1170   FRINTM_s = FPDataProcessing1SourceFixed | 0x00050000,
   1171   FRINTM_d = FPDataProcessing1SourceFixed | FP64 | 0x00050000,
   1172   FRINTM = FRINTM_s,
   1173   FRINTZ_s = FPDataProcessing1SourceFixed | 0x00058000,
   1174   FRINTZ_d = FPDataProcessing1SourceFixed | FP64 | 0x00058000,
   1175   FRINTZ = FRINTZ_s,
   1176   FRINTA_s = FPDataProcessing1SourceFixed | 0x00060000,
   1177   FRINTA_d = FPDataProcessing1SourceFixed | FP64 | 0x00060000,
   1178   FRINTA = FRINTA_s,
   1179   FRINTX_s = FPDataProcessing1SourceFixed | 0x00070000,
   1180   FRINTX_d = FPDataProcessing1SourceFixed | FP64 | 0x00070000,
   1181   FRINTX = FRINTX_s,
   1182   FRINTI_s = FPDataProcessing1SourceFixed | 0x00078000,
   1183   FRINTI_d = FPDataProcessing1SourceFixed | FP64 | 0x00078000,
   1184   FRINTI = FRINTI_s
   1185 };
   1186 
   1187 // Floating point data processing 2 source.
   1188 enum FPDataProcessing2SourceOp {
   1189   FPDataProcessing2SourceFixed = 0x1E200800,
   1190   FPDataProcessing2SourceFMask = 0x5F200C00,
   1191   FPDataProcessing2SourceMask  = 0xFFE0FC00,
   1192   FMUL     = FPDataProcessing2SourceFixed | 0x00000000,
   1193   FMUL_s   = FMUL,
   1194   FMUL_d   = FMUL | FP64,
   1195   FDIV     = FPDataProcessing2SourceFixed | 0x00001000,
   1196   FDIV_s   = FDIV,
   1197   FDIV_d   = FDIV | FP64,
   1198   FADD     = FPDataProcessing2SourceFixed | 0x00002000,
   1199   FADD_s   = FADD,
   1200   FADD_d   = FADD | FP64,
   1201   FSUB     = FPDataProcessing2SourceFixed | 0x00003000,
   1202   FSUB_s   = FSUB,
   1203   FSUB_d   = FSUB | FP64,
   1204   FMAX     = FPDataProcessing2SourceFixed | 0x00004000,
   1205   FMAX_s   = FMAX,
   1206   FMAX_d   = FMAX | FP64,
   1207   FMIN     = FPDataProcessing2SourceFixed | 0x00005000,
   1208   FMIN_s   = FMIN,
   1209   FMIN_d   = FMIN | FP64,
   1210   FMAXNM   = FPDataProcessing2SourceFixed | 0x00006000,
   1211   FMAXNM_s = FMAXNM,
   1212   FMAXNM_d = FMAXNM | FP64,
   1213   FMINNM   = FPDataProcessing2SourceFixed | 0x00007000,
   1214   FMINNM_s = FMINNM,
   1215   FMINNM_d = FMINNM | FP64,
   1216   FNMUL    = FPDataProcessing2SourceFixed | 0x00008000,
   1217   FNMUL_s  = FNMUL,
   1218   FNMUL_d  = FNMUL | FP64
   1219 };
   1220 
   1221 // Floating point data processing 3 source.
   1222 enum FPDataProcessing3SourceOp {
   1223   FPDataProcessing3SourceFixed = 0x1F000000,
   1224   FPDataProcessing3SourceFMask = 0x5F000000,
   1225   FPDataProcessing3SourceMask  = 0xFFE08000,
   1226   FMADD_s                      = FPDataProcessing3SourceFixed | 0x00000000,
   1227   FMSUB_s                      = FPDataProcessing3SourceFixed | 0x00008000,
   1228   FNMADD_s                     = FPDataProcessing3SourceFixed | 0x00200000,
   1229   FNMSUB_s                     = FPDataProcessing3SourceFixed | 0x00208000,
   1230   FMADD_d                      = FPDataProcessing3SourceFixed | 0x00400000,
   1231   FMSUB_d                      = FPDataProcessing3SourceFixed | 0x00408000,
   1232   FNMADD_d                     = FPDataProcessing3SourceFixed | 0x00600000,
   1233   FNMSUB_d                     = FPDataProcessing3SourceFixed | 0x00608000
   1234 };
   1235 
   1236 // Conversion between floating point and integer.
   1237 enum FPIntegerConvertOp {
   1238   FPIntegerConvertFixed = 0x1E200000,
   1239   FPIntegerConvertFMask = 0x5F20FC00,
   1240   FPIntegerConvertMask = 0xFFFFFC00,
   1241   FCVTNS = FPIntegerConvertFixed | 0x00000000,
   1242   FCVTNS_ws = FCVTNS,
   1243   FCVTNS_xs = FCVTNS | SixtyFourBits,
   1244   FCVTNS_wd = FCVTNS | FP64,
   1245   FCVTNS_xd = FCVTNS | SixtyFourBits | FP64,
   1246   FCVTNU = FPIntegerConvertFixed | 0x00010000,
   1247   FCVTNU_ws = FCVTNU,
   1248   FCVTNU_xs = FCVTNU | SixtyFourBits,
   1249   FCVTNU_wd = FCVTNU | FP64,
   1250   FCVTNU_xd = FCVTNU | SixtyFourBits | FP64,
   1251   FCVTPS = FPIntegerConvertFixed | 0x00080000,
   1252   FCVTPS_ws = FCVTPS,
   1253   FCVTPS_xs = FCVTPS | SixtyFourBits,
   1254   FCVTPS_wd = FCVTPS | FP64,
   1255   FCVTPS_xd = FCVTPS | SixtyFourBits | FP64,
   1256   FCVTPU = FPIntegerConvertFixed | 0x00090000,
   1257   FCVTPU_ws = FCVTPU,
   1258   FCVTPU_xs = FCVTPU | SixtyFourBits,
   1259   FCVTPU_wd = FCVTPU | FP64,
   1260   FCVTPU_xd = FCVTPU | SixtyFourBits | FP64,
   1261   FCVTMS = FPIntegerConvertFixed | 0x00100000,
   1262   FCVTMS_ws = FCVTMS,
   1263   FCVTMS_xs = FCVTMS | SixtyFourBits,
   1264   FCVTMS_wd = FCVTMS | FP64,
   1265   FCVTMS_xd = FCVTMS | SixtyFourBits | FP64,
   1266   FCVTMU = FPIntegerConvertFixed | 0x00110000,
   1267   FCVTMU_ws = FCVTMU,
   1268   FCVTMU_xs = FCVTMU | SixtyFourBits,
   1269   FCVTMU_wd = FCVTMU | FP64,
   1270   FCVTMU_xd = FCVTMU | SixtyFourBits | FP64,
   1271   FCVTZS = FPIntegerConvertFixed | 0x00180000,
   1272   FCVTZS_ws = FCVTZS,
   1273   FCVTZS_xs = FCVTZS | SixtyFourBits,
   1274   FCVTZS_wd = FCVTZS | FP64,
   1275   FCVTZS_xd = FCVTZS | SixtyFourBits | FP64,
   1276   FCVTZU = FPIntegerConvertFixed | 0x00190000,
   1277   FCVTZU_ws = FCVTZU,
   1278   FCVTZU_xs = FCVTZU | SixtyFourBits,
   1279   FCVTZU_wd = FCVTZU | FP64,
   1280   FCVTZU_xd = FCVTZU | SixtyFourBits | FP64,
   1281   SCVTF = FPIntegerConvertFixed | 0x00020000,
   1282   SCVTF_sw = SCVTF,
   1283   SCVTF_sx = SCVTF | SixtyFourBits,
   1284   SCVTF_dw = SCVTF | FP64,
   1285   SCVTF_dx = SCVTF | SixtyFourBits | FP64,
   1286   UCVTF = FPIntegerConvertFixed | 0x00030000,
   1287   UCVTF_sw = UCVTF,
   1288   UCVTF_sx = UCVTF | SixtyFourBits,
   1289   UCVTF_dw = UCVTF | FP64,
   1290   UCVTF_dx = UCVTF | SixtyFourBits | FP64,
   1291   FCVTAS = FPIntegerConvertFixed | 0x00040000,
   1292   FCVTAS_ws = FCVTAS,
   1293   FCVTAS_xs = FCVTAS | SixtyFourBits,
   1294   FCVTAS_wd = FCVTAS | FP64,
   1295   FCVTAS_xd = FCVTAS | SixtyFourBits | FP64,
   1296   FCVTAU = FPIntegerConvertFixed | 0x00050000,
   1297   FCVTAU_ws = FCVTAU,
   1298   FCVTAU_xs = FCVTAU | SixtyFourBits,
   1299   FCVTAU_wd = FCVTAU | FP64,
   1300   FCVTAU_xd = FCVTAU | SixtyFourBits | FP64,
   1301   FMOV_ws = FPIntegerConvertFixed | 0x00060000,
   1302   FMOV_sw = FPIntegerConvertFixed | 0x00070000,
   1303   FMOV_xd = FMOV_ws | SixtyFourBits | FP64,
   1304   FMOV_dx = FMOV_sw | SixtyFourBits | FP64,
   1305   FMOV_d1_x = FPIntegerConvertFixed | SixtyFourBits | 0x008F0000,
   1306   FMOV_x_d1 = FPIntegerConvertFixed | SixtyFourBits | 0x008E0000
   1307 };
   1308 
   1309 // Conversion between fixed point and floating point.
   1310 enum FPFixedPointConvertOp {
   1311   FPFixedPointConvertFixed = 0x1E000000,
   1312   FPFixedPointConvertFMask = 0x5F200000,
   1313   FPFixedPointConvertMask  = 0xFFFF0000,
   1314   FCVTZS_fixed    = FPFixedPointConvertFixed | 0x00180000,
   1315   FCVTZS_ws_fixed = FCVTZS_fixed,
   1316   FCVTZS_xs_fixed = FCVTZS_fixed | SixtyFourBits,
   1317   FCVTZS_wd_fixed = FCVTZS_fixed | FP64,
   1318   FCVTZS_xd_fixed = FCVTZS_fixed | SixtyFourBits | FP64,
   1319   FCVTZU_fixed    = FPFixedPointConvertFixed | 0x00190000,
   1320   FCVTZU_ws_fixed = FCVTZU_fixed,
   1321   FCVTZU_xs_fixed = FCVTZU_fixed | SixtyFourBits,
   1322   FCVTZU_wd_fixed = FCVTZU_fixed | FP64,
   1323   FCVTZU_xd_fixed = FCVTZU_fixed | SixtyFourBits | FP64,
   1324   SCVTF_fixed     = FPFixedPointConvertFixed | 0x00020000,
   1325   SCVTF_sw_fixed  = SCVTF_fixed,
   1326   SCVTF_sx_fixed  = SCVTF_fixed | SixtyFourBits,
   1327   SCVTF_dw_fixed  = SCVTF_fixed | FP64,
   1328   SCVTF_dx_fixed  = SCVTF_fixed | SixtyFourBits | FP64,
   1329   UCVTF_fixed     = FPFixedPointConvertFixed | 0x00030000,
   1330   UCVTF_sw_fixed  = UCVTF_fixed,
   1331   UCVTF_sx_fixed  = UCVTF_fixed | SixtyFourBits,
   1332   UCVTF_dw_fixed  = UCVTF_fixed | FP64,
   1333   UCVTF_dx_fixed  = UCVTF_fixed | SixtyFourBits | FP64
   1334 };
   1335 
   1336 // NEON instructions with two register operands.
   1337 enum NEON2RegMiscOp {
   1338   NEON2RegMiscFixed = 0x0E200800,
   1339   NEON2RegMiscFMask = 0x9F3E0C00,
   1340   NEON2RegMiscMask = 0xBF3FFC00,
   1341   NEON2RegMiscUBit = 0x20000000,
   1342   NEON_REV64 = NEON2RegMiscFixed | 0x00000000,
   1343   NEON_REV32 = NEON2RegMiscFixed | 0x20000000,
   1344   NEON_REV16 = NEON2RegMiscFixed | 0x00001000,
   1345   NEON_SADDLP = NEON2RegMiscFixed | 0x00002000,
   1346   NEON_UADDLP = NEON_SADDLP | NEON2RegMiscUBit,
   1347   NEON_SUQADD = NEON2RegMiscFixed | 0x00003000,
   1348   NEON_USQADD = NEON_SUQADD | NEON2RegMiscUBit,
   1349   NEON_CLS = NEON2RegMiscFixed | 0x00004000,
   1350   NEON_CLZ = NEON2RegMiscFixed | 0x20004000,
   1351   NEON_CNT = NEON2RegMiscFixed | 0x00005000,
   1352   NEON_RBIT_NOT = NEON2RegMiscFixed | 0x20005000,
   1353   NEON_SADALP = NEON2RegMiscFixed | 0x00006000,
   1354   NEON_UADALP = NEON_SADALP | NEON2RegMiscUBit,
   1355   NEON_SQABS = NEON2RegMiscFixed | 0x00007000,
   1356   NEON_SQNEG = NEON2RegMiscFixed | 0x20007000,
   1357   NEON_CMGT_zero = NEON2RegMiscFixed | 0x00008000,
   1358   NEON_CMGE_zero = NEON2RegMiscFixed | 0x20008000,
   1359   NEON_CMEQ_zero = NEON2RegMiscFixed | 0x00009000,
   1360   NEON_CMLE_zero = NEON2RegMiscFixed | 0x20009000,
   1361   NEON_CMLT_zero = NEON2RegMiscFixed | 0x0000A000,
   1362   NEON_ABS = NEON2RegMiscFixed | 0x0000B000,
   1363   NEON_NEG = NEON2RegMiscFixed | 0x2000B000,
   1364   NEON_XTN = NEON2RegMiscFixed | 0x00012000,
   1365   NEON_SQXTUN = NEON2RegMiscFixed | 0x20012000,
   1366   NEON_SHLL = NEON2RegMiscFixed | 0x20013000,
   1367   NEON_SQXTN = NEON2RegMiscFixed | 0x00014000,
   1368   NEON_UQXTN = NEON_SQXTN | NEON2RegMiscUBit,
   1369 
   1370   NEON2RegMiscOpcode = 0x0001F000,
   1371   NEON_RBIT_NOT_opcode = NEON_RBIT_NOT & NEON2RegMiscOpcode,
   1372   NEON_NEG_opcode = NEON_NEG & NEON2RegMiscOpcode,
   1373   NEON_XTN_opcode = NEON_XTN & NEON2RegMiscOpcode,
   1374   NEON_UQXTN_opcode = NEON_UQXTN & NEON2RegMiscOpcode,
   1375 
   1376   // These instructions use only one bit of the size field. The other bit is
   1377   // used to distinguish between instructions.
   1378   NEON2RegMiscFPMask = NEON2RegMiscMask | 0x00800000,
   1379   NEON_FABS = NEON2RegMiscFixed | 0x0080F000,
   1380   NEON_FNEG = NEON2RegMiscFixed | 0x2080F000,
   1381   NEON_FCVTN = NEON2RegMiscFixed | 0x00016000,
   1382   NEON_FCVTXN = NEON2RegMiscFixed | 0x20016000,
   1383   NEON_FCVTL = NEON2RegMiscFixed | 0x00017000,
   1384   NEON_FRINTN = NEON2RegMiscFixed | 0x00018000,
   1385   NEON_FRINTA = NEON2RegMiscFixed | 0x20018000,
   1386   NEON_FRINTP = NEON2RegMiscFixed | 0x00818000,
   1387   NEON_FRINTM = NEON2RegMiscFixed | 0x00019000,
   1388   NEON_FRINTX = NEON2RegMiscFixed | 0x20019000,
   1389   NEON_FRINTZ = NEON2RegMiscFixed | 0x00819000,
   1390   NEON_FRINTI = NEON2RegMiscFixed | 0x20819000,
   1391   NEON_FCVTNS = NEON2RegMiscFixed | 0x0001A000,
   1392   NEON_FCVTNU = NEON_FCVTNS | NEON2RegMiscUBit,
   1393   NEON_FCVTPS = NEON2RegMiscFixed | 0x0081A000,
   1394   NEON_FCVTPU = NEON_FCVTPS | NEON2RegMiscUBit,
   1395   NEON_FCVTMS = NEON2RegMiscFixed | 0x0001B000,
   1396   NEON_FCVTMU = NEON_FCVTMS | NEON2RegMiscUBit,
   1397   NEON_FCVTZS = NEON2RegMiscFixed | 0x0081B000,
   1398   NEON_FCVTZU = NEON_FCVTZS | NEON2RegMiscUBit,
   1399   NEON_FCVTAS = NEON2RegMiscFixed | 0x0001C000,
   1400   NEON_FCVTAU = NEON_FCVTAS | NEON2RegMiscUBit,
   1401   NEON_FSQRT = NEON2RegMiscFixed | 0x2081F000,
   1402   NEON_SCVTF = NEON2RegMiscFixed | 0x0001D000,
   1403   NEON_UCVTF = NEON_SCVTF | NEON2RegMiscUBit,
   1404   NEON_URSQRTE = NEON2RegMiscFixed | 0x2081C000,
   1405   NEON_URECPE = NEON2RegMiscFixed | 0x0081C000,
   1406   NEON_FRSQRTE = NEON2RegMiscFixed | 0x2081D000,
   1407   NEON_FRECPE = NEON2RegMiscFixed | 0x0081D000,
   1408   NEON_FCMGT_zero = NEON2RegMiscFixed | 0x0080C000,
   1409   NEON_FCMGE_zero = NEON2RegMiscFixed | 0x2080C000,
   1410   NEON_FCMEQ_zero = NEON2RegMiscFixed | 0x0080D000,
   1411   NEON_FCMLE_zero = NEON2RegMiscFixed | 0x2080D000,
   1412   NEON_FCMLT_zero = NEON2RegMiscFixed | 0x0080E000,
   1413 
   1414   NEON_FCVTL_opcode = NEON_FCVTL & NEON2RegMiscOpcode,
   1415   NEON_FCVTN_opcode = NEON_FCVTN & NEON2RegMiscOpcode
   1416 };
   1417 
   1418 // NEON instructions with three same-type operands.
   1419 enum NEON3SameOp {
   1420   NEON3SameFixed = 0x0E200400,
   1421   NEON3SameFMask = 0x9F200400,
   1422   NEON3SameMask = 0xBF20FC00,
   1423   NEON3SameUBit = 0x20000000,
   1424   NEON_ADD = NEON3SameFixed | 0x00008000,
   1425   NEON_ADDP = NEON3SameFixed | 0x0000B800,
   1426   NEON_SHADD = NEON3SameFixed | 0x00000000,
   1427   NEON_SHSUB = NEON3SameFixed | 0x00002000,
   1428   NEON_SRHADD = NEON3SameFixed | 0x00001000,
   1429   NEON_CMEQ = NEON3SameFixed | NEON3SameUBit | 0x00008800,
   1430   NEON_CMGE = NEON3SameFixed | 0x00003800,
   1431   NEON_CMGT = NEON3SameFixed | 0x00003000,
   1432   NEON_CMHI = NEON3SameFixed | NEON3SameUBit | NEON_CMGT,
   1433   NEON_CMHS = NEON3SameFixed | NEON3SameUBit | NEON_CMGE,
   1434   NEON_CMTST = NEON3SameFixed | 0x00008800,
   1435   NEON_MLA = NEON3SameFixed | 0x00009000,
   1436   NEON_MLS = NEON3SameFixed | 0x20009000,
   1437   NEON_MUL = NEON3SameFixed | 0x00009800,
   1438   NEON_PMUL = NEON3SameFixed | 0x20009800,
   1439   NEON_SRSHL = NEON3SameFixed | 0x00005000,
   1440   NEON_SQSHL = NEON3SameFixed | 0x00004800,
   1441   NEON_SQRSHL = NEON3SameFixed | 0x00005800,
   1442   NEON_SSHL = NEON3SameFixed | 0x00004000,
   1443   NEON_SMAX = NEON3SameFixed | 0x00006000,
   1444   NEON_SMAXP = NEON3SameFixed | 0x0000A000,
   1445   NEON_SMIN = NEON3SameFixed | 0x00006800,
   1446   NEON_SMINP = NEON3SameFixed | 0x0000A800,
   1447   NEON_SABD = NEON3SameFixed | 0x00007000,
   1448   NEON_SABA = NEON3SameFixed | 0x00007800,
   1449   NEON_UABD = NEON3SameFixed | NEON3SameUBit | NEON_SABD,
   1450   NEON_UABA = NEON3SameFixed | NEON3SameUBit | NEON_SABA,
   1451   NEON_SQADD = NEON3SameFixed | 0x00000800,
   1452   NEON_SQSUB = NEON3SameFixed | 0x00002800,
   1453   NEON_SUB = NEON3SameFixed | NEON3SameUBit | 0x00008000,
   1454   NEON_UHADD = NEON3SameFixed | NEON3SameUBit | NEON_SHADD,
   1455   NEON_UHSUB = NEON3SameFixed | NEON3SameUBit | NEON_SHSUB,
   1456   NEON_URHADD = NEON3SameFixed | NEON3SameUBit | NEON_SRHADD,
   1457   NEON_UMAX = NEON3SameFixed | NEON3SameUBit | NEON_SMAX,
   1458   NEON_UMAXP = NEON3SameFixed | NEON3SameUBit | NEON_SMAXP,
   1459   NEON_UMIN = NEON3SameFixed | NEON3SameUBit | NEON_SMIN,
   1460   NEON_UMINP = NEON3SameFixed | NEON3SameUBit | NEON_SMINP,
   1461   NEON_URSHL = NEON3SameFixed | NEON3SameUBit | NEON_SRSHL,
   1462   NEON_UQADD = NEON3SameFixed | NEON3SameUBit | NEON_SQADD,
   1463   NEON_UQRSHL = NEON3SameFixed | NEON3SameUBit | NEON_SQRSHL,
   1464   NEON_UQSHL = NEON3SameFixed | NEON3SameUBit | NEON_SQSHL,
   1465   NEON_UQSUB = NEON3SameFixed | NEON3SameUBit | NEON_SQSUB,
   1466   NEON_USHL = NEON3SameFixed | NEON3SameUBit | NEON_SSHL,
   1467   NEON_SQDMULH = NEON3SameFixed | 0x0000B000,
   1468   NEON_SQRDMULH = NEON3SameFixed | 0x2000B000,
   1469 
   1470   // NEON floating point instructions with three same-type operands.
   1471   NEON3SameFPFixed = NEON3SameFixed | 0x0000C000,
   1472   NEON3SameFPFMask = NEON3SameFMask | 0x0000C000,
   1473   NEON3SameFPMask = NEON3SameMask | 0x00800000,
   1474   NEON_FADD = NEON3SameFixed | 0x0000D000,
   1475   NEON_FSUB = NEON3SameFixed | 0x0080D000,
   1476   NEON_FMUL = NEON3SameFixed | 0x2000D800,
   1477   NEON_FDIV = NEON3SameFixed | 0x2000F800,
   1478   NEON_FMAX = NEON3SameFixed | 0x0000F000,
   1479   NEON_FMAXNM = NEON3SameFixed | 0x0000C000,
   1480   NEON_FMAXP = NEON3SameFixed | 0x2000F000,
   1481   NEON_FMAXNMP = NEON3SameFixed | 0x2000C000,
   1482   NEON_FMIN = NEON3SameFixed | 0x0080F000,
   1483   NEON_FMINNM = NEON3SameFixed | 0x0080C000,
   1484   NEON_FMINP = NEON3SameFixed | 0x2080F000,
   1485   NEON_FMINNMP = NEON3SameFixed | 0x2080C000,
   1486   NEON_FMLA = NEON3SameFixed | 0x0000C800,
   1487   NEON_FMLS = NEON3SameFixed | 0x0080C800,
   1488   NEON_FMULX = NEON3SameFixed | 0x0000D800,
   1489   NEON_FRECPS = NEON3SameFixed | 0x0000F800,
   1490   NEON_FRSQRTS = NEON3SameFixed | 0x0080F800,
   1491   NEON_FABD = NEON3SameFixed | 0x2080D000,
   1492   NEON_FADDP = NEON3SameFixed | 0x2000D000,
   1493   NEON_FCMEQ = NEON3SameFixed | 0x0000E000,
   1494   NEON_FCMGE = NEON3SameFixed | 0x2000E000,
   1495   NEON_FCMGT = NEON3SameFixed | 0x2080E000,
   1496   NEON_FACGE = NEON3SameFixed | 0x2000E800,
   1497   NEON_FACGT = NEON3SameFixed | 0x2080E800,
   1498 
   1499   // NEON logical instructions with three same-type operands.
   1500   NEON3SameLogicalFixed = NEON3SameFixed | 0x00001800,
   1501   NEON3SameLogicalFMask = NEON3SameFMask | 0x0000F800,
   1502   NEON3SameLogicalMask = 0xBFE0FC00,
   1503   NEON3SameLogicalFormatMask = NEON_Q,
   1504   NEON_AND = NEON3SameLogicalFixed | 0x00000000,
   1505   NEON_ORR = NEON3SameLogicalFixed | 0x00A00000,
   1506   NEON_ORN = NEON3SameLogicalFixed | 0x00C00000,
   1507   NEON_EOR = NEON3SameLogicalFixed | 0x20000000,
   1508   NEON_BIC = NEON3SameLogicalFixed | 0x00400000,
   1509   NEON_BIF = NEON3SameLogicalFixed | 0x20C00000,
   1510   NEON_BIT = NEON3SameLogicalFixed | 0x20800000,
   1511   NEON_BSL = NEON3SameLogicalFixed | 0x20400000
   1512 };
   1513 
   1514 // NEON instructions with three different-type operands.
   1515 enum NEON3DifferentOp {
   1516   NEON3DifferentFixed = 0x0E200000,
   1517   NEON3DifferentFMask = 0x9F200C00,
   1518   NEON3DifferentMask = 0xFF20FC00,
   1519   NEON_ADDHN = NEON3DifferentFixed | 0x00004000,
   1520   NEON_ADDHN2 = NEON_ADDHN | NEON_Q,
   1521   NEON_PMULL = NEON3DifferentFixed | 0x0000E000,
   1522   NEON_PMULL2 = NEON_PMULL | NEON_Q,
   1523   NEON_RADDHN = NEON3DifferentFixed | 0x20004000,
   1524   NEON_RADDHN2 = NEON_RADDHN | NEON_Q,
   1525   NEON_RSUBHN = NEON3DifferentFixed | 0x20006000,
   1526   NEON_RSUBHN2 = NEON_RSUBHN | NEON_Q,
   1527   NEON_SABAL = NEON3DifferentFixed | 0x00005000,
   1528   NEON_SABAL2 = NEON_SABAL | NEON_Q,
   1529   NEON_SABDL = NEON3DifferentFixed | 0x00007000,
   1530   NEON_SABDL2 = NEON_SABDL | NEON_Q,
   1531   NEON_SADDL = NEON3DifferentFixed | 0x00000000,
   1532   NEON_SADDL2 = NEON_SADDL | NEON_Q,
   1533   NEON_SADDW = NEON3DifferentFixed | 0x00001000,
   1534   NEON_SADDW2 = NEON_SADDW | NEON_Q,
   1535   NEON_SMLAL = NEON3DifferentFixed | 0x00008000,
   1536   NEON_SMLAL2 = NEON_SMLAL | NEON_Q,
   1537   NEON_SMLSL = NEON3DifferentFixed | 0x0000A000,
   1538   NEON_SMLSL2 = NEON_SMLSL | NEON_Q,
   1539   NEON_SMULL = NEON3DifferentFixed | 0x0000C000,
   1540   NEON_SMULL2 = NEON_SMULL | NEON_Q,
   1541   NEON_SSUBL = NEON3DifferentFixed | 0x00002000,
   1542   NEON_SSUBL2 = NEON_SSUBL | NEON_Q,
   1543   NEON_SSUBW = NEON3DifferentFixed | 0x00003000,
   1544   NEON_SSUBW2 = NEON_SSUBW | NEON_Q,
   1545   NEON_SQDMLAL = NEON3DifferentFixed | 0x00009000,
   1546   NEON_SQDMLAL2 = NEON_SQDMLAL | NEON_Q,
   1547   NEON_SQDMLSL = NEON3DifferentFixed | 0x0000B000,
   1548   NEON_SQDMLSL2 = NEON_SQDMLSL | NEON_Q,
   1549   NEON_SQDMULL = NEON3DifferentFixed | 0x0000D000,
   1550   NEON_SQDMULL2 = NEON_SQDMULL | NEON_Q,
   1551   NEON_SUBHN = NEON3DifferentFixed | 0x00006000,
   1552   NEON_SUBHN2 = NEON_SUBHN | NEON_Q,
   1553   NEON_UABAL = NEON_SABAL | NEON3SameUBit,
   1554   NEON_UABAL2 = NEON_UABAL | NEON_Q,
   1555   NEON_UABDL = NEON_SABDL | NEON3SameUBit,
   1556   NEON_UABDL2 = NEON_UABDL | NEON_Q,
   1557   NEON_UADDL = NEON_SADDL | NEON3SameUBit,
   1558   NEON_UADDL2 = NEON_UADDL | NEON_Q,
   1559   NEON_UADDW = NEON_SADDW | NEON3SameUBit,
   1560   NEON_UADDW2 = NEON_UADDW | NEON_Q,
   1561   NEON_UMLAL = NEON_SMLAL | NEON3SameUBit,
   1562   NEON_UMLAL2 = NEON_UMLAL | NEON_Q,
   1563   NEON_UMLSL = NEON_SMLSL | NEON3SameUBit,
   1564   NEON_UMLSL2 = NEON_UMLSL | NEON_Q,
   1565   NEON_UMULL = NEON_SMULL | NEON3SameUBit,
   1566   NEON_UMULL2 = NEON_UMULL | NEON_Q,
   1567   NEON_USUBL = NEON_SSUBL | NEON3SameUBit,
   1568   NEON_USUBL2 = NEON_USUBL | NEON_Q,
   1569   NEON_USUBW = NEON_SSUBW | NEON3SameUBit,
   1570   NEON_USUBW2 = NEON_USUBW | NEON_Q
   1571 };
   1572 
   1573 // NEON instructions operating across vectors.
   1574 enum NEONAcrossLanesOp {
   1575   NEONAcrossLanesFixed = 0x0E300800,
   1576   NEONAcrossLanesFMask = 0x9F3E0C00,
   1577   NEONAcrossLanesMask = 0xBF3FFC00,
   1578   NEON_ADDV = NEONAcrossLanesFixed | 0x0001B000,
   1579   NEON_SADDLV = NEONAcrossLanesFixed | 0x00003000,
   1580   NEON_UADDLV = NEONAcrossLanesFixed | 0x20003000,
   1581   NEON_SMAXV = NEONAcrossLanesFixed | 0x0000A000,
   1582   NEON_SMINV = NEONAcrossLanesFixed | 0x0001A000,
   1583   NEON_UMAXV = NEONAcrossLanesFixed | 0x2000A000,
   1584   NEON_UMINV = NEONAcrossLanesFixed | 0x2001A000,
   1585 
   1586   // NEON floating point across instructions.
   1587   NEONAcrossLanesFPFixed = NEONAcrossLanesFixed | 0x0000C000,
   1588   NEONAcrossLanesFPFMask = NEONAcrossLanesFMask | 0x0000C000,
   1589   NEONAcrossLanesFPMask = NEONAcrossLanesMask | 0x00800000,
   1590 
   1591   NEON_FMAXV = NEONAcrossLanesFPFixed | 0x2000F000,
   1592   NEON_FMINV = NEONAcrossLanesFPFixed | 0x2080F000,
   1593   NEON_FMAXNMV = NEONAcrossLanesFPFixed | 0x2000C000,
   1594   NEON_FMINNMV = NEONAcrossLanesFPFixed | 0x2080C000
   1595 };
   1596 
   1597 // NEON instructions with indexed element operand.
   1598 enum NEONByIndexedElementOp {
   1599   NEONByIndexedElementFixed = 0x0F000000,
   1600   NEONByIndexedElementFMask = 0x9F000400,
   1601   NEONByIndexedElementMask = 0xBF00F400,
   1602   NEON_MUL_byelement = NEONByIndexedElementFixed | 0x00008000,
   1603   NEON_MLA_byelement = NEONByIndexedElementFixed | 0x20000000,
   1604   NEON_MLS_byelement = NEONByIndexedElementFixed | 0x20004000,
   1605   NEON_SMULL_byelement = NEONByIndexedElementFixed | 0x0000A000,
   1606   NEON_SMLAL_byelement = NEONByIndexedElementFixed | 0x00002000,
   1607   NEON_SMLSL_byelement = NEONByIndexedElementFixed | 0x00006000,
   1608   NEON_UMULL_byelement = NEONByIndexedElementFixed | 0x2000A000,
   1609   NEON_UMLAL_byelement = NEONByIndexedElementFixed | 0x20002000,
   1610   NEON_UMLSL_byelement = NEONByIndexedElementFixed | 0x20006000,
   1611   NEON_SQDMULL_byelement = NEONByIndexedElementFixed | 0x0000B000,
   1612   NEON_SQDMLAL_byelement = NEONByIndexedElementFixed | 0x00003000,
   1613   NEON_SQDMLSL_byelement = NEONByIndexedElementFixed | 0x00007000,
   1614   NEON_SQDMULH_byelement = NEONByIndexedElementFixed | 0x0000C000,
   1615   NEON_SQRDMULH_byelement = NEONByIndexedElementFixed | 0x0000D000,
   1616 
   1617   // Floating point instructions.
   1618   NEONByIndexedElementFPFixed = NEONByIndexedElementFixed | 0x00800000,
   1619   NEONByIndexedElementFPMask = NEONByIndexedElementMask | 0x00800000,
   1620   NEON_FMLA_byelement = NEONByIndexedElementFPFixed | 0x00001000,
   1621   NEON_FMLS_byelement = NEONByIndexedElementFPFixed | 0x00005000,
   1622   NEON_FMUL_byelement = NEONByIndexedElementFPFixed | 0x00009000,
   1623   NEON_FMULX_byelement = NEONByIndexedElementFPFixed | 0x20009000
   1624 };
   1625 
   1626 // NEON modified immediate.
   1627 enum NEONModifiedImmediateOp {
   1628   NEONModifiedImmediateFixed = 0x0F000400,
   1629   NEONModifiedImmediateFMask = 0x9FF80400,
   1630   NEONModifiedImmediateOpBit = 0x20000000,
   1631   NEONModifiedImmediate_MOVI = NEONModifiedImmediateFixed | 0x00000000,
   1632   NEONModifiedImmediate_MVNI = NEONModifiedImmediateFixed | 0x20000000,
   1633   NEONModifiedImmediate_ORR = NEONModifiedImmediateFixed | 0x00001000,
   1634   NEONModifiedImmediate_BIC = NEONModifiedImmediateFixed | 0x20001000
   1635 };
   1636 
   1637 // NEON extract.
   1638 enum NEONExtractOp {
   1639   NEONExtractFixed = 0x2E000000,
   1640   NEONExtractFMask = 0xBF208400,
   1641   NEONExtractMask = 0xBFE08400,
   1642   NEON_EXT = NEONExtractFixed | 0x00000000
   1643 };
   1644 
   1645 enum NEONLoadStoreMultiOp {
   1646   NEONLoadStoreMultiL = 0x00400000,
   1647   NEONLoadStoreMulti1_1v = 0x00007000,
   1648   NEONLoadStoreMulti1_2v = 0x0000A000,
   1649   NEONLoadStoreMulti1_3v = 0x00006000,
   1650   NEONLoadStoreMulti1_4v = 0x00002000,
   1651   NEONLoadStoreMulti2 = 0x00008000,
   1652   NEONLoadStoreMulti3 = 0x00004000,
   1653   NEONLoadStoreMulti4 = 0x00000000
   1654 };
   1655 
   1656 // NEON load/store multiple structures.
   1657 enum NEONLoadStoreMultiStructOp {
   1658   NEONLoadStoreMultiStructFixed = 0x0C000000,
   1659   NEONLoadStoreMultiStructFMask = 0xBFBF0000,
   1660   NEONLoadStoreMultiStructMask = 0xBFFFF000,
   1661   NEONLoadStoreMultiStructStore = NEONLoadStoreMultiStructFixed,
   1662   NEONLoadStoreMultiStructLoad =
   1663       NEONLoadStoreMultiStructFixed | NEONLoadStoreMultiL,
   1664   NEON_LD1_1v = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti1_1v,
   1665   NEON_LD1_2v = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti1_2v,
   1666   NEON_LD1_3v = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti1_3v,
   1667   NEON_LD1_4v = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti1_4v,
   1668   NEON_LD2 = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti2,
   1669   NEON_LD3 = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti3,
   1670   NEON_LD4 = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti4,
   1671   NEON_ST1_1v = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti1_1v,
   1672   NEON_ST1_2v = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti1_2v,
   1673   NEON_ST1_3v = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti1_3v,
   1674   NEON_ST1_4v = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti1_4v,
   1675   NEON_ST2 = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti2,
   1676   NEON_ST3 = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti3,
   1677   NEON_ST4 = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti4
   1678 };
   1679 
   1680 // NEON load/store multiple structures with post-index addressing.
   1681 enum NEONLoadStoreMultiStructPostIndexOp {
   1682   NEONLoadStoreMultiStructPostIndexFixed = 0x0C800000,
   1683   NEONLoadStoreMultiStructPostIndexFMask = 0xBFA00000,
   1684   NEONLoadStoreMultiStructPostIndexMask = 0xBFE0F000,
   1685   NEONLoadStoreMultiStructPostIndex = 0x00800000,
   1686   NEON_LD1_1v_post = NEON_LD1_1v | NEONLoadStoreMultiStructPostIndex,
   1687   NEON_LD1_2v_post = NEON_LD1_2v | NEONLoadStoreMultiStructPostIndex,
   1688   NEON_LD1_3v_post = NEON_LD1_3v | NEONLoadStoreMultiStructPostIndex,
   1689   NEON_LD1_4v_post = NEON_LD1_4v | NEONLoadStoreMultiStructPostIndex,
   1690   NEON_LD2_post = NEON_LD2 | NEONLoadStoreMultiStructPostIndex,
   1691   NEON_LD3_post = NEON_LD3 | NEONLoadStoreMultiStructPostIndex,
   1692   NEON_LD4_post = NEON_LD4 | NEONLoadStoreMultiStructPostIndex,
   1693   NEON_ST1_1v_post = NEON_ST1_1v | NEONLoadStoreMultiStructPostIndex,
   1694   NEON_ST1_2v_post = NEON_ST1_2v | NEONLoadStoreMultiStructPostIndex,
   1695   NEON_ST1_3v_post = NEON_ST1_3v | NEONLoadStoreMultiStructPostIndex,
   1696   NEON_ST1_4v_post = NEON_ST1_4v | NEONLoadStoreMultiStructPostIndex,
   1697   NEON_ST2_post = NEON_ST2 | NEONLoadStoreMultiStructPostIndex,
   1698   NEON_ST3_post = NEON_ST3 | NEONLoadStoreMultiStructPostIndex,
   1699   NEON_ST4_post = NEON_ST4 | NEONLoadStoreMultiStructPostIndex
   1700 };
   1701 
   1702 enum NEONLoadStoreSingleOp {
   1703   NEONLoadStoreSingle1 = 0x00000000,
   1704   NEONLoadStoreSingle2 = 0x00200000,
   1705   NEONLoadStoreSingle3 = 0x00002000,
   1706   NEONLoadStoreSingle4 = 0x00202000,
   1707   NEONLoadStoreSingleL = 0x00400000,
   1708   NEONLoadStoreSingle_b = 0x00000000,
   1709   NEONLoadStoreSingle_h = 0x00004000,
   1710   NEONLoadStoreSingle_s = 0x00008000,
   1711   NEONLoadStoreSingle_d = 0x00008400,
   1712   NEONLoadStoreSingleAllLanes = 0x0000C000,
   1713   NEONLoadStoreSingleLenMask = 0x00202000
   1714 };
   1715 
   1716 // NEON load/store single structure.
   1717 enum NEONLoadStoreSingleStructOp {
   1718   NEONLoadStoreSingleStructFixed = 0x0D000000,
   1719   NEONLoadStoreSingleStructFMask = 0xBF9F0000,
   1720   NEONLoadStoreSingleStructMask = 0xBFFFE000,
   1721   NEONLoadStoreSingleStructStore = NEONLoadStoreSingleStructFixed,
   1722   NEONLoadStoreSingleStructLoad =
   1723       NEONLoadStoreSingleStructFixed | NEONLoadStoreSingleL,
   1724   NEONLoadStoreSingleStructLoad1 =
   1725       NEONLoadStoreSingle1 | NEONLoadStoreSingleStructLoad,
   1726   NEONLoadStoreSingleStructLoad2 =
   1727       NEONLoadStoreSingle2 | NEONLoadStoreSingleStructLoad,
   1728   NEONLoadStoreSingleStructLoad3 =
   1729       NEONLoadStoreSingle3 | NEONLoadStoreSingleStructLoad,
   1730   NEONLoadStoreSingleStructLoad4 =
   1731       NEONLoadStoreSingle4 | NEONLoadStoreSingleStructLoad,
   1732   NEONLoadStoreSingleStructStore1 =
   1733       NEONLoadStoreSingle1 | NEONLoadStoreSingleStructFixed,
   1734   NEONLoadStoreSingleStructStore2 =
   1735       NEONLoadStoreSingle2 | NEONLoadStoreSingleStructFixed,
   1736   NEONLoadStoreSingleStructStore3 =
   1737       NEONLoadStoreSingle3 | NEONLoadStoreSingleStructFixed,
   1738   NEONLoadStoreSingleStructStore4 =
   1739       NEONLoadStoreSingle4 | NEONLoadStoreSingleStructFixed,
   1740   NEON_LD1_b = NEONLoadStoreSingleStructLoad1 | NEONLoadStoreSingle_b,
   1741   NEON_LD1_h = NEONLoadStoreSingleStructLoad1 | NEONLoadStoreSingle_h,
   1742   NEON_LD1_s = NEONLoadStoreSingleStructLoad1 | NEONLoadStoreSingle_s,
   1743   NEON_LD1_d = NEONLoadStoreSingleStructLoad1 | NEONLoadStoreSingle_d,
   1744   NEON_LD1R = NEONLoadStoreSingleStructLoad1 | NEONLoadStoreSingleAllLanes,
   1745   NEON_ST1_b = NEONLoadStoreSingleStructStore1 | NEONLoadStoreSingle_b,
   1746   NEON_ST1_h = NEONLoadStoreSingleStructStore1 | NEONLoadStoreSingle_h,
   1747   NEON_ST1_s = NEONLoadStoreSingleStructStore1 | NEONLoadStoreSingle_s,
   1748   NEON_ST1_d = NEONLoadStoreSingleStructStore1 | NEONLoadStoreSingle_d,
   1749 
   1750   NEON_LD2_b = NEONLoadStoreSingleStructLoad2 | NEONLoadStoreSingle_b,
   1751   NEON_LD2_h = NEONLoadStoreSingleStructLoad2 | NEONLoadStoreSingle_h,
   1752   NEON_LD2_s = NEONLoadStoreSingleStructLoad2 | NEONLoadStoreSingle_s,
   1753   NEON_LD2_d = NEONLoadStoreSingleStructLoad2 | NEONLoadStoreSingle_d,
   1754   NEON_LD2R = NEONLoadStoreSingleStructLoad2 | NEONLoadStoreSingleAllLanes,
   1755   NEON_ST2_b = NEONLoadStoreSingleStructStore2 | NEONLoadStoreSingle_b,
   1756   NEON_ST2_h = NEONLoadStoreSingleStructStore2 | NEONLoadStoreSingle_h,
   1757   NEON_ST2_s = NEONLoadStoreSingleStructStore2 | NEONLoadStoreSingle_s,
   1758   NEON_ST2_d = NEONLoadStoreSingleStructStore2 | NEONLoadStoreSingle_d,
   1759 
   1760   NEON_LD3_b = NEONLoadStoreSingleStructLoad3 | NEONLoadStoreSingle_b,
   1761   NEON_LD3_h = NEONLoadStoreSingleStructLoad3 | NEONLoadStoreSingle_h,
   1762   NEON_LD3_s = NEONLoadStoreSingleStructLoad3 | NEONLoadStoreSingle_s,
   1763   NEON_LD3_d = NEONLoadStoreSingleStructLoad3 | NEONLoadStoreSingle_d,
   1764   NEON_LD3R = NEONLoadStoreSingleStructLoad3 | NEONLoadStoreSingleAllLanes,
   1765   NEON_ST3_b = NEONLoadStoreSingleStructStore3 | NEONLoadStoreSingle_b,
   1766   NEON_ST3_h = NEONLoadStoreSingleStructStore3 | NEONLoadStoreSingle_h,
   1767   NEON_ST3_s = NEONLoadStoreSingleStructStore3 | NEONLoadStoreSingle_s,
   1768   NEON_ST3_d = NEONLoadStoreSingleStructStore3 | NEONLoadStoreSingle_d,
   1769 
   1770   NEON_LD4_b = NEONLoadStoreSingleStructLoad4 | NEONLoadStoreSingle_b,
   1771   NEON_LD4_h = NEONLoadStoreSingleStructLoad4 | NEONLoadStoreSingle_h,
   1772   NEON_LD4_s = NEONLoadStoreSingleStructLoad4 | NEONLoadStoreSingle_s,
   1773   NEON_LD4_d = NEONLoadStoreSingleStructLoad4 | NEONLoadStoreSingle_d,
   1774   NEON_LD4R = NEONLoadStoreSingleStructLoad4 | NEONLoadStoreSingleAllLanes,
   1775   NEON_ST4_b = NEONLoadStoreSingleStructStore4 | NEONLoadStoreSingle_b,
   1776   NEON_ST4_h = NEONLoadStoreSingleStructStore4 | NEONLoadStoreSingle_h,
   1777   NEON_ST4_s = NEONLoadStoreSingleStructStore4 | NEONLoadStoreSingle_s,
   1778   NEON_ST4_d = NEONLoadStoreSingleStructStore4 | NEONLoadStoreSingle_d
   1779 };
   1780 
   1781 // NEON load/store single structure with post-index addressing.
   1782 enum NEONLoadStoreSingleStructPostIndexOp {
   1783   NEONLoadStoreSingleStructPostIndexFixed = 0x0D800000,
   1784   NEONLoadStoreSingleStructPostIndexFMask = 0xBF800000,
   1785   NEONLoadStoreSingleStructPostIndexMask = 0xBFE0E000,
   1786   NEONLoadStoreSingleStructPostIndex = 0x00800000,
   1787   NEON_LD1_b_post = NEON_LD1_b | NEONLoadStoreSingleStructPostIndex,
   1788   NEON_LD1_h_post = NEON_LD1_h | NEONLoadStoreSingleStructPostIndex,
   1789   NEON_LD1_s_post = NEON_LD1_s | NEONLoadStoreSingleStructPostIndex,
   1790   NEON_LD1_d_post = NEON_LD1_d | NEONLoadStoreSingleStructPostIndex,
   1791   NEON_LD1R_post = NEON_LD1R | NEONLoadStoreSingleStructPostIndex,
   1792   NEON_ST1_b_post = NEON_ST1_b | NEONLoadStoreSingleStructPostIndex,
   1793   NEON_ST1_h_post = NEON_ST1_h | NEONLoadStoreSingleStructPostIndex,
   1794   NEON_ST1_s_post = NEON_ST1_s | NEONLoadStoreSingleStructPostIndex,
   1795   NEON_ST1_d_post = NEON_ST1_d | NEONLoadStoreSingleStructPostIndex,
   1796 
   1797   NEON_LD2_b_post = NEON_LD2_b | NEONLoadStoreSingleStructPostIndex,
   1798   NEON_LD2_h_post = NEON_LD2_h | NEONLoadStoreSingleStructPostIndex,
   1799   NEON_LD2_s_post = NEON_LD2_s | NEONLoadStoreSingleStructPostIndex,
   1800   NEON_LD2_d_post = NEON_LD2_d | NEONLoadStoreSingleStructPostIndex,
   1801   NEON_LD2R_post = NEON_LD2R | NEONLoadStoreSingleStructPostIndex,
   1802   NEON_ST2_b_post = NEON_ST2_b | NEONLoadStoreSingleStructPostIndex,
   1803   NEON_ST2_h_post = NEON_ST2_h | NEONLoadStoreSingleStructPostIndex,
   1804   NEON_ST2_s_post = NEON_ST2_s | NEONLoadStoreSingleStructPostIndex,
   1805   NEON_ST2_d_post = NEON_ST2_d | NEONLoadStoreSingleStructPostIndex,
   1806 
   1807   NEON_LD3_b_post = NEON_LD3_b | NEONLoadStoreSingleStructPostIndex,
   1808   NEON_LD3_h_post = NEON_LD3_h | NEONLoadStoreSingleStructPostIndex,
   1809   NEON_LD3_s_post = NEON_LD3_s | NEONLoadStoreSingleStructPostIndex,
   1810   NEON_LD3_d_post = NEON_LD3_d | NEONLoadStoreSingleStructPostIndex,
   1811   NEON_LD3R_post = NEON_LD3R | NEONLoadStoreSingleStructPostIndex,
   1812   NEON_ST3_b_post = NEON_ST3_b | NEONLoadStoreSingleStructPostIndex,
   1813   NEON_ST3_h_post = NEON_ST3_h | NEONLoadStoreSingleStructPostIndex,
   1814   NEON_ST3_s_post = NEON_ST3_s | NEONLoadStoreSingleStructPostIndex,
   1815   NEON_ST3_d_post = NEON_ST3_d | NEONLoadStoreSingleStructPostIndex,
   1816 
   1817   NEON_LD4_b_post = NEON_LD4_b | NEONLoadStoreSingleStructPostIndex,
   1818   NEON_LD4_h_post = NEON_LD4_h | NEONLoadStoreSingleStructPostIndex,
   1819   NEON_LD4_s_post = NEON_LD4_s | NEONLoadStoreSingleStructPostIndex,
   1820   NEON_LD4_d_post = NEON_LD4_d | NEONLoadStoreSingleStructPostIndex,
   1821   NEON_LD4R_post = NEON_LD4R | NEONLoadStoreSingleStructPostIndex,
   1822   NEON_ST4_b_post = NEON_ST4_b | NEONLoadStoreSingleStructPostIndex,
   1823   NEON_ST4_h_post = NEON_ST4_h | NEONLoadStoreSingleStructPostIndex,
   1824   NEON_ST4_s_post = NEON_ST4_s | NEONLoadStoreSingleStructPostIndex,
   1825   NEON_ST4_d_post = NEON_ST4_d | NEONLoadStoreSingleStructPostIndex
   1826 };
   1827 
   1828 // NEON register copy.
   1829 enum NEONCopyOp {
   1830   NEONCopyFixed = 0x0E000400,
   1831   NEONCopyFMask = 0x9FE08400,
   1832   NEONCopyMask = 0x3FE08400,
   1833   NEONCopyInsElementMask = NEONCopyMask | 0x40000000,
   1834   NEONCopyInsGeneralMask = NEONCopyMask | 0x40007800,
   1835   NEONCopyDupElementMask = NEONCopyMask | 0x20007800,
   1836   NEONCopyDupGeneralMask = NEONCopyDupElementMask,
   1837   NEONCopyUmovMask = NEONCopyMask | 0x20007800,
   1838   NEONCopySmovMask = NEONCopyMask | 0x20007800,
   1839   NEON_INS_ELEMENT = NEONCopyFixed | 0x60000000,
   1840   NEON_INS_GENERAL = NEONCopyFixed | 0x40001800,
   1841   NEON_DUP_ELEMENT = NEONCopyFixed | 0x00000000,
   1842   NEON_DUP_GENERAL = NEONCopyFixed | 0x00000800,
   1843   NEON_SMOV = NEONCopyFixed | 0x00002800,
   1844   NEON_UMOV = NEONCopyFixed | 0x00003800
   1845 };
   1846 
   1847 // NEON scalar instructions with indexed element operand.
   1848 enum NEONScalarByIndexedElementOp {
   1849   NEONScalarByIndexedElementFixed = 0x5F000000,
   1850   NEONScalarByIndexedElementFMask = 0xDF000400,
   1851   NEONScalarByIndexedElementMask = 0xFF00F400,
   1852   NEON_SQDMLAL_byelement_scalar = NEON_Q | NEONScalar | NEON_SQDMLAL_byelement,
   1853   NEON_SQDMLSL_byelement_scalar = NEON_Q | NEONScalar | NEON_SQDMLSL_byelement,
   1854   NEON_SQDMULL_byelement_scalar = NEON_Q | NEONScalar | NEON_SQDMULL_byelement,
   1855   NEON_SQDMULH_byelement_scalar = NEON_Q | NEONScalar | NEON_SQDMULH_byelement,
   1856   NEON_SQRDMULH_byelement_scalar =
   1857       NEON_Q | NEONScalar | NEON_SQRDMULH_byelement,
   1858 
   1859   // Floating point instructions.
   1860   NEONScalarByIndexedElementFPFixed =
   1861       NEONScalarByIndexedElementFixed | 0x00800000,
   1862   NEONScalarByIndexedElementFPMask =
   1863       NEONScalarByIndexedElementMask | 0x00800000,
   1864   NEON_FMLA_byelement_scalar = NEON_Q | NEONScalar | NEON_FMLA_byelement,
   1865   NEON_FMLS_byelement_scalar = NEON_Q | NEONScalar | NEON_FMLS_byelement,
   1866   NEON_FMUL_byelement_scalar = NEON_Q | NEONScalar | NEON_FMUL_byelement,
   1867   NEON_FMULX_byelement_scalar = NEON_Q | NEONScalar | NEON_FMULX_byelement
   1868 };
   1869 
   1870 // NEON shift immediate.
   1871 enum NEONShiftImmediateOp {
   1872   NEONShiftImmediateFixed = 0x0F000400,
   1873   NEONShiftImmediateFMask = 0x9F800400,
   1874   NEONShiftImmediateMask = 0xBF80FC00,
   1875   NEONShiftImmediateUBit = 0x20000000,
   1876   NEON_SHL = NEONShiftImmediateFixed | 0x00005000,
   1877   NEON_SSHLL = NEONShiftImmediateFixed | 0x0000A000,
   1878   NEON_USHLL = NEONShiftImmediateFixed | 0x2000A000,
   1879   NEON_SLI = NEONShiftImmediateFixed | 0x20005000,
   1880   NEON_SRI = NEONShiftImmediateFixed | 0x20004000,
   1881   NEON_SHRN = NEONShiftImmediateFixed | 0x00008000,
   1882   NEON_RSHRN = NEONShiftImmediateFixed | 0x00008800,
   1883   NEON_UQSHRN = NEONShiftImmediateFixed | 0x20009000,
   1884   NEON_UQRSHRN = NEONShiftImmediateFixed | 0x20009800,
   1885   NEON_SQSHRN = NEONShiftImmediateFixed | 0x00009000,
   1886   NEON_SQRSHRN = NEONShiftImmediateFixed | 0x00009800,
   1887   NEON_SQSHRUN = NEONShiftImmediateFixed | 0x20008000,
   1888   NEON_SQRSHRUN = NEONShiftImmediateFixed | 0x20008800,
   1889   NEON_SSHR = NEONShiftImmediateFixed | 0x00000000,
   1890   NEON_SRSHR = NEONShiftImmediateFixed | 0x00002000,
   1891   NEON_USHR = NEONShiftImmediateFixed | 0x20000000,
   1892   NEON_URSHR = NEONShiftImmediateFixed | 0x20002000,
   1893   NEON_SSRA = NEONShiftImmediateFixed | 0x00001000,
   1894   NEON_SRSRA = NEONShiftImmediateFixed | 0x00003000,
   1895   NEON_USRA = NEONShiftImmediateFixed | 0x20001000,
   1896   NEON_URSRA = NEONShiftImmediateFixed | 0x20003000,
   1897   NEON_SQSHLU = NEONShiftImmediateFixed | 0x20006000,
   1898   NEON_SCVTF_imm = NEONShiftImmediateFixed | 0x0000E000,
   1899   NEON_UCVTF_imm = NEONShiftImmediateFixed | 0x2000E000,
   1900   NEON_FCVTZS_imm = NEONShiftImmediateFixed | 0x0000F800,
   1901   NEON_FCVTZU_imm = NEONShiftImmediateFixed | 0x2000F800,
   1902   NEON_SQSHL_imm = NEONShiftImmediateFixed | 0x00007000,
   1903   NEON_UQSHL_imm = NEONShiftImmediateFixed | 0x20007000
   1904 };
   1905 
   1906 // NEON scalar register copy.
   1907 enum NEONScalarCopyOp {
   1908   NEONScalarCopyFixed = 0x5E000400,
   1909   NEONScalarCopyFMask = 0xDFE08400,
   1910   NEONScalarCopyMask = 0xFFE0FC00,
   1911   NEON_DUP_ELEMENT_scalar = NEON_Q | NEONScalar | NEON_DUP_ELEMENT
   1912 };
   1913 
   1914 // NEON scalar pairwise instructions.
   1915 enum NEONScalarPairwiseOp {
   1916   NEONScalarPairwiseFixed = 0x5E300800,
   1917   NEONScalarPairwiseFMask = 0xDF3E0C00,
   1918   NEONScalarPairwiseMask = 0xFFB1F800,
   1919   NEON_ADDP_scalar = NEONScalarPairwiseFixed | 0x0081B000,
   1920   NEON_FMAXNMP_scalar = NEONScalarPairwiseFixed | 0x2000C000,
   1921   NEON_FMINNMP_scalar = NEONScalarPairwiseFixed | 0x2080C000,
   1922   NEON_FADDP_scalar = NEONScalarPairwiseFixed | 0x2000D000,
   1923   NEON_FMAXP_scalar = NEONScalarPairwiseFixed | 0x2000F000,
   1924   NEON_FMINP_scalar = NEONScalarPairwiseFixed | 0x2080F000
   1925 };
   1926 
   1927 // NEON scalar shift immediate.
   1928 enum NEONScalarShiftImmediateOp {
   1929   NEONScalarShiftImmediateFixed = 0x5F000400,
   1930   NEONScalarShiftImmediateFMask = 0xDF800400,
   1931   NEONScalarShiftImmediateMask = 0xFF80FC00,
   1932   NEON_SHL_scalar = NEON_Q | NEONScalar | NEON_SHL,
   1933   NEON_SLI_scalar = NEON_Q | NEONScalar | NEON_SLI,
   1934   NEON_SRI_scalar = NEON_Q | NEONScalar | NEON_SRI,
   1935   NEON_SSHR_scalar = NEON_Q | NEONScalar | NEON_SSHR,
   1936   NEON_USHR_scalar = NEON_Q | NEONScalar | NEON_USHR,
   1937   NEON_SRSHR_scalar = NEON_Q | NEONScalar | NEON_SRSHR,
   1938   NEON_URSHR_scalar = NEON_Q | NEONScalar | NEON_URSHR,
   1939   NEON_SSRA_scalar = NEON_Q | NEONScalar | NEON_SSRA,
   1940   NEON_USRA_scalar = NEON_Q | NEONScalar | NEON_USRA,
   1941   NEON_SRSRA_scalar = NEON_Q | NEONScalar | NEON_SRSRA,
   1942   NEON_URSRA_scalar = NEON_Q | NEONScalar | NEON_URSRA,
   1943   NEON_UQSHRN_scalar = NEON_Q | NEONScalar | NEON_UQSHRN,
   1944   NEON_UQRSHRN_scalar = NEON_Q | NEONScalar | NEON_UQRSHRN,
   1945   NEON_SQSHRN_scalar = NEON_Q | NEONScalar | NEON_SQSHRN,
   1946   NEON_SQRSHRN_scalar = NEON_Q | NEONScalar | NEON_SQRSHRN,
   1947   NEON_SQSHRUN_scalar = NEON_Q | NEONScalar | NEON_SQSHRUN,
   1948   NEON_SQRSHRUN_scalar = NEON_Q | NEONScalar | NEON_SQRSHRUN,
   1949   NEON_SQSHLU_scalar = NEON_Q | NEONScalar | NEON_SQSHLU,
   1950   NEON_SQSHL_imm_scalar = NEON_Q | NEONScalar | NEON_SQSHL_imm,
   1951   NEON_UQSHL_imm_scalar = NEON_Q | NEONScalar | NEON_UQSHL_imm,
   1952   NEON_SCVTF_imm_scalar = NEON_Q | NEONScalar | NEON_SCVTF_imm,
   1953   NEON_UCVTF_imm_scalar = NEON_Q | NEONScalar | NEON_UCVTF_imm,
   1954   NEON_FCVTZS_imm_scalar = NEON_Q | NEONScalar | NEON_FCVTZS_imm,
   1955   NEON_FCVTZU_imm_scalar = NEON_Q | NEONScalar | NEON_FCVTZU_imm
   1956 };
   1957 
   1958 // NEON table.
   1959 enum NEONTableOp {
   1960   NEONTableFixed = 0x0E000000,
   1961   NEONTableFMask = 0xBF208C00,
   1962   NEONTableExt = 0x00001000,
   1963   NEONTableMask = 0xBF20FC00,
   1964   NEON_TBL_1v = NEONTableFixed | 0x00000000,
   1965   NEON_TBL_2v = NEONTableFixed | 0x00002000,
   1966   NEON_TBL_3v = NEONTableFixed | 0x00004000,
   1967   NEON_TBL_4v = NEONTableFixed | 0x00006000,
   1968   NEON_TBX_1v = NEON_TBL_1v | NEONTableExt,
   1969   NEON_TBX_2v = NEON_TBL_2v | NEONTableExt,
   1970   NEON_TBX_3v = NEON_TBL_3v | NEONTableExt,
   1971   NEON_TBX_4v = NEON_TBL_4v | NEONTableExt
   1972 };
   1973 
   1974 // NEON perm.
   1975 enum NEONPermOp {
   1976   NEONPermFixed = 0x0E000800,
   1977   NEONPermFMask = 0xBF208C00,
   1978   NEONPermMask = 0x3F20FC00,
   1979   NEON_UZP1 = NEONPermFixed | 0x00001000,
   1980   NEON_TRN1 = NEONPermFixed | 0x00002000,
   1981   NEON_ZIP1 = NEONPermFixed | 0x00003000,
   1982   NEON_UZP2 = NEONPermFixed | 0x00005000,
   1983   NEON_TRN2 = NEONPermFixed | 0x00006000,
   1984   NEON_ZIP2 = NEONPermFixed | 0x00007000
   1985 };
   1986 
   1987 // NEON scalar instructions with two register operands.
   1988 enum NEONScalar2RegMiscOp {
   1989   NEONScalar2RegMiscFixed = 0x5E200800,
   1990   NEONScalar2RegMiscFMask = 0xDF3E0C00,
   1991   NEONScalar2RegMiscMask = NEON_Q | NEONScalar | NEON2RegMiscMask,
   1992   NEON_CMGT_zero_scalar = NEON_Q | NEONScalar | NEON_CMGT_zero,
   1993   NEON_CMEQ_zero_scalar = NEON_Q | NEONScalar | NEON_CMEQ_zero,
   1994   NEON_CMLT_zero_scalar = NEON_Q | NEONScalar | NEON_CMLT_zero,
   1995   NEON_CMGE_zero_scalar = NEON_Q | NEONScalar | NEON_CMGE_zero,
   1996   NEON_CMLE_zero_scalar = NEON_Q | NEONScalar | NEON_CMLE_zero,
   1997   NEON_ABS_scalar = NEON_Q | NEONScalar | NEON_ABS,
   1998   NEON_SQABS_scalar = NEON_Q | NEONScalar | NEON_SQABS,
   1999   NEON_NEG_scalar = NEON_Q | NEONScalar | NEON_NEG,
   2000   NEON_SQNEG_scalar = NEON_Q | NEONScalar | NEON_SQNEG,
   2001   NEON_SQXTN_scalar = NEON_Q | NEONScalar | NEON_SQXTN,
   2002   NEON_UQXTN_scalar = NEON_Q | NEONScalar | NEON_UQXTN,
   2003   NEON_SQXTUN_scalar = NEON_Q | NEONScalar | NEON_SQXTUN,
   2004   NEON_SUQADD_scalar = NEON_Q | NEONScalar | NEON_SUQADD,
   2005   NEON_USQADD_scalar = NEON_Q | NEONScalar | NEON_USQADD,
   2006 
   2007   NEONScalar2RegMiscOpcode = NEON2RegMiscOpcode,
   2008   NEON_NEG_scalar_opcode = NEON_NEG_scalar & NEONScalar2RegMiscOpcode,
   2009 
   2010   NEONScalar2RegMiscFPMask = NEONScalar2RegMiscMask | 0x00800000,
   2011   NEON_FRSQRTE_scalar = NEON_Q | NEONScalar | NEON_FRSQRTE,
   2012   NEON_FRECPE_scalar = NEON_Q | NEONScalar | NEON_FRECPE,
   2013   NEON_SCVTF_scalar = NEON_Q | NEONScalar | NEON_SCVTF,
   2014   NEON_UCVTF_scalar = NEON_Q | NEONScalar | NEON_UCVTF,
   2015   NEON_FCMGT_zero_scalar = NEON_Q | NEONScalar | NEON_FCMGT_zero,
   2016   NEON_FCMEQ_zero_scalar = NEON_Q | NEONScalar | NEON_FCMEQ_zero,
   2017   NEON_FCMLT_zero_scalar = NEON_Q | NEONScalar | NEON_FCMLT_zero,
   2018   NEON_FCMGE_zero_scalar = NEON_Q | NEONScalar | NEON_FCMGE_zero,
   2019   NEON_FCMLE_zero_scalar = NEON_Q | NEONScalar | NEON_FCMLE_zero,
   2020   NEON_FRECPX_scalar = NEONScalar2RegMiscFixed | 0x0081F000,
   2021   NEON_FCVTNS_scalar = NEON_Q | NEONScalar | NEON_FCVTNS,
   2022   NEON_FCVTNU_scalar = NEON_Q | NEONScalar | NEON_FCVTNU,
   2023   NEON_FCVTPS_scalar = NEON_Q | NEONScalar | NEON_FCVTPS,
   2024   NEON_FCVTPU_scalar = NEON_Q | NEONScalar | NEON_FCVTPU,
   2025   NEON_FCVTMS_scalar = NEON_Q | NEONScalar | NEON_FCVTMS,
   2026   NEON_FCVTMU_scalar = NEON_Q | NEONScalar | NEON_FCVTMU,
   2027   NEON_FCVTZS_scalar = NEON_Q | NEONScalar | NEON_FCVTZS,
   2028   NEON_FCVTZU_scalar = NEON_Q | NEONScalar | NEON_FCVTZU,
   2029   NEON_FCVTAS_scalar = NEON_Q | NEONScalar | NEON_FCVTAS,
   2030   NEON_FCVTAU_scalar = NEON_Q | NEONScalar | NEON_FCVTAU,
   2031   NEON_FCVTXN_scalar = NEON_Q | NEONScalar | NEON_FCVTXN
   2032 };
   2033 
   2034 // NEON scalar instructions with three same-type operands.
   2035 enum NEONScalar3SameOp {
   2036   NEONScalar3SameFixed = 0x5E200400,
   2037   NEONScalar3SameFMask = 0xDF200400,
   2038   NEONScalar3SameMask = 0xFF20FC00,
   2039   NEON_ADD_scalar = NEON_Q | NEONScalar | NEON_ADD,
   2040   NEON_CMEQ_scalar = NEON_Q | NEONScalar | NEON_CMEQ,
   2041   NEON_CMGE_scalar = NEON_Q | NEONScalar | NEON_CMGE,
   2042   NEON_CMGT_scalar = NEON_Q | NEONScalar | NEON_CMGT,
   2043   NEON_CMHI_scalar = NEON_Q | NEONScalar | NEON_CMHI,
   2044   NEON_CMHS_scalar = NEON_Q | NEONScalar | NEON_CMHS,
   2045   NEON_CMTST_scalar = NEON_Q | NEONScalar | NEON_CMTST,
   2046   NEON_SUB_scalar = NEON_Q | NEONScalar | NEON_SUB,
   2047   NEON_UQADD_scalar = NEON_Q | NEONScalar | NEON_UQADD,
   2048   NEON_SQADD_scalar = NEON_Q | NEONScalar | NEON_SQADD,
   2049   NEON_UQSUB_scalar = NEON_Q | NEONScalar | NEON_UQSUB,
   2050   NEON_SQSUB_scalar = NEON_Q | NEONScalar | NEON_SQSUB,
   2051   NEON_USHL_scalar = NEON_Q | NEONScalar | NEON_USHL,
   2052   NEON_SSHL_scalar = NEON_Q | NEONScalar | NEON_SSHL,
   2053   NEON_UQSHL_scalar = NEON_Q | NEONScalar | NEON_UQSHL,
   2054   NEON_SQSHL_scalar = NEON_Q | NEONScalar | NEON_SQSHL,
   2055   NEON_URSHL_scalar = NEON_Q | NEONScalar | NEON_URSHL,
   2056   NEON_SRSHL_scalar = NEON_Q | NEONScalar | NEON_SRSHL,
   2057   NEON_UQRSHL_scalar = NEON_Q | NEONScalar | NEON_UQRSHL,
   2058   NEON_SQRSHL_scalar = NEON_Q | NEONScalar | NEON_SQRSHL,
   2059   NEON_SQDMULH_scalar = NEON_Q | NEONScalar | NEON_SQDMULH,
   2060   NEON_SQRDMULH_scalar = NEON_Q | NEONScalar | NEON_SQRDMULH,
   2061 
   2062   // NEON floating point scalar instructions with three same-type operands.
   2063   NEONScalar3SameFPFixed = NEONScalar3SameFixed | 0x0000C000,
   2064   NEONScalar3SameFPFMask = NEONScalar3SameFMask | 0x0000C000,
   2065   NEONScalar3SameFPMask = NEONScalar3SameMask | 0x00800000,
   2066   NEON_FACGE_scalar = NEON_Q | NEONScalar | NEON_FACGE,
   2067   NEON_FACGT_scalar = NEON_Q | NEONScalar | NEON_FACGT,
   2068   NEON_FCMEQ_scalar = NEON_Q | NEONScalar | NEON_FCMEQ,
   2069   NEON_FCMGE_scalar = NEON_Q | NEONScalar | NEON_FCMGE,
   2070   NEON_FCMGT_scalar = NEON_Q | NEONScalar | NEON_FCMGT,
   2071   NEON_FMULX_scalar = NEON_Q | NEONScalar | NEON_FMULX,
   2072   NEON_FRECPS_scalar = NEON_Q | NEONScalar | NEON_FRECPS,
   2073   NEON_FRSQRTS_scalar = NEON_Q | NEONScalar | NEON_FRSQRTS,
   2074   NEON_FABD_scalar = NEON_Q | NEONScalar | NEON_FABD
   2075 };
   2076 
   2077 // NEON scalar instructions with three different-type operands.
   2078 enum NEONScalar3DiffOp {
   2079   NEONScalar3DiffFixed = 0x5E200000,
   2080   NEONScalar3DiffFMask = 0xDF200C00,
   2081   NEONScalar3DiffMask = NEON_Q | NEONScalar | NEON3DifferentMask,
   2082   NEON_SQDMLAL_scalar = NEON_Q | NEONScalar | NEON_SQDMLAL,
   2083   NEON_SQDMLSL_scalar = NEON_Q | NEONScalar | NEON_SQDMLSL,
   2084   NEON_SQDMULL_scalar = NEON_Q | NEONScalar | NEON_SQDMULL
   2085 };
   2086 
   2087 // Unimplemented and unallocated instructions. These are defined to make fixed
   2088 // bit assertion easier.
   2089 enum UnimplementedOp {
   2090   UnimplementedFixed = 0x00000000,
   2091   UnimplementedFMask = 0x00000000
   2092 };
   2093 
   2094 enum UnallocatedOp {
   2095   UnallocatedFixed = 0x00000000,
   2096   UnallocatedFMask = 0x00000000
   2097 };
   2098 
   2099 }  // namespace internal
   2100 }  // namespace v8
   2101 
   2102 #endif  // V8_ARM64_CONSTANTS_ARM64_H_
   2103