| /external/u-boot/board/freescale/t1040qds/ |
| t1040qds.c | 226 u32 pllcr0 = srds_regs->bank[i].pllcr0; local
227 u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
|
| /external/u-boot/board/freescale/b4860qds/ |
| b4860qds.c | 632 u32 fcap, dcbias, bcap, pllcr1, pllcr0; local
637 clrbits_be32(&srds_regs->bank[pll_num].pllcr0,
645 setbits_be32(&srds_regs->bank[pll_num].pllcr0,
663 clrbits_be32(&srds_regs->bank[pll_num].pllcr0,
671 setbits_be32(&srds_regs->bank[pll_num].pllcr0,
697 clrbits_be32(&srds_regs->bank[pll_num].pllcr0,
699 pllcr0 = (in_be32
700 (&srds_regs->bank[pll_num].pllcr0)|
702 out_be32(&srds_regs->bank[pll_num].pllcr0,
703 pllcr0);
1179 u32 pllcr0 = srds_regs->bank[i].pllcr0; local
[all...] |
| /external/u-boot/board/freescale/t4qds/ |
| t4240qds.c | 643 u32 pllcr0, expected; local
667 pllcr0 = srds_regs->bank[0].pllcr0;
668 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
|
| /external/u-boot/arch/arm/include/asm/arch-fsl-layerscape/ |
| immap_lsch3.h | 397 u32 pllcr0; /* PLL Control Register 0 */ member in struct:ccsr_serdes::__anon46567
|
| immap_lsch2.h | 550 u32 pllcr0; /* PLL Control Register 0 */ member in struct:ccsr_serdes::__anon46556
|
| /external/u-boot/arch/arm/include/asm/arch-ls102xa/ |
| immap_ls102xa.h | 343 u32 pllcr0; /* PLL Control Register 0 */ member in struct:ccsr_serdes::__anon46574
|
| /external/u-boot/arch/powerpc/include/asm/ |
| immap_85xx.h | 2542 u32 pllcr0; \/* PLL Control Register 0 *\/ member in struct:serdes_corenet::__anon46991
2626 u32 pllcr0; \/* PLL Control Register 0 *\/ member in struct:serdes_corenet::__anon46994
[all...] |
