1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2013 Freescale Semiconductor, Inc. 4 */ 5 6 #include <common.h> 7 #include <command.h> 8 #include <i2c.h> 9 #include <netdev.h> 10 #include <linux/compiler.h> 11 #include <asm/mmu.h> 12 #include <asm/processor.h> 13 #include <asm/cache.h> 14 #include <asm/immap_85xx.h> 15 #include <asm/fsl_law.h> 16 #include <asm/fsl_serdes.h> 17 #include <asm/fsl_liodn.h> 18 #include <fm_eth.h> 19 #include <hwconfig.h> 20 21 #include "../common/sleep.h" 22 #include "../common/qixis.h" 23 #include "t1040qds.h" 24 #include "t1040qds_qixis.h" 25 26 DECLARE_GLOBAL_DATA_PTR; 27 28 int checkboard(void) 29 { 30 char buf[64]; 31 u8 sw; 32 struct cpu_type *cpu = gd->arch.cpu; 33 static const char *const freq[] = {"100", "125", "156.25", "161.13", 34 "122.88", "122.88", "122.88"}; 35 int clock; 36 37 printf("Board: %sQDS, ", cpu->name); 38 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ", 39 QIXIS_READ(id), QIXIS_READ(arch)); 40 41 sw = QIXIS_READ(brdcfg[0]); 42 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; 43 44 if (sw < 0x8) 45 printf("vBank: %d\n", sw); 46 else if (sw == 0x8) 47 puts("PromJet\n"); 48 else if (sw == 0x9) 49 puts("NAND\n"); 50 else if (sw == 0x15) 51 printf("IFCCard\n"); 52 else 53 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); 54 55 printf("FPGA: v%d (%s), build %d", 56 (int)QIXIS_READ(scver), qixis_read_tag(buf), 57 (int)qixis_read_minor()); 58 /* the timestamp string contains "\n" at the end */ 59 printf(" on %s", qixis_read_time(buf)); 60 61 /* 62 * Display the actual SERDES reference clocks as configured by the 63 * dip switches on the board. Note that the SWx registers could 64 * technically be set to force the reference clocks to match the 65 * values that the SERDES expects (or vice versa). For now, however, 66 * we just display both values and hope the user notices when they 67 * don't match. 68 */ 69 puts("SERDES Reference: "); 70 sw = QIXIS_READ(brdcfg[2]); 71 clock = (sw >> 6) & 3; 72 printf("Clock1=%sMHz ", freq[clock]); 73 clock = (sw >> 4) & 3; 74 printf("Clock2=%sMHz\n", freq[clock]); 75 76 return 0; 77 } 78 79 int select_i2c_ch_pca9547(u8 ch) 80 { 81 int ret; 82 83 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); 84 if (ret) { 85 puts("PCA: failed to select proper channel\n"); 86 return ret; 87 } 88 89 return 0; 90 } 91 92 static void qe_board_setup(void) 93 { 94 u8 brdcfg15, brdcfg9; 95 96 if (hwconfig("qe") && hwconfig("tdm")) { 97 brdcfg15 = QIXIS_READ(brdcfg[15]); 98 /* 99 * TDMRiser uses QE-TDM 100 * Route QE_TDM signals to TDM Riser slot 101 */ 102 QIXIS_WRITE(brdcfg[15], brdcfg15 | 7); 103 } else if (hwconfig("qe") && hwconfig("uart")) { 104 brdcfg15 = QIXIS_READ(brdcfg[15]); 105 brdcfg9 = QIXIS_READ(brdcfg[9]); 106 /* 107 * Route QE_TDM signals to UCC 108 * ProfiBus controlled by UCC3 109 */ 110 brdcfg15 &= 0xfc; 111 QIXIS_WRITE(brdcfg[15], brdcfg15 | 2); 112 QIXIS_WRITE(brdcfg[9], brdcfg9 | 4); 113 } 114 } 115 116 int board_early_init_f(void) 117 { 118 #if defined(CONFIG_DEEP_SLEEP) 119 if (is_warm_boot()) 120 fsl_dp_disable_console(); 121 #endif 122 123 return 0; 124 } 125 126 int board_early_init_r(void) 127 { 128 #ifdef CONFIG_SYS_FLASH_BASE 129 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; 130 int flash_esel = find_tlb_idx((void *)flashbase, 1); 131 132 /* 133 * Remap Boot flash + PROMJET region to caching-inhibited 134 * so that flash can be erased properly. 135 */ 136 137 /* Flush d-cache and invalidate i-cache of any FLASH data */ 138 flush_dcache(); 139 invalidate_icache(); 140 141 if (flash_esel == -1) { 142 /* very unlikely unless something is messed up */ 143 puts("Error: Could not find TLB for FLASH BASE\n"); 144 flash_esel = 2; /* give our best effort to continue */ 145 } else { 146 /* invalidate existing TLB entry for flash + promjet */ 147 disable_tlb(flash_esel); 148 } 149 150 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, 151 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 152 0, flash_esel, BOOKE_PAGESZ_256M, 1); 153 #endif 154 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); 155 156 return 0; 157 } 158 159 unsigned long get_board_sys_clk(void) 160 { 161 u8 sysclk_conf = QIXIS_READ(brdcfg[1]); 162 163 switch (sysclk_conf & 0x0F) { 164 case QIXIS_SYSCLK_64: 165 return 64000000; 166 case QIXIS_SYSCLK_83: 167 return 83333333; 168 case QIXIS_SYSCLK_100: 169 return 100000000; 170 case QIXIS_SYSCLK_125: 171 return 125000000; 172 case QIXIS_SYSCLK_133: 173 return 133333333; 174 case QIXIS_SYSCLK_150: 175 return 150000000; 176 case QIXIS_SYSCLK_160: 177 return 160000000; 178 case QIXIS_SYSCLK_166: 179 return 166666666; 180 } 181 return 66666666; 182 } 183 184 unsigned long get_board_ddr_clk(void) 185 { 186 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); 187 188 switch ((ddrclk_conf & 0x30) >> 4) { 189 case QIXIS_DDRCLK_100: 190 return 100000000; 191 case QIXIS_DDRCLK_125: 192 return 125000000; 193 case QIXIS_DDRCLK_133: 194 return 133333333; 195 } 196 return 66666666; 197 } 198 199 #define NUM_SRDS_BANKS 2 200 int misc_init_r(void) 201 { 202 u8 sw; 203 serdes_corenet_t *srds_regs = 204 (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; 205 u32 actual[NUM_SRDS_BANKS] = { 0 }; 206 int i; 207 208 sw = QIXIS_READ(brdcfg[2]); 209 for (i = 0; i < NUM_SRDS_BANKS; i++) { 210 unsigned int clock = (sw >> (6 - 2 * i)) & 3; 211 switch (clock) { 212 case 0: 213 actual[i] = SRDS_PLLCR0_RFCK_SEL_100; 214 break; 215 case 1: 216 actual[i] = SRDS_PLLCR0_RFCK_SEL_125; 217 break; 218 case 2: 219 actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25; 220 break; 221 } 222 } 223 224 puts("SerDes1"); 225 for (i = 0; i < NUM_SRDS_BANKS; i++) { 226 u32 pllcr0 = srds_regs->bank[i].pllcr0; 227 u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK; 228 if (expected != actual[i]) { 229 printf("expects ref clk%d %sMHz, but actual is %sMHz\n", 230 i + 1, serdes_clock_to_string(expected), 231 serdes_clock_to_string(actual[i])); 232 } 233 } 234 235 qe_board_setup(); 236 237 return 0; 238 } 239 240 int ft_board_setup(void *blob, bd_t *bd) 241 { 242 phys_addr_t base; 243 phys_size_t size; 244 245 ft_cpu_setup(blob, bd); 246 247 base = env_get_bootm_low(); 248 size = env_get_bootm_size(); 249 250 fdt_fixup_memory(blob, (u64)base, (u64)size); 251 252 #ifdef CONFIG_PCI 253 pci_of_setup(blob, bd); 254 #endif 255 256 fdt_fixup_liodn(blob); 257 258 #ifdef CONFIG_HAS_FSL_DR_USB 259 fsl_fdt_fixup_dr_usb(blob, bd); 260 #endif 261 262 #ifdef CONFIG_SYS_DPAA_FMAN 263 fdt_fixup_fman_ethernet(blob); 264 fdt_fixup_board_enet(blob); 265 #endif 266 267 return 0; 268 } 269 270 void qixis_dump_switch(void) 271 { 272 int i, nr_of_cfgsw; 273 274 QIXIS_WRITE(cms[0], 0x00); 275 nr_of_cfgsw = QIXIS_READ(cms[1]); 276 277 puts("DIP switch settings dump:\n"); 278 for (i = 1; i <= nr_of_cfgsw; i++) { 279 QIXIS_WRITE(cms[0], i); 280 printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1])); 281 } 282 } 283 284 int board_need_mem_reset(void) 285 { 286 return 1; 287 } 288
