| /external/u-boot/board/freescale/b4860qds/ |
| b4860qds.c | 596 static int calibrate_pll(serdes_corenet_t *srds_regs, int pll_num)
604 clrbits_be32(&srds_regs->bank[pll_num].rstctl,
607 clrbits_be32(&srds_regs->bank[pll_num].rstctl,
610 setbits_be32(&srds_regs->bank[pll_num].rstctl,
612 setbits_be32(&srds_regs->bank[pll_num].rstctl,
619 rst_err = in_be32(&srds_regs->bank[pll_num].rstctl) &
629 static int check_pll_locks(serdes_corenet_t *srds_regs, int pll_num)
634 if (calibrate_pll(srds_regs, pll_num)) {
637 clrbits_be32(&srds_regs->bank[pll_num].pllcr0,
639 fcap = in_be32(&srds_regs->bank[pll_num].pllsr2)
775 serdes_corenet_t *srds_regs = local
1158 serdes_corenet_t *srds_regs = local
[all...] |
| /external/u-boot/arch/powerpc/cpu/mpc85xx/ |
| fsl_corenet2_serdes.c | 207 serdes_corenet_t __iomem *srds_regs = (void *)sd_addr; local
231 pll_status = in_be32(&srds_regs->bank[pll_num].pllcr0);
266 pll_cr1 = in_be32(&srds_regs->bank[pll_num].pllcr1);
269 out_be32(&srds_regs->bank[pll_num].pllcr1,
275 pll_cr0 = in_be32(&srds_regs->bank[pll_num].pllcr0);
276 out_be32(&srds_regs->bank[pll_num].pllcr0,
283 pll_cr1 = in_be32(&srds_regs->bank[pll_num].pllcr1);
285 out_be32(&srds_regs->bank[pll_num].pllcr1,
293 pll_sr2 = in_be32(&srds_regs->bank[pll_num].pllsr2);
302 pll_cr0 = in_be32(&srds_regs->bank[pll_num].pllcr0)
[all...] |
| fsl_corenet_serdes.c | 464 serdes_corenet_t *srds_regs = local
472 rstctl = in_be32(&srds_regs->bank[bank].rstctl);
492 serdes_corenet_t *srds_regs; local
526 srds_regs = (void *)(CONFIG_SYS_FSL_CORENET_SERDES_ADDR);
644 setbits_be32(&srds_regs->bank[bank].rstctl,
647 setbits_be32(&srds_regs->bank[bank].rstctl,
677 if (in_be32(&srds_regs->lane[idx].gcr0) & SRDS_GCR0_UOTHL) {
679 setbits_be32(&srds_regs->bank[bank].pllcr0,
735 out_be32(&srds_regs->lane[idx].ttlcr0,
818 p4080_erratum_serdes_a005(srds_regs, cfg)
[all...] |
| cmd_errata.c | 85 const serdes_corenet_t __iomem *srds_regs = local
92 &srds_regs->lane[serdes_get_lane_idx(lane)];
|
| /external/u-boot/arch/powerpc/cpu/mpc8xxx/ |
| srio.c | 73 serdes_corenet_t *srds_regs; local
81 srds_regs = (void *)(CONFIG_SYS_FSL_CORENET_SERDES_ADDR);
82 conf_lane = (in_be32((void *)&srds_regs->srdspccr0)
92 if (in_be32((void *)&srds_regs->bank[0].rstctl)
148 clrbits_be32(&srds_regs->lane[idx].gcr0,
155 in_be32(&srds_regs->lane[idx].gcr0);
165 setbits_be32(&srds_regs->lane[idx].gcr0,
172 in_be32(&srds_regs->lane[idx].gcr0);
|
| /external/u-boot/board/freescale/corenet_ds/ |
| corenet_ds.c | 133 serdes_corenet_t *srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; local
174 u32 expected = srds_regs->bank[i].pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
|
| /external/u-boot/board/freescale/t1040qds/ |
| t1040qds.c | 203 serdes_corenet_t *srds_regs = local
226 u32 pllcr0 = srds_regs->bank[i].pllcr0;
|
| /external/u-boot/board/freescale/t208xqds/ |
| eth_t208xqds.c | 207 serdes_corenet_t *srds_regs = local
209 u32 srds1_pccr1 = in_be32(&srds_regs->srdspccr1);
228 out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
240 out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
252 out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
265 out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
287 out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
299 out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
|
| /external/u-boot/board/freescale/t4qds/ |
| t4240qds.c | 641 serdes_corenet_t *srds_regs; local
666 srds_regs = srds_base + i * 0x1000;
667 pllcr0 = srds_regs->bank[0].pllcr0;
|
| /external/u-boot/drivers/pci/ |
| fsl_pci_init.c | 500 serdes_corenet_t *srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; local
501 temp32 = in_be32(&srds_regs->srdspccr0);
506 out_be32(&srds_regs->srdspccr0, 2 << 28);
|
