1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2009-2011 Freescale Semiconductor, Inc. 4 */ 5 6 #include <common.h> 7 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 8 #include <hwconfig.h> 9 #endif 10 #include <asm/fsl_serdes.h> 11 #include <asm/immap_85xx.h> 12 #include <asm/io.h> 13 #include <asm/processor.h> 14 #include <asm/fsl_law.h> 15 #include <linux/errno.h> 16 #include "fsl_corenet_serdes.h" 17 18 /* 19 * The work-arounds for erratum SERDES8 and SERDES-A001 are linked together. 20 * The code is already very complicated as it is, and separating the two 21 * completely would just make things worse. We try to keep them as separate 22 * as possible, but for now we require SERDES8 if SERDES_A001 is defined. 23 */ 24 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001 25 #ifndef CONFIG_SYS_P4080_ERRATUM_SERDES8 26 #error "CONFIG_SYS_P4080_ERRATUM_SERDES_A001 requires CONFIG_SYS_P4080_ERRATUM_SERDES8" 27 #endif 28 #endif 29 30 static u32 serdes_prtcl_map; 31 32 #ifdef DEBUG 33 static const char *serdes_prtcl_str[] = { 34 [NONE] = "NA", 35 [PCIE1] = "PCIE1", 36 [PCIE2] = "PCIE2", 37 [PCIE3] = "PCIE3", 38 [PCIE4] = "PCIE4", 39 [SATA1] = "SATA1", 40 [SATA2] = "SATA2", 41 [SRIO1] = "SRIO1", 42 [SRIO2] = "SRIO2", 43 [SGMII_FM1_DTSEC1] = "SGMII_FM1_DTSEC1", 44 [SGMII_FM1_DTSEC2] = "SGMII_FM1_DTSEC2", 45 [SGMII_FM1_DTSEC3] = "SGMII_FM1_DTSEC3", 46 [SGMII_FM1_DTSEC4] = "SGMII_FM1_DTSEC4", 47 [SGMII_FM1_DTSEC5] = "SGMII_FM1_DTSEC5", 48 [SGMII_FM2_DTSEC1] = "SGMII_FM2_DTSEC1", 49 [SGMII_FM2_DTSEC2] = "SGMII_FM2_DTSEC2", 50 [SGMII_FM2_DTSEC3] = "SGMII_FM2_DTSEC3", 51 [SGMII_FM2_DTSEC4] = "SGMII_FM2_DTSEC4", 52 [SGMII_FM2_DTSEC5] = "SGMII_FM2_DTSEC5", 53 [XAUI_FM1] = "XAUI_FM1", 54 [XAUI_FM2] = "XAUI_FM2", 55 [AURORA] = "DEBUG", 56 }; 57 #endif 58 59 static const struct { 60 int idx; 61 unsigned int lpd; /* RCW lane powerdown bit */ 62 int bank; 63 } lanes[SRDS_MAX_LANES] = { 64 { 0, 152, FSL_SRDS_BANK_1 }, 65 { 1, 153, FSL_SRDS_BANK_1 }, 66 { 2, 154, FSL_SRDS_BANK_1 }, 67 { 3, 155, FSL_SRDS_BANK_1 }, 68 { 4, 156, FSL_SRDS_BANK_1 }, 69 { 5, 157, FSL_SRDS_BANK_1 }, 70 { 6, 158, FSL_SRDS_BANK_1 }, 71 { 7, 159, FSL_SRDS_BANK_1 }, 72 { 8, 160, FSL_SRDS_BANK_1 }, 73 { 9, 161, FSL_SRDS_BANK_1 }, 74 { 16, 162, FSL_SRDS_BANK_2 }, 75 { 17, 163, FSL_SRDS_BANK_2 }, 76 { 18, 164, FSL_SRDS_BANK_2 }, 77 { 19, 165, FSL_SRDS_BANK_2 }, 78 #ifdef CONFIG_ARCH_P4080 79 { 20, 170, FSL_SRDS_BANK_3 }, 80 { 21, 171, FSL_SRDS_BANK_3 }, 81 { 22, 172, FSL_SRDS_BANK_3 }, 82 { 23, 173, FSL_SRDS_BANK_3 }, 83 #else 84 { 20, 166, FSL_SRDS_BANK_3 }, 85 { 21, 167, FSL_SRDS_BANK_3 }, 86 { 22, 168, FSL_SRDS_BANK_3 }, 87 { 23, 169, FSL_SRDS_BANK_3 }, 88 #endif 89 #if SRDS_MAX_BANK > 3 90 { 24, 175, FSL_SRDS_BANK_4 }, 91 { 25, 176, FSL_SRDS_BANK_4 }, 92 #endif 93 }; 94 95 int serdes_get_lane_idx(int lane) 96 { 97 return lanes[lane].idx; 98 } 99 100 int serdes_get_bank_by_lane(int lane) 101 { 102 return lanes[lane].bank; 103 } 104 105 int serdes_lane_enabled(int lane) 106 { 107 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 108 serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; 109 110 int bank = lanes[lane].bank; 111 int word = lanes[lane].lpd / 32; 112 int bit = lanes[lane].lpd % 32; 113 114 if (in_be32(®s->bank[bank].rstctl) & SRDS_RSTCTL_SDPD) 115 return 0; 116 117 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 118 /* 119 * For banks two and three, use the srds_lpd_b[] array instead of the 120 * RCW, because this array contains the real values of SRDS_LPD_B2 and 121 * SRDS_LPD_B3. 122 */ 123 if (bank > 0) 124 return !(srds_lpd_b[bank] & (8 >> (lane - (6 + 4 * bank)))); 125 #endif 126 127 return !(in_be32(&gur->rcwsr[word]) & (0x80000000 >> bit)); 128 } 129 130 int is_serdes_configured(enum srds_prtcl device) 131 { 132 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 133 134 /* Is serdes enabled at all? */ 135 if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN)) 136 return 0; 137 138 if (!(serdes_prtcl_map & (1 << NONE))) 139 fsl_serdes_init(); 140 141 return (1 << device) & serdes_prtcl_map; 142 } 143 144 static int __serdes_get_first_lane(uint32_t prtcl, enum srds_prtcl device) 145 { 146 int i; 147 148 for (i = 0; i < SRDS_MAX_LANES; i++) { 149 if (serdes_get_prtcl(prtcl, i) == device) 150 return i; 151 } 152 153 return -ENODEV; 154 } 155 156 /* 157 * Returns the SERDES lane (0..SRDS_MAX_LANES-1) that routes to the given 158 * device. This depends on the current SERDES protocol, as defined in the RCW. 159 * 160 * Returns a negative error code if SERDES is disabled or the given device is 161 * not supported in the current SERDES protocol. 162 */ 163 int serdes_get_first_lane(enum srds_prtcl device) 164 { 165 u32 prtcl; 166 const ccsr_gur_t *gur; 167 168 gur = (typeof(gur))CONFIG_SYS_MPC85xx_GUTS_ADDR; 169 170 /* Is serdes enabled at all? */ 171 if (unlikely((in_be32(&gur->rcwsr[5]) & 0x2000) == 0)) 172 return -ENODEV; 173 174 prtcl = (in_be32(&gur->rcwsr[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26; 175 176 return __serdes_get_first_lane(prtcl, device); 177 } 178 179 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9 180 /* 181 * Returns the SERDES bank (1, 2, or 3) that a given device is on for a given 182 * SERDES protocol. 183 * 184 * Returns a negative error code if the given device is not supported for the 185 * given SERDES protocol. 186 */ 187 static int serdes_get_bank_by_device(uint32_t prtcl, enum srds_prtcl device) 188 { 189 int lane; 190 191 lane = __serdes_get_first_lane(prtcl, device); 192 if (unlikely(lane < 0)) 193 return lane; 194 195 return serdes_get_bank_by_lane(lane); 196 } 197 198 static uint32_t __serdes_get_lane_count(uint32_t prtcl, enum srds_prtcl device, 199 int first) 200 { 201 int lane; 202 203 for (lane = first; lane < SRDS_MAX_LANES; lane++) { 204 if (serdes_get_prtcl(prtcl, lane) != device) 205 break; 206 } 207 208 return lane - first; 209 } 210 211 static void __serdes_reset_rx(serdes_corenet_t *regs, 212 uint32_t prtcl, 213 enum srds_prtcl device) 214 { 215 int lane, idx, first, last; 216 217 lane = __serdes_get_first_lane(prtcl, device); 218 if (unlikely(lane < 0)) 219 return; 220 first = serdes_get_lane_idx(lane); 221 last = first + __serdes_get_lane_count(prtcl, device, lane); 222 223 /* 224 * Set BnGCRy0[RRST] = 0 for each lane in the each bank that is 225 * selected as XAUI to place the lane into reset. 226 */ 227 for (idx = first; idx < last; idx++) 228 clrbits_be32(®s->lane[idx].gcr0, SRDS_GCR0_RRST); 229 230 /* Wait at least 250 ns */ 231 udelay(1); 232 233 /* 234 * Set BnGCRy0[RRST] = 1 for each lane in the each bank that is 235 * selected as XAUI to bring the lane out of reset. 236 */ 237 for (idx = first; idx < last; idx++) 238 setbits_be32(®s->lane[idx].gcr0, SRDS_GCR0_RRST); 239 } 240 241 void serdes_reset_rx(enum srds_prtcl device) 242 { 243 u32 prtcl; 244 const ccsr_gur_t *gur; 245 serdes_corenet_t *regs; 246 247 if (unlikely(device == NONE)) 248 return; 249 250 gur = (typeof(gur))CONFIG_SYS_MPC85xx_GUTS_ADDR; 251 252 /* Is serdes enabled at all? */ 253 if (unlikely((in_be32(&gur->rcwsr[5]) & 0x2000) == 0)) 254 return; 255 256 regs = (typeof(regs))CONFIG_SYS_FSL_CORENET_SERDES_ADDR; 257 prtcl = (in_be32(&gur->rcwsr[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26; 258 259 __serdes_reset_rx(regs, prtcl, device); 260 } 261 #endif 262 263 #ifndef CONFIG_SYS_DCSRBAR_PHYS 264 #define CONFIG_SYS_DCSRBAR_PHYS 0x80000000 /* Must be 1GB-aligned for rev1.0 */ 265 #define CONFIG_SYS_DCSRBAR 0x80000000 266 #define __DCSR_NOT_DEFINED_BY_CONFIG 267 #endif 268 269 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 270 /* 271 * Enable a SERDES bank that was disabled via the RCW 272 * 273 * We only call this function for SERDES8 and SERDES-A001 in cases we really 274 * want to enable the bank, whether we actually want to use the lanes or not, 275 * so make sure at least one lane is enabled. We're only enabling this one 276 * lane to satisfy errata requirements that the bank be enabled. 277 * 278 * We use a local variable instead of srds_lpd_b[] because we want drivers to 279 * think that the lanes actually are disabled. 280 */ 281 static void enable_bank(ccsr_gur_t *gur, int bank) 282 { 283 u32 rcw5; 284 u32 temp_lpd_b = srds_lpd_b[bank]; 285 286 /* 287 * If we're asked to disable all lanes, just pretend we're doing 288 * that. 289 */ 290 if (temp_lpd_b == 0xF) 291 temp_lpd_b = 0xE; 292 293 /* 294 * Enable the lanes SRDS_LPD_Bn. The RCW bits are read-only in 295 * CCSR, and read/write in DSCR. 296 */ 297 rcw5 = in_be32(gur->rcwsr + 5); 298 if (bank == FSL_SRDS_BANK_2) { 299 rcw5 &= ~FSL_CORENET_RCWSRn_SRDS_LPD_B2; 300 rcw5 |= temp_lpd_b << 26; 301 } else if (bank == FSL_SRDS_BANK_3) { 302 rcw5 &= ~FSL_CORENET_RCWSRn_SRDS_LPD_B3; 303 rcw5 |= temp_lpd_b << 18; 304 } else { 305 printf("SERDES: enable_bank: bad bank %d\n", bank + 1); 306 return; 307 } 308 309 /* See similar code in cpu/mpc85xx/cpu_init.c for an explanation 310 * of the DCSR mapping. 311 */ 312 { 313 #ifdef __DCSR_NOT_DEFINED_BY_CONFIG 314 struct law_entry law = find_law(CONFIG_SYS_DCSRBAR_PHYS); 315 int law_index; 316 if (law.index == -1) 317 law_index = set_next_law(CONFIG_SYS_DCSRBAR_PHYS, 318 LAW_SIZE_1M, LAW_TRGT_IF_DCSR); 319 else 320 set_law(law.index, CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_1M, 321 LAW_TRGT_IF_DCSR); 322 #endif 323 u32 *p = (void *)CONFIG_SYS_DCSRBAR + 0x20114; 324 out_be32(p, rcw5); 325 #ifdef __DCSR_NOT_DEFINED_BY_CONFIG 326 if (law.index == -1) 327 disable_law(law_index); 328 else 329 set_law(law.index, law.addr, law.size, law.trgt_id); 330 #endif 331 } 332 } 333 334 /* 335 * To avoid problems with clock jitter, rev 2 p4080 uses the pll from 336 * bank 3 to clock banks 2 and 3, as well as a limited selection of 337 * protocol configurations. This requires that banks 2 and 3's lanes be 338 * disabled in the RCW, and enabled with some fixup here to re-enable 339 * them, and to configure bank 2's clock parameters in bank 3's pll in 340 * cases where they differ. 341 */ 342 static void p4080_erratum_serdes8(serdes_corenet_t *regs, ccsr_gur_t *gur, 343 u32 devdisr, u32 devdisr2, int cfg) 344 { 345 int srds_ratio_b2; 346 int rfck_sel; 347 348 /* 349 * The disabled lanes of bank 2 will cause the associated 350 * logic blocks to be disabled in DEVDISR. We reverse that here. 351 * 352 * Note that normally it is not permitted to clear DEVDISR bits 353 * once the device has been disabled, but the hardware people 354 * say that this special case is OK. 355 */ 356 clrbits_be32(&gur->devdisr, devdisr); 357 clrbits_be32(&gur->devdisr2, devdisr2); 358 359 /* 360 * Some protocols require special handling. There are a few 361 * additional protocol configurations that can be used, which are 362 * not listed here. See app note 4065 for supported protocol 363 * configurations. 364 */ 365 switch (cfg) { 366 case 0x19: 367 /* 368 * Bank 2 has PCIe which wants BWSEL -- tell bank 3's PLL. 369 * SGMII on bank 3 should still be usable. 370 */ 371 setbits_be32(®s->bank[FSL_SRDS_BANK_3].pllcr1, 372 SRDS_PLLCR1_PLL_BWSEL); 373 break; 374 375 case 0x0f: 376 case 0x10: 377 /* 378 * Banks 2 (XAUI) and 3 (SGMII) have different clocking 379 * requirements in these configurations. Bank 3 cannot 380 * be used and should have its lanes (but not the bank 381 * itself) disabled in the RCW. We set up bank 3's pll 382 * for bank 2's needs here. 383 */ 384 srds_ratio_b2 = (in_be32(&gur->rcwsr[4]) >> 13) & 7; 385 386 /* Determine refclock from XAUI ratio */ 387 switch (srds_ratio_b2) { 388 case 1: /* 20:1 */ 389 rfck_sel = SRDS_PLLCR0_RFCK_SEL_156_25; 390 break; 391 case 2: /* 25:1 */ 392 rfck_sel = SRDS_PLLCR0_RFCK_SEL_125; 393 break; 394 default: 395 printf("SERDES: bad SRDS_RATIO_B2 %d\n", 396 srds_ratio_b2); 397 return; 398 } 399 400 clrsetbits_be32(®s->bank[FSL_SRDS_BANK_3].pllcr0, 401 SRDS_PLLCR0_RFCK_SEL_MASK, rfck_sel); 402 403 clrsetbits_be32(®s->bank[FSL_SRDS_BANK_3].pllcr0, 404 SRDS_PLLCR0_FRATE_SEL_MASK, 405 SRDS_PLLCR0_FRATE_SEL_6_25); 406 break; 407 } 408 409 enable_bank(gur, FSL_SRDS_BANK_3); 410 } 411 #endif 412 413 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A005 414 /* 415 * If PCIe is not selected as a protocol for any lanes driven by a given PLL, 416 * that PLL should have SRDSBnPLLCR1[PLLBW_SEL] = 0. 417 */ 418 static void p4080_erratum_serdes_a005(serdes_corenet_t *regs, unsigned int cfg) 419 { 420 enum srds_prtcl device; 421 422 switch (cfg) { 423 case 0x13: 424 case 0x16: 425 /* 426 * If SRDS_PRTCL = 0x13 or 0x16, set SRDSB1PLLCR1[PLLBW_SEL] 427 * to 0. 428 */ 429 clrbits_be32(®s->bank[FSL_SRDS_BANK_1].pllcr1, 430 SRDS_PLLCR1_PLL_BWSEL); 431 break; 432 case 0x19: 433 /* 434 * If SRDS_PRTCL = 0x19, set SRDSB1PLLCR1[PLLBW_SEL] to 0 and 435 * SRDSB3PLLCR1[PLLBW_SEL] to 1. 436 */ 437 clrbits_be32(®s->bank[FSL_SRDS_BANK_1].pllcr1, 438 SRDS_PLLCR1_PLL_BWSEL); 439 setbits_be32(®s->bank[FSL_SRDS_BANK_3].pllcr1, 440 SRDS_PLLCR1_PLL_BWSEL); 441 break; 442 } 443 444 /* 445 * Set SRDSBnPLLCR1[PLLBW_SEL] to 0 for each bank that selects XAUI 446 * before XAUI is initialized. 447 */ 448 for (device = XAUI_FM1; device <= XAUI_FM2; device++) { 449 if (is_serdes_configured(device)) { 450 int bank = serdes_get_bank_by_device(cfg, device); 451 452 clrbits_be32(®s->bank[bank].pllcr1, 453 SRDS_PLLCR1_PLL_BWSEL); 454 } 455 } 456 } 457 #endif 458 459 /* 460 * Wait for the RSTDONE bit to get set, or a one-second timeout. 461 */ 462 static void wait_for_rstdone(unsigned int bank) 463 { 464 serdes_corenet_t *srds_regs = 465 (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; 466 unsigned long long end_tick; 467 u32 rstctl; 468 469 /* wait for reset complete or 1-second timeout */ 470 end_tick = usec2ticks(1000000) + get_ticks(); 471 do { 472 rstctl = in_be32(&srds_regs->bank[bank].rstctl); 473 if (rstctl & SRDS_RSTCTL_RSTDONE) 474 break; 475 } while (end_tick > get_ticks()); 476 477 if (!(rstctl & SRDS_RSTCTL_RSTDONE)) 478 printf("SERDES: timeout resetting bank %u\n", bank + 1); 479 } 480 481 482 static void __soc_serdes_init(void) 483 { 484 /* Allow for SoC-specific initialization in <SOC>_serdes.c */ 485 }; 486 void soc_serdes_init(void) __attribute__((weak, alias("__soc_serdes_init"))); 487 488 void fsl_serdes_init(void) 489 { 490 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 491 int cfg; 492 serdes_corenet_t *srds_regs; 493 #ifdef CONFIG_ARCH_P5040 494 serdes_corenet_t *srds2_regs; 495 #endif 496 int lane, bank, idx; 497 int have_bank[SRDS_MAX_BANK] = {}; 498 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 499 u32 serdes8_devdisr = 0; 500 u32 serdes8_devdisr2 = 0; 501 char srds_lpd_opt[16]; 502 const char *srds_lpd_arg; 503 size_t arglen; 504 #endif 505 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001 506 int need_serdes_a001; /* true == need work-around for SERDES A001 */ 507 #endif 508 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 509 char buffer[HWCONFIG_BUFFER_SIZE]; 510 char *buf = NULL; 511 512 /* 513 * Extract hwconfig from environment since we have not properly setup 514 * the environment but need it for ddr config params 515 */ 516 if (env_get_f("hwconfig", buffer, sizeof(buffer)) > 0) 517 buf = buffer; 518 #endif 519 if (serdes_prtcl_map & (1 << NONE)) 520 return; 521 522 /* Is serdes enabled at all? */ 523 if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN)) 524 return; 525 526 srds_regs = (void *)(CONFIG_SYS_FSL_CORENET_SERDES_ADDR); 527 cfg = (in_be32(&gur->rcwsr[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26; 528 debug("Using SERDES configuration 0x%x, lane settings:\n", cfg); 529 530 if (!is_serdes_prtcl_valid(cfg)) { 531 printf("SERDES[PRTCL] = 0x%x is not valid\n", cfg); 532 return; 533 } 534 535 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 536 /* 537 * Display a warning if banks two and three are not disabled in the RCW, 538 * since our work-around for SERDES8 depends on these banks being 539 * disabled at power-on. 540 */ 541 #define B2_B3 (FSL_CORENET_RCWSRn_SRDS_LPD_B2 | FSL_CORENET_RCWSRn_SRDS_LPD_B3) 542 if ((in_be32(&gur->rcwsr[5]) & B2_B3) != B2_B3) { 543 printf("Warning: SERDES8 requires banks two and " 544 "three to be disabled in the RCW\n"); 545 } 546 547 /* 548 * Store the values of the fsl_srds_lpd_b2 and fsl_srds_lpd_b3 549 * hwconfig options into the srds_lpd_b[] array. See README.p4080ds 550 * for a description of these options. 551 */ 552 for (bank = 1; bank < ARRAY_SIZE(srds_lpd_b); bank++) { 553 sprintf(srds_lpd_opt, "fsl_srds_lpd_b%u", bank + 1); 554 srds_lpd_arg = 555 hwconfig_subarg_f("serdes", srds_lpd_opt, &arglen, buf); 556 if (srds_lpd_arg) 557 srds_lpd_b[bank] = 558 simple_strtoul(srds_lpd_arg, NULL, 0) & 0xf; 559 } 560 561 if ((cfg == 0xf) || (cfg == 0x10)) { 562 /* 563 * For SERDES protocols 0xF and 0x10, force bank 3 to be 564 * disabled, because it is not supported. 565 */ 566 srds_lpd_b[FSL_SRDS_BANK_3] = 0xF; 567 } 568 #endif 569 570 /* Look for banks with all lanes disabled, and power down the bank. */ 571 for (lane = 0; lane < SRDS_MAX_LANES; lane++) { 572 enum srds_prtcl lane_prtcl = serdes_get_prtcl(cfg, lane); 573 if (serdes_lane_enabled(lane)) { 574 have_bank[serdes_get_bank_by_lane(lane)] = 1; 575 serdes_prtcl_map |= (1 << lane_prtcl); 576 } 577 } 578 579 #ifdef CONFIG_ARCH_P5040 580 /* 581 * Lanes on bank 4 on P5040 are commented-out, but for some SERDES 582 * protocols, these lanes are routed to SATA. We use serdes_prtcl_map 583 * to decide whether a protocol is supported on a given lane, so SATA 584 * will be identified as not supported, and therefore not initialized. 585 * So for protocols which use SATA on bank4, we add SATA support in 586 * serdes_prtcl_map. 587 */ 588 switch (cfg) { 589 case 0x0: 590 case 0x1: 591 case 0x2: 592 case 0x3: 593 case 0x4: 594 case 0x5: 595 case 0x6: 596 case 0x7: 597 serdes_prtcl_map |= 1 << SATA1 | 1 << SATA2; 598 break; 599 default: 600 srds2_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES2_ADDR; 601 602 /* We don't need bank 4, so power it down */ 603 setbits_be32(&srds2_regs->bank[0].rstctl, SRDS_RSTCTL_SDPD); 604 } 605 #endif 606 607 soc_serdes_init(); 608 609 /* Set the first bit to indicate serdes has been initialized */ 610 serdes_prtcl_map |= (1 << NONE); 611 612 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 613 /* 614 * Bank two uses the clock from bank three, so if bank two is enabled, 615 * then bank three must also be enabled. 616 */ 617 if (have_bank[FSL_SRDS_BANK_2]) 618 have_bank[FSL_SRDS_BANK_3] = 1; 619 #endif 620 621 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001 622 /* 623 * The work-aroud for erratum SERDES-A001 is needed only if bank two 624 * is disabled and bank three is enabled. The converse is also true, 625 * but SERDES8 ensures that bank 3 is always enabled if bank 2 is 626 * enabled, so there's no point in complicating the code to handle 627 * that situation. 628 */ 629 need_serdes_a001 = 630 !have_bank[FSL_SRDS_BANK_2] && have_bank[FSL_SRDS_BANK_3]; 631 #endif 632 633 /* Power down the banks we're not interested in */ 634 for (bank = 0; bank < SRDS_MAX_BANK; bank++) { 635 if (!have_bank[bank]) { 636 printf("SERDES: bank %d disabled\n", bank + 1); 637 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001 638 /* 639 * Erratum SERDES-A001 says bank two needs to be powered 640 * down after bank three is powered up, so don't power 641 * down bank two here. 642 */ 643 if (!need_serdes_a001 || (bank != FSL_SRDS_BANK_2)) 644 setbits_be32(&srds_regs->bank[bank].rstctl, 645 SRDS_RSTCTL_SDPD); 646 #else 647 setbits_be32(&srds_regs->bank[bank].rstctl, 648 SRDS_RSTCTL_SDPD); 649 #endif 650 } 651 } 652 653 #ifdef CONFIG_SYS_FSL_ERRATUM_A004699 654 /* 655 * To avoid the situation that resulted in the P4080 erratum 656 * SERDES-8, a given SerDes bank will use the PLLs from the previous 657 * bank if one of the PLL frequencies is a multiple of the other. For 658 * instance, if bank 3 is running at 2.5GHz and bank 2 is at 1.25GHz, 659 * then bank 3 will use bank 2's PLL. P5040 Erratum A-004699 says 660 * that, in this situation, lane synchronization is not initiated. So 661 * when we detect a bank with a "borrowed" PLL, we have to manually 662 * initiate lane synchronization. 663 */ 664 for (bank = FSL_SRDS_BANK_2; bank <= FSL_SRDS_BANK_3; bank++) { 665 /* Determine the first lane for this bank */ 666 unsigned int lane; 667 668 for (lane = 0; lane < SRDS_MAX_LANES; lane++) 669 if (lanes[lane].bank == bank) 670 break; 671 idx = lanes[lane].idx; 672 673 /* 674 * Check if the PLL for the bank is borrowed. The UOTHL 675 * bit of the first lane will tell us that. 676 */ 677 if (in_be32(&srds_regs->lane[idx].gcr0) & SRDS_GCR0_UOTHL) { 678 /* Manually start lane synchronization */ 679 setbits_be32(&srds_regs->bank[bank].pllcr0, 680 SRDS_PLLCR0_PVCOCNT_EN); 681 } 682 } 683 #endif 684 685 #if defined(CONFIG_SYS_P4080_ERRATUM_SERDES8) || defined (CONFIG_SYS_P4080_ERRATUM_SERDES9) 686 for (lane = 0; lane < SRDS_MAX_LANES; lane++) { 687 enum srds_prtcl lane_prtcl; 688 689 idx = serdes_get_lane_idx(lane); 690 lane_prtcl = serdes_get_prtcl(cfg, lane); 691 692 #ifdef DEBUG 693 switch (lane) { 694 case 0: 695 puts("Bank1: "); 696 break; 697 case 10: 698 puts("\nBank2: "); 699 break; 700 case 14: 701 puts("\nBank3: "); 702 break; 703 default: 704 break; 705 } 706 707 printf("%s ", serdes_prtcl_str[lane_prtcl]); 708 #endif 709 710 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9 711 /* 712 * Set BnTTLCRy0[FLT_SEL] = 011011 and set BnTTLCRy0[31] = 1 713 * for each of the SerDes lanes selected as SGMII, XAUI, SRIO, 714 * or AURORA before the device is initialized. 715 * 716 * Note that this part of the SERDES-9 work-around is 717 * redundant if the work-around for A-4580 has already been 718 * applied via PBI. 719 */ 720 switch (lane_prtcl) { 721 case SGMII_FM1_DTSEC1: 722 case SGMII_FM1_DTSEC2: 723 case SGMII_FM1_DTSEC3: 724 case SGMII_FM1_DTSEC4: 725 case SGMII_FM2_DTSEC1: 726 case SGMII_FM2_DTSEC2: 727 case SGMII_FM2_DTSEC3: 728 case SGMII_FM2_DTSEC4: 729 case SGMII_FM2_DTSEC5: 730 case XAUI_FM1: 731 case XAUI_FM2: 732 case SRIO1: 733 case SRIO2: 734 case AURORA: 735 out_be32(&srds_regs->lane[idx].ttlcr0, 736 SRDS_TTLCR0_FLT_SEL_KFR_26 | 737 SRDS_TTLCR0_FLT_SEL_KPH_28 | 738 SRDS_TTLCR0_FLT_SEL_750PPM | 739 SRDS_TTLCR0_FREQOVD_EN); 740 break; 741 default: 742 break; 743 } 744 #endif 745 746 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 747 switch (lane_prtcl) { 748 case PCIE1: 749 case PCIE2: 750 case PCIE3: 751 serdes8_devdisr |= FSL_CORENET_DEVDISR_PCIE1 >> 752 (lane_prtcl - PCIE1); 753 break; 754 case SRIO1: 755 case SRIO2: 756 serdes8_devdisr |= FSL_CORENET_DEVDISR_SRIO1 >> 757 (lane_prtcl - SRIO1); 758 break; 759 case SGMII_FM1_DTSEC1: 760 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 | 761 FSL_CORENET_DEVDISR2_DTSEC1_1; 762 break; 763 case SGMII_FM1_DTSEC2: 764 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 | 765 FSL_CORENET_DEVDISR2_DTSEC1_2; 766 break; 767 case SGMII_FM1_DTSEC3: 768 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 | 769 FSL_CORENET_DEVDISR2_DTSEC1_3; 770 break; 771 case SGMII_FM1_DTSEC4: 772 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 | 773 FSL_CORENET_DEVDISR2_DTSEC1_4; 774 break; 775 case SGMII_FM2_DTSEC1: 776 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 | 777 FSL_CORENET_DEVDISR2_DTSEC2_1; 778 break; 779 case SGMII_FM2_DTSEC2: 780 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 | 781 FSL_CORENET_DEVDISR2_DTSEC2_2; 782 break; 783 case SGMII_FM2_DTSEC3: 784 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 | 785 FSL_CORENET_DEVDISR2_DTSEC2_3; 786 break; 787 case SGMII_FM2_DTSEC4: 788 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 | 789 FSL_CORENET_DEVDISR2_DTSEC2_4; 790 break; 791 case SGMII_FM2_DTSEC5: 792 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 | 793 FSL_CORENET_DEVDISR2_DTSEC2_5; 794 break; 795 case XAUI_FM1: 796 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 | 797 FSL_CORENET_DEVDISR2_10GEC1; 798 break; 799 case XAUI_FM2: 800 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 | 801 FSL_CORENET_DEVDISR2_10GEC2; 802 break; 803 case AURORA: 804 break; 805 default: 806 break; 807 } 808 809 #endif 810 } 811 #endif 812 813 #ifdef DEBUG 814 puts("\n"); 815 #endif 816 817 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A005 818 p4080_erratum_serdes_a005(srds_regs, cfg); 819 #endif 820 821 for (idx = 0; idx < SRDS_MAX_BANK; idx++) { 822 bank = idx; 823 824 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 825 /* 826 * Change bank init order to 0, 2, 1, so that the third bank's 827 * PLL is established before we start the second bank. The 828 * second bank uses the third bank's PLL. 829 */ 830 831 if (idx == 1) 832 bank = FSL_SRDS_BANK_3; 833 else if (idx == 2) 834 bank = FSL_SRDS_BANK_2; 835 #endif 836 837 /* Skip disabled banks */ 838 if (!have_bank[bank]) 839 continue; 840 841 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 842 if (idx == 1) { 843 /* 844 * Re-enable devices on banks two and three that were 845 * disabled by the RCW, and then enable bank three. The 846 * devices need to be enabled before either bank is 847 * powered up. 848 */ 849 p4080_erratum_serdes8(srds_regs, gur, serdes8_devdisr, 850 serdes8_devdisr2, cfg); 851 } else if (idx == 2) { 852 /* Enable bank two now that bank three is enabled. */ 853 enable_bank(gur, FSL_SRDS_BANK_2); 854 } 855 #endif 856 857 wait_for_rstdone(bank); 858 } 859 860 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001 861 if (need_serdes_a001) { 862 /* Bank 3 has been enabled, so now we can disable bank 2 */ 863 setbits_be32(&srds_regs->bank[FSL_SRDS_BANK_2].rstctl, 864 SRDS_RSTCTL_SDPD); 865 } 866 #endif 867 } 868 869 const char *serdes_clock_to_string(u32 clock) 870 { 871 switch (clock) { 872 case SRDS_PLLCR0_RFCK_SEL_100: 873 return "100"; 874 case SRDS_PLLCR0_RFCK_SEL_125: 875 return "125"; 876 case SRDS_PLLCR0_RFCK_SEL_156_25: 877 return "156.25"; 878 case SRDS_PLLCR0_RFCK_SEL_161_13: 879 return "161.1328123"; 880 default: 881 return "150"; 882 } 883 } 884 885
