1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2009-2012 Freescale Semiconductor, Inc. 4 */ 5 6 #include <common.h> 7 #include <command.h> 8 #include <i2c.h> 9 #include <netdev.h> 10 #include <linux/compiler.h> 11 #include <asm/mmu.h> 12 #include <asm/processor.h> 13 #include <asm/cache.h> 14 #include <asm/immap_85xx.h> 15 #include <asm/fsl_law.h> 16 #include <asm/fsl_serdes.h> 17 #include <asm/fsl_liodn.h> 18 #include <fm_eth.h> 19 20 #include "../common/qixis.h" 21 #include "../common/vsc3316_3308.h" 22 #include "t4qds.h" 23 #include "t4240qds_qixis.h" 24 25 DECLARE_GLOBAL_DATA_PTR; 26 27 static int8_t vsc3316_fsm1_tx[8][2] = { {0, 0}, {1, 1}, {6, 6}, {7, 7}, 28 {8, 8}, {9, 9}, {14, 14}, {15, 15} }; 29 30 static int8_t vsc3316_fsm2_tx[8][2] = { {2, 2}, {3, 3}, {4, 4}, {5, 5}, 31 {10, 10}, {11, 11}, {12, 12}, {13, 13} }; 32 33 static int8_t vsc3316_fsm1_rx[8][2] = { {2, 12}, {3, 13}, {4, 5}, {5, 4}, 34 {10, 11}, {11, 10}, {12, 2}, {13, 3} }; 35 36 static int8_t vsc3316_fsm2_rx[8][2] = { {0, 15}, {1, 14}, {6, 7}, {7, 6}, 37 {8, 9}, {9, 8}, {14, 1}, {15, 0} }; 38 39 int checkboard(void) 40 { 41 char buf[64]; 42 u8 sw; 43 struct cpu_type *cpu = gd->arch.cpu; 44 unsigned int i; 45 46 printf("Board: %sQDS, ", cpu->name); 47 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ", 48 QIXIS_READ(id), QIXIS_READ(arch)); 49 50 sw = QIXIS_READ(brdcfg[0]); 51 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; 52 53 if (sw < 0x8) 54 printf("vBank: %d\n", sw); 55 else if (sw == 0x8) 56 puts("Promjet\n"); 57 else if (sw == 0x9) 58 puts("NAND\n"); 59 else 60 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); 61 62 printf("FPGA: v%d (%s), build %d", 63 (int)QIXIS_READ(scver), qixis_read_tag(buf), 64 (int)qixis_read_minor()); 65 /* the timestamp string contains "\n" at the end */ 66 printf(" on %s", qixis_read_time(buf)); 67 68 /* 69 * Display the actual SERDES reference clocks as configured by the 70 * dip switches on the board. Note that the SWx registers could 71 * technically be set to force the reference clocks to match the 72 * values that the SERDES expects (or vice versa). For now, however, 73 * we just display both values and hope the user notices when they 74 * don't match. 75 */ 76 puts("SERDES Reference Clocks: "); 77 sw = QIXIS_READ(brdcfg[2]); 78 for (i = 0; i < MAX_SERDES; i++) { 79 static const char * const freq[] = { 80 "100", "125", "156.25", "161.1328125"}; 81 unsigned int clock = (sw >> (6 - 2 * i)) & 3; 82 83 printf("SERDES%u=%sMHz ", i+1, freq[clock]); 84 } 85 puts("\n"); 86 87 return 0; 88 } 89 90 int select_i2c_ch_pca9547(u8 ch) 91 { 92 int ret; 93 94 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); 95 if (ret) { 96 puts("PCA: failed to select proper channel\n"); 97 return ret; 98 } 99 100 return 0; 101 } 102 103 /* 104 * read_voltage from sensor on I2C bus 105 * We use average of 4 readings, waiting for 532us befor another reading 106 */ 107 #define NUM_READINGS 4 /* prefer to be power of 2 for efficiency */ 108 #define WAIT_FOR_ADC 532 /* wait for 532 microseconds for ADC */ 109 110 static inline int read_voltage(void) 111 { 112 int i, ret, voltage_read = 0; 113 u16 vol_mon; 114 115 for (i = 0; i < NUM_READINGS; i++) { 116 ret = i2c_read(I2C_VOL_MONITOR_ADDR, 117 I2C_VOL_MONITOR_BUS_V_OFFSET, 1, (void *)&vol_mon, 2); 118 if (ret) { 119 printf("VID: failed to read core voltage\n"); 120 return ret; 121 } 122 if (vol_mon & I2C_VOL_MONITOR_BUS_V_OVF) { 123 printf("VID: Core voltage sensor error\n"); 124 return -1; 125 } 126 debug("VID: bus voltage reads 0x%04x\n", vol_mon); 127 /* LSB = 4mv */ 128 voltage_read += (vol_mon >> I2C_VOL_MONITOR_BUS_V_SHIFT) * 4; 129 udelay(WAIT_FOR_ADC); 130 } 131 /* calculate the average */ 132 voltage_read /= NUM_READINGS; 133 134 return voltage_read; 135 } 136 137 /* 138 * We need to calculate how long before the voltage starts to drop or increase 139 * It returns with the loop count. Each loop takes several readings (532us) 140 */ 141 static inline int wait_for_voltage_change(int vdd_last) 142 { 143 int timeout, vdd_current; 144 145 vdd_current = read_voltage(); 146 /* wait until voltage starts to drop */ 147 for (timeout = 0; abs(vdd_last - vdd_current) <= 4 && 148 timeout < 100; timeout++) { 149 vdd_current = read_voltage(); 150 } 151 if (timeout >= 100) { 152 printf("VID: Voltage adjustment timeout\n"); 153 return -1; 154 } 155 return timeout; 156 } 157 158 /* 159 * argument 'wait' is the time we know the voltage difference can be measured 160 * this function keeps reading the voltage until it is stable 161 */ 162 static inline int wait_for_voltage_stable(int wait) 163 { 164 int timeout, vdd_current, vdd_last; 165 166 vdd_last = read_voltage(); 167 udelay(wait * NUM_READINGS * WAIT_FOR_ADC); 168 /* wait until voltage is stable */ 169 vdd_current = read_voltage(); 170 for (timeout = 0; abs(vdd_last - vdd_current) >= 4 && 171 timeout < 100; timeout++) { 172 vdd_last = vdd_current; 173 udelay(wait * NUM_READINGS * WAIT_FOR_ADC); 174 vdd_current = read_voltage(); 175 } 176 if (timeout >= 100) { 177 printf("VID: Voltage adjustment timeout\n"); 178 return -1; 179 } 180 181 return vdd_current; 182 } 183 184 static inline int set_voltage(u8 vid) 185 { 186 int wait, vdd_last; 187 188 vdd_last = read_voltage(); 189 QIXIS_WRITE(brdcfg[6], vid); 190 wait = wait_for_voltage_change(vdd_last); 191 if (wait < 0) 192 return -1; 193 debug("VID: Waited %d us\n", wait * NUM_READINGS * WAIT_FOR_ADC); 194 wait = wait ? wait : 1; 195 196 vdd_last = wait_for_voltage_stable(wait); 197 if (vdd_last < 0) 198 return -1; 199 debug("VID: Current voltage is %d mV\n", vdd_last); 200 201 return vdd_last; 202 } 203 204 205 static int adjust_vdd(ulong vdd_override) 206 { 207 int re_enable = disable_interrupts(); 208 ccsr_gur_t __iomem *gur = 209 (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 210 u32 fusesr; 211 u8 vid, vid_current; 212 int vdd_target, vdd_current, vdd_last; 213 int ret; 214 unsigned long vdd_string_override; 215 char *vdd_string; 216 static const uint16_t vdd[32] = { 217 0, /* unused */ 218 9875, /* 0.9875V */ 219 9750, 220 9625, 221 9500, 222 9375, 223 9250, 224 9125, 225 9000, 226 8875, 227 8750, 228 8625, 229 8500, 230 8375, 231 8250, 232 8125, 233 10000, /* 1.0000V */ 234 10125, 235 10250, 236 10375, 237 10500, 238 10625, 239 10750, 240 10875, 241 11000, 242 0, /* reserved */ 243 }; 244 struct vdd_drive { 245 u8 vid; 246 unsigned voltage; 247 }; 248 249 ret = select_i2c_ch_pca9547(I2C_MUX_CH_VOL_MONITOR); 250 if (ret) { 251 debug("VID: I2c failed to switch channel\n"); 252 ret = -1; 253 goto exit; 254 } 255 256 /* get the voltage ID from fuse status register */ 257 fusesr = in_be32(&gur->dcfg_fusesr); 258 vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_VID_SHIFT) & 259 FSL_CORENET_DCFG_FUSESR_VID_MASK; 260 if (vid == FSL_CORENET_DCFG_FUSESR_VID_MASK) { 261 vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT) & 262 FSL_CORENET_DCFG_FUSESR_ALTVID_MASK; 263 } 264 vdd_target = vdd[vid]; 265 266 /* check override variable for overriding VDD */ 267 vdd_string = env_get("t4240qds_vdd_mv"); 268 if (vdd_override == 0 && vdd_string && 269 !strict_strtoul(vdd_string, 10, &vdd_string_override)) 270 vdd_override = vdd_string_override; 271 if (vdd_override >= 819 && vdd_override <= 1212) { 272 vdd_target = vdd_override * 10; /* convert to 1/10 mV */ 273 debug("VDD override is %lu\n", vdd_override); 274 } else if (vdd_override != 0) { 275 printf("Invalid value.\n"); 276 } 277 278 if (vdd_target == 0) { 279 debug("VID: VID not used\n"); 280 ret = 0; 281 goto exit; 282 } else { 283 /* round up and divice by 10 to get a value in mV */ 284 vdd_target = DIV_ROUND_UP(vdd_target, 10); 285 debug("VID: vid = %d mV\n", vdd_target); 286 } 287 288 /* 289 * Check current board VID setting 290 * Voltage regulator support output to 6.250mv step 291 * The highes voltage allowed for this board is (vid=0x40) 1.21250V 292 * the lowest is (vid=0x7f) 0.81875V 293 */ 294 vid_current = QIXIS_READ(brdcfg[6]); 295 vdd_current = 121250 - (vid_current - 0x40) * 625; 296 debug("VID: Current vid setting is (0x%x) %d mV\n", 297 vid_current, vdd_current/100); 298 299 /* 300 * Read voltage monitor to check real voltage. 301 * Voltage monitor LSB is 4mv. 302 */ 303 vdd_last = read_voltage(); 304 if (vdd_last < 0) { 305 printf("VID: Could not read voltage sensor abort VID adjustment\n"); 306 ret = -1; 307 goto exit; 308 } 309 debug("VID: Core voltage is at %d mV\n", vdd_last); 310 /* 311 * Adjust voltage to at or 8mV above target. 312 * Each step of adjustment is 6.25mV. 313 * Stepping down too fast may cause over current. 314 */ 315 while (vdd_last > 0 && vid_current < 0x80 && 316 vdd_last > (vdd_target + 8)) { 317 vid_current++; 318 vdd_last = set_voltage(vid_current); 319 } 320 /* 321 * Check if we need to step up 322 * This happens when board voltage switch was set too low 323 */ 324 while (vdd_last > 0 && vid_current >= 0x40 && 325 vdd_last < vdd_target + 2) { 326 vid_current--; 327 vdd_last = set_voltage(vid_current); 328 } 329 if (vdd_last > 0) 330 printf("VID: Core voltage %d mV\n", vdd_last); 331 else 332 ret = -1; 333 334 exit: 335 if (re_enable) 336 enable_interrupts(); 337 return ret; 338 } 339 340 /* Configure Crossbar switches for Front-Side SerDes Ports */ 341 int config_frontside_crossbar_vsc3316(void) 342 { 343 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 344 u32 srds_prtcl_s1, srds_prtcl_s2; 345 int ret; 346 347 ret = select_i2c_ch_pca9547(I2C_MUX_CH_VSC3316_FS); 348 if (ret) 349 return ret; 350 351 srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) & 352 FSL_CORENET2_RCWSR4_SRDS1_PRTCL; 353 srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; 354 switch (srds_prtcl_s1) { 355 case 37: 356 case 38: 357 /* swap first lane and third lane on slot1 */ 358 vsc3316_fsm1_tx[0][1] = 14; 359 vsc3316_fsm1_tx[6][1] = 0; 360 vsc3316_fsm1_rx[1][1] = 2; 361 vsc3316_fsm1_rx[6][1] = 13; 362 case 39: 363 case 40: 364 case 45: 365 case 46: 366 case 47: 367 case 48: 368 /* swap first lane and third lane on slot2 */ 369 vsc3316_fsm1_tx[2][1] = 8; 370 vsc3316_fsm1_tx[4][1] = 6; 371 vsc3316_fsm1_rx[2][1] = 10; 372 vsc3316_fsm1_rx[5][1] = 5; 373 default: 374 ret = vsc3316_config(VSC3316_FSM_TX_ADDR, vsc3316_fsm1_tx, 8); 375 if (ret) 376 return ret; 377 ret = vsc3316_config(VSC3316_FSM_RX_ADDR, vsc3316_fsm1_rx, 8); 378 if (ret) 379 return ret; 380 break; 381 } 382 383 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) & 384 FSL_CORENET2_RCWSR4_SRDS2_PRTCL; 385 srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; 386 switch (srds_prtcl_s2) { 387 case 37: 388 case 38: 389 /* swap first lane and third lane on slot3 */ 390 vsc3316_fsm2_tx[2][1] = 11; 391 vsc3316_fsm2_tx[5][1] = 4; 392 vsc3316_fsm2_rx[2][1] = 9; 393 vsc3316_fsm2_rx[4][1] = 7; 394 case 39: 395 case 40: 396 case 45: 397 case 46: 398 case 47: 399 case 48: 400 case 49: 401 case 50: 402 case 51: 403 case 52: 404 case 53: 405 case 54: 406 /* swap first lane and third lane on slot4 */ 407 vsc3316_fsm2_tx[6][1] = 3; 408 vsc3316_fsm2_tx[1][1] = 12; 409 vsc3316_fsm2_rx[0][1] = 1; 410 vsc3316_fsm2_rx[6][1] = 15; 411 default: 412 ret = vsc3316_config(VSC3316_FSM_TX_ADDR, vsc3316_fsm2_tx, 8); 413 if (ret) 414 return ret; 415 ret = vsc3316_config(VSC3316_FSM_RX_ADDR, vsc3316_fsm2_rx, 8); 416 if (ret) 417 return ret; 418 break; 419 } 420 421 return 0; 422 } 423 424 int config_backside_crossbar_mux(void) 425 { 426 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 427 u32 srds_prtcl_s3, srds_prtcl_s4; 428 u8 brdcfg; 429 430 srds_prtcl_s3 = in_be32(&gur->rcwsr[4]) & 431 FSL_CORENET2_RCWSR4_SRDS3_PRTCL; 432 srds_prtcl_s3 >>= FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT; 433 switch (srds_prtcl_s3) { 434 case 0: 435 /* SerDes3 is not enabled */ 436 break; 437 case 1: 438 case 2: 439 case 9: 440 case 10: 441 /* SD3(0:7) => SLOT5(0:7) */ 442 brdcfg = QIXIS_READ(brdcfg[12]); 443 brdcfg &= ~BRDCFG12_SD3MX_MASK; 444 brdcfg |= BRDCFG12_SD3MX_SLOT5; 445 QIXIS_WRITE(brdcfg[12], brdcfg); 446 break; 447 case 3: 448 case 4: 449 case 5: 450 case 6: 451 case 7: 452 case 8: 453 case 11: 454 case 12: 455 case 13: 456 case 14: 457 case 15: 458 case 16: 459 case 17: 460 case 18: 461 case 19: 462 case 20: 463 /* SD3(4:7) => SLOT6(0:3) */ 464 brdcfg = QIXIS_READ(brdcfg[12]); 465 brdcfg &= ~BRDCFG12_SD3MX_MASK; 466 brdcfg |= BRDCFG12_SD3MX_SLOT6; 467 QIXIS_WRITE(brdcfg[12], brdcfg); 468 break; 469 default: 470 printf("WARNING: unsupported for SerDes3 Protocol %d\n", 471 srds_prtcl_s3); 472 return -1; 473 } 474 475 srds_prtcl_s4 = in_be32(&gur->rcwsr[4]) & 476 FSL_CORENET2_RCWSR4_SRDS4_PRTCL; 477 srds_prtcl_s4 >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT; 478 switch (srds_prtcl_s4) { 479 case 0: 480 /* SerDes4 is not enabled */ 481 break; 482 case 1: 483 case 2: 484 /* 10b, SD4(0:7) => SLOT7(0:7) */ 485 brdcfg = QIXIS_READ(brdcfg[12]); 486 brdcfg &= ~BRDCFG12_SD4MX_MASK; 487 brdcfg |= BRDCFG12_SD4MX_SLOT7; 488 QIXIS_WRITE(brdcfg[12], brdcfg); 489 break; 490 case 3: 491 case 4: 492 case 5: 493 case 6: 494 case 7: 495 case 8: 496 /* x1b, SD4(4:7) => SLOT8(0:3) */ 497 brdcfg = QIXIS_READ(brdcfg[12]); 498 brdcfg &= ~BRDCFG12_SD4MX_MASK; 499 brdcfg |= BRDCFG12_SD4MX_SLOT8; 500 QIXIS_WRITE(brdcfg[12], brdcfg); 501 break; 502 case 9: 503 case 10: 504 case 11: 505 case 12: 506 case 13: 507 case 14: 508 case 15: 509 case 16: 510 case 18: 511 /* 00b, SD4(4:5) => AURORA, SD4(6:7) => SATA */ 512 brdcfg = QIXIS_READ(brdcfg[12]); 513 brdcfg &= ~BRDCFG12_SD4MX_MASK; 514 brdcfg |= BRDCFG12_SD4MX_AURO_SATA; 515 QIXIS_WRITE(brdcfg[12], brdcfg); 516 break; 517 default: 518 printf("WARNING: unsupported for SerDes4 Protocol %d\n", 519 srds_prtcl_s4); 520 return -1; 521 } 522 523 return 0; 524 } 525 526 int board_early_init_r(void) 527 { 528 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; 529 int flash_esel = find_tlb_idx((void *)flashbase, 1); 530 531 /* 532 * Remap Boot flash + PROMJET region to caching-inhibited 533 * so that flash can be erased properly. 534 */ 535 536 /* Flush d-cache and invalidate i-cache of any FLASH data */ 537 flush_dcache(); 538 invalidate_icache(); 539 540 if (flash_esel == -1) { 541 /* very unlikely unless something is messed up */ 542 puts("Error: Could not find TLB for FLASH BASE\n"); 543 flash_esel = 2; /* give our best effort to continue */ 544 } else { 545 /* invalidate existing TLB entry for flash + promjet */ 546 disable_tlb(flash_esel); 547 } 548 549 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, 550 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 551 0, flash_esel, BOOKE_PAGESZ_256M, 1); 552 553 /* Disable remote I2C connection to qixis fpga */ 554 QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE); 555 556 /* 557 * Adjust core voltage according to voltage ID 558 * This function changes I2C mux to channel 2. 559 */ 560 if (adjust_vdd(0)) 561 printf("Warning: Adjusting core voltage failed.\n"); 562 563 /* Configure board SERDES ports crossbar */ 564 config_frontside_crossbar_vsc3316(); 565 config_backside_crossbar_mux(); 566 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); 567 568 return 0; 569 } 570 571 unsigned long get_board_sys_clk(void) 572 { 573 u8 sysclk_conf = QIXIS_READ(brdcfg[1]); 574 #ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT 575 /* use accurate clock measurement */ 576 int freq = QIXIS_READ(clk_freq[0]) << 8 | QIXIS_READ(clk_freq[1]); 577 int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]); 578 u32 val; 579 580 val = freq * base; 581 if (val) { 582 debug("SYS Clock measurement is: %d\n", val); 583 return val; 584 } else { 585 printf("Warning: SYS clock measurement is invalid, using value from brdcfg1.\n"); 586 } 587 #endif 588 589 switch (sysclk_conf & 0x0F) { 590 case QIXIS_SYSCLK_83: 591 return 83333333; 592 case QIXIS_SYSCLK_100: 593 return 100000000; 594 case QIXIS_SYSCLK_125: 595 return 125000000; 596 case QIXIS_SYSCLK_133: 597 return 133333333; 598 case QIXIS_SYSCLK_150: 599 return 150000000; 600 case QIXIS_SYSCLK_160: 601 return 160000000; 602 case QIXIS_SYSCLK_166: 603 return 166666666; 604 } 605 return 66666666; 606 } 607 608 unsigned long get_board_ddr_clk(void) 609 { 610 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); 611 #ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT 612 /* use accurate clock measurement */ 613 int freq = QIXIS_READ(clk_freq[2]) << 8 | QIXIS_READ(clk_freq[3]); 614 int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]); 615 u32 val; 616 617 val = freq * base; 618 if (val) { 619 debug("DDR Clock measurement is: %d\n", val); 620 return val; 621 } else { 622 printf("Warning: DDR clock measurement is invalid, using value from brdcfg1.\n"); 623 } 624 #endif 625 626 switch ((ddrclk_conf & 0x30) >> 4) { 627 case QIXIS_DDRCLK_100: 628 return 100000000; 629 case QIXIS_DDRCLK_125: 630 return 125000000; 631 case QIXIS_DDRCLK_133: 632 return 133333333; 633 } 634 return 66666666; 635 } 636 637 int misc_init_r(void) 638 { 639 u8 sw; 640 void *srds_base = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; 641 serdes_corenet_t *srds_regs; 642 u32 actual[MAX_SERDES]; 643 u32 pllcr0, expected; 644 unsigned int i; 645 646 sw = QIXIS_READ(brdcfg[2]); 647 for (i = 0; i < MAX_SERDES; i++) { 648 unsigned int clock = (sw >> (6 - 2 * i)) & 3; 649 switch (clock) { 650 case 0: 651 actual[i] = SRDS_PLLCR0_RFCK_SEL_100; 652 break; 653 case 1: 654 actual[i] = SRDS_PLLCR0_RFCK_SEL_125; 655 break; 656 case 2: 657 actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25; 658 break; 659 case 3: 660 actual[i] = SRDS_PLLCR0_RFCK_SEL_161_13; 661 break; 662 } 663 } 664 665 for (i = 0; i < MAX_SERDES; i++) { 666 srds_regs = srds_base + i * 0x1000; 667 pllcr0 = srds_regs->bank[0].pllcr0; 668 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK; 669 if (expected != actual[i]) { 670 printf("Warning: SERDES%u expects reference clock %sMHz, but actual is %sMHz\n", 671 i + 1, serdes_clock_to_string(expected), 672 serdes_clock_to_string(actual[i])); 673 } 674 } 675 676 return 0; 677 } 678 679 int ft_board_setup(void *blob, bd_t *bd) 680 { 681 phys_addr_t base; 682 phys_size_t size; 683 684 ft_cpu_setup(blob, bd); 685 686 base = env_get_bootm_low(); 687 size = env_get_bootm_size(); 688 689 fdt_fixup_memory(blob, (u64)base, (u64)size); 690 691 #ifdef CONFIG_PCI 692 pci_of_setup(blob, bd); 693 #endif 694 695 fdt_fixup_liodn(blob); 696 fsl_fdt_fixup_dr_usb(blob, bd); 697 698 #ifdef CONFIG_SYS_DPAA_FMAN 699 fdt_fixup_fman_ethernet(blob); 700 fdt_fixup_board_enet(blob); 701 #endif 702 703 return 0; 704 } 705 706 /* 707 * This function is called by bdinfo to print detail board information. 708 * As an exmaple for future board, we organize the messages into 709 * several sections. If applicable, the message is in the format of 710 * <name> = <value> 711 * It should aligned with normal output of bdinfo command. 712 * 713 * Voltage: Core, DDR and another configurable voltages 714 * Clock : Critical clocks which are not printed already 715 * RCW : RCW source if not printed already 716 * Misc : Other important information not in above catagories 717 */ 718 void board_detail(void) 719 { 720 int i; 721 u8 brdcfg[16], dutcfg[16], rst_ctl; 722 int vdd, rcwsrc; 723 static const char * const clk[] = {"66.67", "100", "125", "133.33"}; 724 725 for (i = 0; i < 16; i++) { 726 brdcfg[i] = qixis_read(offsetof(struct qixis, brdcfg[0]) + i); 727 dutcfg[i] = qixis_read(offsetof(struct qixis, dutcfg[0]) + i); 728 } 729 730 /* Voltage secion */ 731 if (!select_i2c_ch_pca9547(I2C_MUX_CH_VOL_MONITOR)) { 732 vdd = read_voltage(); 733 if (vdd > 0) 734 printf("Core voltage= %d mV\n", vdd); 735 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); 736 } 737 738 printf("XVDD = 1.%d V\n", ((brdcfg[8] & 0xf) - 4) * 5 + 25); 739 740 /* clock section */ 741 printf("SYSCLK = %s MHz\nDDRCLK = %s MHz\n", 742 clk[(brdcfg[11] >> 2) & 0x3], clk[brdcfg[11] & 3]); 743 744 /* RCW section */ 745 rcwsrc = (dutcfg[0] << 1) + (dutcfg[1] & 1); 746 puts("RCW source = "); 747 switch (rcwsrc) { 748 case 0x017: 749 case 0x01f: 750 puts("8-bit NOR\n"); 751 break; 752 case 0x027: 753 case 0x02F: 754 puts("16-bit NOR\n"); 755 break; 756 case 0x040: 757 puts("SDHC/eMMC\n"); 758 break; 759 case 0x044: 760 puts("SPI 16-bit addressing\n"); 761 break; 762 case 0x045: 763 puts("SPI 24-bit addressing\n"); 764 break; 765 case 0x048: 766 puts("I2C normal addressing\n"); 767 break; 768 case 0x049: 769 puts("I2C extended addressing\n"); 770 break; 771 case 0x108: 772 case 0x109: 773 case 0x10a: 774 case 0x10b: 775 puts("8-bit NAND, 2KB\n"); 776 break; 777 default: 778 if ((rcwsrc >= 0x080) && (rcwsrc <= 0x09f)) 779 puts("Hard-coded RCW\n"); 780 else if ((rcwsrc >= 0x110) && (rcwsrc <= 0x11f)) 781 puts("8-bit NAND, 4KB\n"); 782 else 783 puts("unknown\n"); 784 break; 785 } 786 787 /* Misc section */ 788 rst_ctl = QIXIS_READ(rst_ctl); 789 puts("HRESET_REQ = "); 790 switch (rst_ctl & 0x30) { 791 case 0x00: 792 puts("Ignored\n"); 793 break; 794 case 0x10: 795 puts("Assert HRESET\n"); 796 break; 797 case 0x30: 798 puts("Reset system\n"); 799 break; 800 default: 801 puts("N/A\n"); 802 break; 803 } 804 } 805 806 /* 807 * Reverse engineering switch settings. 808 * Some bits cannot be figured out. They will be displayed as 809 * underscore in binary format. mask[] has those bits. 810 * Some bits are calculated differently than the actual switches 811 * if booting with overriding by FPGA. 812 */ 813 void qixis_dump_switch(void) 814 { 815 int i; 816 u8 sw[9]; 817 818 /* 819 * Any bit with 1 means that bit cannot be reverse engineered. 820 * It will be displayed as _ in binary format. 821 */ 822 static const u8 mask[] = {0, 0, 0, 0, 0, 0x1, 0xcf, 0x3f, 0x1f}; 823 char buf[10]; 824 u8 brdcfg[16], dutcfg[16]; 825 826 for (i = 0; i < 16; i++) { 827 brdcfg[i] = qixis_read(offsetof(struct qixis, brdcfg[0]) + i); 828 dutcfg[i] = qixis_read(offsetof(struct qixis, dutcfg[0]) + i); 829 } 830 831 sw[0] = dutcfg[0]; 832 sw[1] = (dutcfg[1] << 0x07) | 833 ((dutcfg[12] & 0xC0) >> 1) | 834 ((dutcfg[11] & 0xE0) >> 3) | 835 ((dutcfg[6] & 0x80) >> 6) | 836 ((dutcfg[1] & 0x80) >> 7); 837 sw[2] = ((brdcfg[1] & 0x0f) << 4) | 838 ((brdcfg[1] & 0x30) >> 2) | 839 ((brdcfg[1] & 0x40) >> 5) | 840 ((brdcfg[1] & 0x80) >> 7); 841 sw[3] = brdcfg[2]; 842 sw[4] = ((dutcfg[2] & 0x01) << 7) | 843 ((dutcfg[2] & 0x06) << 4) | 844 ((~QIXIS_READ(present)) & 0x10) | 845 ((brdcfg[3] & 0x80) >> 4) | 846 ((brdcfg[3] & 0x01) << 2) | 847 ((brdcfg[6] == 0x62) ? 3 : 848 ((brdcfg[6] == 0x5a) ? 2 : 849 ((brdcfg[6] == 0x5e) ? 1 : 0))); 850 sw[5] = ((brdcfg[0] & 0x0f) << 4) | 851 ((QIXIS_READ(rst_ctl) & 0x30) >> 2) | 852 ((brdcfg[0] & 0x40) >> 5); 853 sw[6] = (brdcfg[11] & 0x20) | 854 ((brdcfg[5] & 0x02) << 3); 855 sw[7] = (((~QIXIS_READ(rst_ctl)) & 0x40) << 1) | 856 ((brdcfg[5] & 0x10) << 2); 857 sw[8] = ((brdcfg[12] & 0x08) << 4) | 858 ((brdcfg[12] & 0x03) << 5); 859 860 puts("DIP switch (reverse-engineering)\n"); 861 for (i = 0; i < 9; i++) { 862 printf("SW%d = 0b%s (0x%02x)\n", 863 i + 1, byte_to_binary_mask(sw[i], mask[i], buf), sw[i]); 864 } 865 } 866 867 static int do_vdd_adjust(cmd_tbl_t *cmdtp, 868 int flag, int argc, 869 char * const argv[]) 870 { 871 ulong override; 872 873 if (argc < 2) 874 return CMD_RET_USAGE; 875 if (!strict_strtoul(argv[1], 10, &override)) 876 adjust_vdd(override); /* the value is checked by callee */ 877 else 878 return CMD_RET_USAGE; 879 880 return 0; 881 } 882 883 U_BOOT_CMD( 884 vdd_override, 2, 0, do_vdd_adjust, 885 "Override VDD", 886 "- override with the voltage specified in mV, eg. 1050" 887 ); 888
