1 # 2 # I2C subsystem configuration 3 # 4 5 menu "I2C support" 6 7 config DM_I2C 8 bool "Enable Driver Model for I2C drivers" 9 depends on DM 10 help 11 Enable driver model for I2C. The I2C uclass interface: probe, read, 12 write and speed, is implemented with the bus drivers operations, 13 which provide methods for bus setting and data transfer. Each chip 14 device (bus child) info is kept as parent platdata. The interface 15 is defined in include/i2c.h. When i2c bus driver supports the i2c 16 uclass, but the device drivers not, then DM_I2C_COMPAT config can 17 be used as compatibility layer. 18 19 config DM_I2C_COMPAT 20 bool "Enable I2C compatibility layer" 21 depends on DM 22 help 23 Enable old-style I2C functions for compatibility with existing code. 24 This option can be enabled as a temporary measure to avoid needing 25 to convert all code for a board in a single commit. It should not 26 be enabled for any board in an official release. 27 28 config I2C_CROS_EC_TUNNEL 29 tristate "Chrome OS EC tunnel I2C bus" 30 depends on CROS_EC 31 help 32 This provides an I2C bus that will tunnel i2c commands through to 33 the other side of the Chrome OS EC to the I2C bus connected there. 34 This will work whatever the interface used to talk to the EC (SPI, 35 I2C or LPC). Some Chromebooks use this when the hardware design 36 does not allow direct access to the main PMIC from the AP. 37 38 config I2C_CROS_EC_LDO 39 bool "Provide access to LDOs on the Chrome OS EC" 40 depends on CROS_EC 41 ---help--- 42 On many Chromebooks the main PMIC is inaccessible to the AP. This is 43 often dealt with by using an I2C pass-through interface provided by 44 the EC. On some unfortunate models (e.g. Spring) the pass-through 45 is not available, and an LDO message is available instead. This 46 option enables a driver which provides very basic access to those 47 regulators, via the EC. We implement this as an I2C bus which 48 emulates just the TPS65090 messages we know about. This is done to 49 avoid duplicating the logic in the TPS65090 regulator driver for 50 enabling/disabling an LDO. 51 52 config I2C_SET_DEFAULT_BUS_NUM 53 bool "Set default I2C bus number" 54 depends on DM_I2C 55 help 56 Set default number of I2C bus to be accessed. This option provides 57 behaviour similar to old (i.e. pre DM) I2C bus driver. 58 59 config I2C_DEFAULT_BUS_NUMBER 60 hex "I2C default bus number" 61 depends on I2C_SET_DEFAULT_BUS_NUM 62 default 0x0 63 help 64 Number of default I2C bus to use 65 66 config DM_I2C_GPIO 67 bool "Enable Driver Model for software emulated I2C bus driver" 68 depends on DM_I2C && DM_GPIO 69 help 70 Enable the i2c bus driver emulation by using the GPIOs. The bus GPIO 71 configuration is given by the device tree. Kernel-style device tree 72 bindings are supported. 73 Binding info: doc/device-tree-bindings/i2c/i2c-gpio.txt 74 75 config SYS_I2C_AT91 76 bool "Atmel I2C driver" 77 depends on DM_I2C && ARCH_AT91 78 help 79 Add support for the Atmel I2C driver. A serious problem is that there 80 is no documented way to issue repeated START conditions for more than 81 two messages, as needed to support combined I2C messages. Use the 82 i2c-gpio driver unless your system can cope with this limitation. 83 Binding info: doc/device-tree-bindings/i2c/i2c-at91.txt 84 85 config SYS_I2C_FSL 86 bool "Freescale I2C bus driver" 87 depends on DM_I2C 88 help 89 Add support for Freescale I2C busses as used on MPC8240, MPC8245, and 90 MPC85xx processors. 91 92 config SYS_I2C_CADENCE 93 tristate "Cadence I2C Controller" 94 depends on DM_I2C && (ARCH_ZYNQ || ARM64) 95 help 96 Say yes here to select Cadence I2C Host Controller. This controller is 97 e.g. used by Xilinx Zynq. 98 99 config SYS_I2C_DW 100 bool "Designware I2C Controller" 101 default n 102 help 103 Say yes here to select the Designware I2C Host Controller. This 104 controller is used in various SoCs, e.g. the ST SPEAr, Altera 105 SoCFPGA, Synopsys ARC700 and some Intel x86 SoCs. 106 107 config SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED 108 bool "DW I2C Enable Status Register not supported" 109 depends on SYS_I2C_DW && (TARGET_SPEAR300 || TARGET_SPEAR310 || \ 110 TARGET_SPEAR320 || TARGET_SPEAR600 || TARGET_X600) 111 default y 112 help 113 Some versions of the Designware I2C controller do not support the 114 enable status register. This config option can be enabled in such 115 cases. 116 117 config SYS_I2C_ASPEED 118 bool "Aspeed I2C Controller" 119 depends on DM_I2C && ARCH_ASPEED 120 help 121 Say yes here to select Aspeed I2C Host Controller. The driver 122 supports AST2500 and AST2400 controllers, but is very limited. 123 Only single master mode is supported and only byte-by-byte 124 synchronous reads and writes are supported, no Pool Buffers or DMA. 125 126 config SYS_I2C_INTEL 127 bool "Intel I2C/SMBUS driver" 128 depends on DM_I2C 129 help 130 Add support for the Intel SMBUS driver. So far this driver is just 131 a stub which perhaps some basic init. There is no implementation of 132 the I2C API meaning that any I2C operations will immediately fail 133 for now. 134 135 config SYS_I2C_IMX_LPI2C 136 bool "NXP i.MX LPI2C driver" 137 help 138 Add support for the NXP i.MX LPI2C driver. 139 140 config SYS_I2C_MESON 141 bool "Amlogic Meson I2C driver" 142 depends on DM_I2C && ARCH_MESON 143 help 144 Add support for the I2C controller available in Amlogic Meson 145 SoCs. The controller supports programmable bus speed including 146 standard (100kbits/s) and fast (400kbit/s) speed and allows the 147 software to define a flexible format of the bit streams. It has an 148 internal buffer holding up to 8 bytes for transfers and supports 149 both 7-bit and 10-bit addresses. 150 151 config SYS_I2C_MXC 152 bool "NXP MXC I2C driver" 153 help 154 Add support for the NXP I2C driver. This supports upto for bus 155 channels and operating on standard mode upto 100 kbits/s and fast 156 mode upto 400 kbits/s. 157 158 if SYS_I2C_MXC 159 config SYS_I2C_MXC_I2C1 160 bool "NXP MXC I2C1" 161 help 162 Add support for NXP MXC I2C Controller 1. 163 Required for SoCs which have I2C MXC controller 1 eg LS1088A, LS2080A 164 165 config SYS_I2C_MXC_I2C2 166 bool "NXP MXC I2C2" 167 help 168 Add support for NXP MXC I2C Controller 2. 169 Required for SoCs which have I2C MXC controller 2 eg LS1088A, LS2080A 170 171 config SYS_I2C_MXC_I2C3 172 bool "NXP MXC I2C3" 173 help 174 Add support for NXP MXC I2C Controller 3. 175 Required for SoCs which have I2C MXC controller 3 eg LS1088A, LS2080A 176 177 config SYS_I2C_MXC_I2C4 178 bool "NXP MXC I2C4" 179 help 180 Add support for NXP MXC I2C Controller 4. 181 Required for SoCs which have I2C MXC controller 4 eg LS1088A, LS2080A 182 183 config SYS_I2C_MXC_I2C5 184 bool "NXP MXC I2C5" 185 help 186 Add support for NXP MXC I2C Controller 5. 187 Required for SoCs which have I2C MXC controller 5 eg LX2160A 188 189 config SYS_I2C_MXC_I2C6 190 bool "NXP MXC I2C6" 191 help 192 Add support for NXP MXC I2C Controller 6. 193 Required for SoCs which have I2C MXC controller 6 eg LX2160A 194 195 config SYS_I2C_MXC_I2C7 196 bool "NXP MXC I2C7" 197 help 198 Add support for NXP MXC I2C Controller 7. 199 Required for SoCs which have I2C MXC controller 7 eg LX2160A 200 201 config SYS_I2C_MXC_I2C8 202 bool "NXP MXC I2C8" 203 help 204 Add support for NXP MXC I2C Controller 8. 205 Required for SoCs which have I2C MXC controller 8 eg LX2160A 206 endif 207 208 if SYS_I2C_MXC_I2C1 209 config SYS_MXC_I2C1_SPEED 210 int "I2C Channel 1 speed" 211 default 40000000 if TARGET_LS2080A_SIMU || TARGET_LS2080A_EMU 212 default 100000 213 help 214 MXC I2C Channel 1 speed 215 216 config SYS_MXC_I2C1_SLAVE 217 int "I2C1 Slave" 218 default 0 219 help 220 MXC I2C1 Slave 221 endif 222 223 if SYS_I2C_MXC_I2C2 224 config SYS_MXC_I2C2_SPEED 225 int "I2C Channel 2 speed" 226 default 40000000 if TARGET_LS2080A_SIMU || TARGET_LS2080A_EMU 227 default 100000 228 help 229 MXC I2C Channel 2 speed 230 231 config SYS_MXC_I2C2_SLAVE 232 int "I2C2 Slave" 233 default 0 234 help 235 MXC I2C2 Slave 236 endif 237 238 if SYS_I2C_MXC_I2C3 239 config SYS_MXC_I2C3_SPEED 240 int "I2C Channel 3 speed" 241 default 100000 242 help 243 MXC I2C Channel 3 speed 244 245 config SYS_MXC_I2C3_SLAVE 246 int "I2C3 Slave" 247 default 0 248 help 249 MXC I2C3 Slave 250 endif 251 252 if SYS_I2C_MXC_I2C4 253 config SYS_MXC_I2C4_SPEED 254 int "I2C Channel 4 speed" 255 default 100000 256 help 257 MXC I2C Channel 4 speed 258 259 config SYS_MXC_I2C4_SLAVE 260 int "I2C4 Slave" 261 default 0 262 help 263 MXC I2C4 Slave 264 endif 265 266 if SYS_I2C_MXC_I2C5 267 config SYS_MXC_I2C5_SPEED 268 int "I2C Channel 5 speed" 269 default 100000 270 help 271 MXC I2C Channel 5 speed 272 273 config SYS_MXC_I2C5_SLAVE 274 int "I2C5 Slave" 275 default 0 276 help 277 MXC I2C5 Slave 278 endif 279 280 if SYS_I2C_MXC_I2C6 281 config SYS_MXC_I2C6_SPEED 282 int "I2C Channel 6 speed" 283 default 100000 284 help 285 MXC I2C Channel 6 speed 286 287 config SYS_MXC_I2C6_SLAVE 288 int "I2C6 Slave" 289 default 0 290 help 291 MXC I2C6 Slave 292 endif 293 294 if SYS_I2C_MXC_I2C7 295 config SYS_MXC_I2C7_SPEED 296 int "I2C Channel 7 speed" 297 default 100000 298 help 299 MXC I2C Channel 7 speed 300 301 config SYS_MXC_I2C7_SLAVE 302 int "I2C7 Slave" 303 default 0 304 help 305 MXC I2C7 Slave 306 endif 307 308 if SYS_I2C_MXC_I2C8 309 config SYS_MXC_I2C8_SPEED 310 int "I2C Channel 8 speed" 311 default 100000 312 help 313 MXC I2C Channel 8 speed 314 315 config SYS_MXC_I2C8_SLAVE 316 int "I2C8 Slave" 317 default 0 318 help 319 MXC I2C8 Slave 320 endif 321 322 config SYS_I2C_OMAP24XX 323 bool "TI OMAP2+ I2C driver" 324 depends on ARCH_OMAP2PLUS 325 help 326 Add support for the OMAP2+ I2C driver. 327 328 if SYS_I2C_OMAP24XX 329 config SYS_OMAP24_I2C_SLAVE 330 int "I2C Slave addr channel 0" 331 default 1 332 help 333 OMAP24xx I2C Slave address channel 0 334 335 config SYS_OMAP24_I2C_SPEED 336 int "I2C Slave channel 0 speed" 337 default 100000 338 help 339 OMAP24xx Slave speed channel 0 340 endif 341 342 config SYS_I2C_RCAR_I2C 343 bool "Renesas RCar I2C driver" 344 depends on (RCAR_GEN3 || RCAR_GEN2) && DM_I2C 345 help 346 Support for Renesas RCar I2C controller. 347 348 config SYS_I2C_RCAR_IIC 349 bool "Renesas RCar Gen3 IIC driver" 350 depends on (RCAR_GEN3 || RCAR_GEN2) && DM_I2C 351 help 352 Support for Renesas RCar Gen3 IIC controller. 353 354 config SYS_I2C_ROCKCHIP 355 bool "Rockchip I2C driver" 356 depends on DM_I2C 357 help 358 Add support for the Rockchip I2C driver. This is used with various 359 Rockchip parts such as RK3126, RK3128, RK3036 and RK3288. All chips 360 have several I2C ports and all are provided, controled by the 361 device tree. 362 363 config SYS_I2C_SANDBOX 364 bool "Sandbox I2C driver" 365 depends on SANDBOX && DM_I2C 366 help 367 Enable I2C support for sandbox. This is an emulation of a real I2C 368 bus. Devices can be attached to the bus using the device tree 369 which specifies the driver to use. See sandbox.dts as an example. 370 371 config SYS_I2C_S3C24X0 372 bool "Samsung I2C driver" 373 depends on ARCH_EXYNOS4 && DM_I2C 374 help 375 Support for Samsung I2C controller as Samsung SoCs. 376 377 config SYS_I2C_STM32F7 378 bool "STMicroelectronics STM32F7 I2C support" 379 depends on (STM32F7 || STM32H7 || ARCH_STM32MP) && DM_I2C 380 help 381 Enable this option to add support for STM32 I2C controller 382 introduced with STM32F7/H7 SoCs. This I2C controller supports : 383 _ Slave and master modes 384 _ Multimaster capability 385 _ Standard-mode (up to 100 kHz) 386 _ Fast-mode (up to 400 kHz) 387 _ Fast-mode Plus (up to 1 MHz) 388 _ 7-bit and 10-bit addressing mode 389 _ Multiple 7-bit slave addresses (2 addresses, 1 with configurable mask) 390 _ All 7-bit addresses acknowledge mode 391 _ General call 392 _ Programmable setup and hold times 393 _ Easy to use event management 394 _ Optional clock stretching 395 _ Software reset 396 397 config SYS_I2C_UNIPHIER 398 bool "UniPhier I2C driver" 399 depends on ARCH_UNIPHIER && DM_I2C 400 default y 401 help 402 Support for UniPhier I2C controller driver. This I2C controller 403 is used on PH1-LD4, PH1-sLD8 or older UniPhier SoCs. 404 405 config SYS_I2C_UNIPHIER_F 406 bool "UniPhier FIFO-builtin I2C driver" 407 depends on ARCH_UNIPHIER && DM_I2C 408 default y 409 help 410 Support for UniPhier FIFO-builtin I2C controller driver. 411 This I2C controller is used on PH1-Pro4 or newer UniPhier SoCs. 412 413 config SYS_I2C_MVTWSI 414 bool "Marvell I2C driver" 415 depends on DM_I2C 416 help 417 Support for Marvell I2C controllers as used on the orion5x and 418 kirkwood SoC families. 419 420 config TEGRA186_BPMP_I2C 421 bool "Enable Tegra186 BPMP-based I2C driver" 422 depends on TEGRA186_BPMP 423 help 424 Support for Tegra I2C controllers managed by the BPMP (Boot and 425 Power Management Processor). On Tegra186, some I2C controllers are 426 directly controlled by the main CPU, whereas others are controlled 427 by the BPMP, and can only be accessed by the main CPU via IPC 428 requests to the BPMP. This driver covers the latter case. 429 430 config SYS_I2C_BUS_MAX 431 int "Max I2C busses" 432 depends on ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_SOCFPGA 433 default 2 if TI816X 434 default 3 if OMAP34XX || AM33XX || AM43XX || ARCH_KEYSTONE 435 default 4 if ARCH_SOCFPGA || OMAP44XX || TI814X 436 default 5 if OMAP54XX 437 help 438 Define the maximum number of available I2C buses. 439 440 config SYS_I2C_ZYNQ 441 bool "Xilinx I2C driver" 442 depends on ARCH_ZYNQMP || ARCH_ZYNQ 443 help 444 Support for Xilinx I2C controller. 445 446 config SYS_I2C_ZYNQ_SLAVE 447 hex "Set slave addr" 448 depends on SYS_I2C_ZYNQ 449 default 0 450 help 451 Set CONFIG_SYS_I2C_ZYNQ_SLAVE for slave addr. 452 453 config SYS_I2C_ZYNQ_SPEED 454 int "Set I2C speed" 455 depends on SYS_I2C_ZYNQ 456 default 100000 457 help 458 Set CONFIG_SYS_I2C_ZYNQ_SPEED for speed setting. 459 460 config ZYNQ_I2C0 461 bool "Xilinx I2C0 controller" 462 depends on SYS_I2C_ZYNQ 463 help 464 Enable Xilinx I2C0 controller. 465 466 config ZYNQ_I2C1 467 bool "Xilinx I2C1 controller" 468 depends on SYS_I2C_ZYNQ 469 help 470 Enable Xilinx I2C1 controller. 471 472 config SYS_I2C_IHS 473 bool "gdsys IHS I2C driver" 474 depends on DM_I2C 475 help 476 Support for gdsys IHS I2C driver on FPGA bus. 477 478 source "drivers/i2c/muxes/Kconfig" 479 480 endmenu 481
