| /external/llvm/lib/Target/Lanai/MCTargetDesc/ |
| LanaiBaseInfo.h | 1 //===-- LanaiBaseInfo.h - Top level definitions for Lanai MC ----*- C++ -*-===//
11 // the Lanai target useful for the compiler back-end and the MC libraries.
31 // Lanai Specific MachineOperand flags.
43 case Lanai::R0:
45 case Lanai::R1:
47 case Lanai::R2:
48 case Lanai::PC:
50 case Lanai::R3:
52 case Lanai::R4:
53 case Lanai::SP
[all...] |
| LanaiELFObjectWriter.cpp | 1 //===-- LanaiELFObjectWriter.cpp - Lanai ELF Writer -----------------------===//
48 case Lanai::FIXUP_LANAI_21:
51 case Lanai::FIXUP_LANAI_21_F:
54 case Lanai::FIXUP_LANAI_25:
57 case Lanai::FIXUP_LANAI_32:
61 case Lanai::FIXUP_LANAI_HI16:
64 case Lanai::FIXUP_LANAI_LO16:
67 case Lanai::FIXUP_LANAI_NONE:
|
| LanaiFixupKinds.h | 1 //===-- LanaiFixupKinds.h - Lanai Specific Fixup Entries --------*- C++ -*-===//
16 namespace Lanai {
22 // MCFixupKindInfo Infos[Lanai::NumTargetFixupKinds]
40 } // namespace Lanai
|
| LanaiAsmBackend.cpp | 1 //===-- LanaiAsmBackend.cpp - Lanai Assembler Backend ---------------------===//
32 case Lanai::FIXUP_LANAI_21:
33 case Lanai::FIXUP_LANAI_21_F:
34 case Lanai::FIXUP_LANAI_25:
35 case Lanai::FIXUP_LANAI_32:
36 case Lanai::FIXUP_LANAI_HI16:
37 case Lanai::FIXUP_LANAI_LO16:
67 return Lanai::NumTargetFixupKinds;
132 static const MCFixupKindInfo Infos[Lanai::NumTargetFixupKinds] = {
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/MCTargetDesc/ |
| LanaiBaseInfo.h | 1 //===-- LanaiBaseInfo.h - Top level definitions for Lanai MC ----*- C++ -*-===//
11 // the Lanai target useful for the compiler back-end and the MC libraries.
31 // Lanai Specific MachineOperand flags.
43 case Lanai::R0:
45 case Lanai::R1:
47 case Lanai::R2:
48 case Lanai::PC:
50 case Lanai::R3:
52 case Lanai::R4:
53 case Lanai::SP
[all...] |
| LanaiELFObjectWriter.cpp | 1 //===-- LanaiELFObjectWriter.cpp - Lanai ELF Writer -----------------------===//
47 case Lanai::FIXUP_LANAI_21:
50 case Lanai::FIXUP_LANAI_21_F:
53 case Lanai::FIXUP_LANAI_25:
56 case Lanai::FIXUP_LANAI_32:
60 case Lanai::FIXUP_LANAI_HI16:
63 case Lanai::FIXUP_LANAI_LO16:
66 case Lanai::FIXUP_LANAI_NONE:
|
| LanaiFixupKinds.h | 1 //===-- LanaiFixupKinds.h - Lanai Specific Fixup Entries --------*- C++ -*-===//
16 namespace Lanai {
22 // MCFixupKindInfo Infos[Lanai::NumTargetFixupKinds]
40 } // namespace Lanai
|
| /external/llvm/lib/Target/Lanai/ |
| LanaiRegisterInfo.cpp | 1 //===-- LanaiRegisterInfo.cpp - Lanai Register Information ------*- C++ -*-===//
10 // This file contains the Lanai implementation of the TargetRegisterInfo class.
15 #include "Lanai.h"
34 LanaiRegisterInfo::LanaiRegisterInfo() : LanaiGenRegisterInfo(Lanai::RCA) {}
44 Reserved.set(Lanai::R0);
45 Reserved.set(Lanai::R1);
46 Reserved.set(Lanai::PC);
47 Reserved.set(Lanai::R2);
48 Reserved.set(Lanai::SP);
49 Reserved.set(Lanai::R4)
[all...] |
| LanaiInstrInfo.cpp | 1 //===-- LanaiInstrInfo.cpp - Lanai Instruction Information ------*- C++ -*-===//
10 // This file contains the Lanai implementation of the TargetInstrInfo class.
14 #include "Lanai.h"
32 : LanaiGenInstrInfo(Lanai::ADJCALLSTACKDOWN, Lanai::ADJCALLSTACKUP),
41 if (!Lanai::GPRRegClass.contains(DestinationRegister, SourceRegister)) {
45 BuildMI(MBB, Position, DL, get(Lanai::OR_I_LO), DestinationRegister)
60 if (!Lanai::GPRRegClass.hasSubClassEq(RegisterClass)) {
63 BuildMI(MBB, Position, DL, get(Lanai::SW_RI))
80 if (!Lanai::GPRRegClass.hasSubClassEq(RegisterClass))
[all...] |
| LanaiMemAluCombiner.cpp | 11 // The Lanai ISA supports instructions where a load/store modifies the base
26 #include "Lanai.h"
40 #define DEBUG_TYPE "lanai-mem-alu-combiner"
45 "disable-lanai-mem-alu-combiner", llvm::cl::init(false),
65 return "Lanai load / store optimization pass";
93 "Lanai memory ALU combiner pass", false, false)
96 bool isSpls(uint16_t Opcode) { return Lanai::splsIdempotent(Opcode) == Opcode; }
103 case Lanai::LDW_RI:
104 case Lanai::LDW_RR:
106 return Lanai::LDW_RI
[all...] |
| LanaiInstrInfo.h | 1 //===- LanaiInstrInfo.h - Lanai Instruction Information ---------*- C++ -*-===//
10 // This file contains the Lanai implementation of the TargetInstrInfo class.
99 // efficient. E.g., on Lanai register-register instructions can set the flag
113 // Lanai can optimize certain select instructions, for example by predicating
143 case Lanai::LDBs_RI:
144 case Lanai::LDBz_RI:
145 case Lanai::LDHs_RI:
146 case Lanai::LDHz_RI:
147 case Lanai::STB_RI:
148 case Lanai::STH_RI
[all...] |
| LanaiMachineFunctionInfo.cpp | 1 //===-- LanaiMachineFuctionInfo.cpp - Lanai machine function info ---===//
22 MF.getRegInfo().createVirtualRegister(&Lanai::GPRRegClass);
|
| LanaiFrameLowering.cpp | 1 //===-- LanaiFrameLowering.cpp - Lanai Frame Information ------------------===//
10 // This file contains the Lanai implementation of TargetFrameLowering class.
62 // ADJDYNALLOC pseudo instructions with a Lanai:ADDI with the
74 if (MI.getOpcode() == Lanai::ADJDYNALLOC) {
79 BuildMI(*MBB, MI, DL, LII.get(Lanai::ADD_I_LO), Dst)
114 BuildMI(MBB, MBBI, DL, LII.get(Lanai::SW_RI))
115 .addReg(Lanai::FP)
116 .addReg(Lanai::SP)
123 BuildMI(MBB, MBBI, DL, LII.get(Lanai::ADD_I_LO), Lanai::FP
[all...] |
| LanaiAsmPrinter.cpp | 1 //===-- LanaiAsmPrinter.cpp - Lanai LLVM assembly writer ------------------===//
11 // of machine-dependent LLVM code to the Lanai assembly language.
16 #include "Lanai.h"
48 const char *getPassName() const override { return "Lanai Assembly Printer"; }
152 assert((MI->getOpcode() == Lanai::CALL || MI->getOpcode() == Lanai::CALLR) &&
160 OutStreamer->EmitInstruction(MCInstBuilder(Lanai::ADD_I_LO)
161 .addReg(Lanai::RCA)
162 .addReg(Lanai::PC)
168 OutStreamer->EmitInstruction(MCInstBuilder(Lanai::SW_RI
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/ |
| LanaiRegisterInfo.cpp | 1 //===-- LanaiRegisterInfo.cpp - Lanai Register Information ------*- C++ -*-===//
10 // This file contains the Lanai implementation of the TargetRegisterInfo class.
15 #include "Lanai.h"
34 LanaiRegisterInfo::LanaiRegisterInfo() : LanaiGenRegisterInfo(Lanai::RCA) {}
44 Reserved.set(Lanai::R0);
45 Reserved.set(Lanai::R1);
46 Reserved.set(Lanai::PC);
47 Reserved.set(Lanai::R2);
48 Reserved.set(Lanai::SP);
49 Reserved.set(Lanai::R4)
[all...] |
| LanaiInstrInfo.cpp | 1 //===-- LanaiInstrInfo.cpp - Lanai Instruction Information ------*- C++ -*-===//
10 // This file contains the Lanai implementation of the TargetInstrInfo class.
14 #include "Lanai.h"
32 : LanaiGenInstrInfo(Lanai::ADJCALLSTACKDOWN, Lanai::ADJCALLSTACKUP),
41 if (!Lanai::GPRRegClass.contains(DestinationRegister, SourceRegister)) {
45 BuildMI(MBB, Position, DL, get(Lanai::OR_I_LO), DestinationRegister)
60 if (!Lanai::GPRRegClass.hasSubClassEq(RegisterClass)) {
63 BuildMI(MBB, Position, DL, get(Lanai::SW_RI))
80 if (!Lanai::GPRRegClass.hasSubClassEq(RegisterClass))
[all...] |
| LanaiMemAluCombiner.cpp | 11 // The Lanai ISA supports instructions where a load/store modifies the base
26 #include "Lanai.h"
40 #define DEBUG_TYPE "lanai-mem-alu-combiner"
45 "disable-lanai-mem-alu-combiner", llvm::cl::init(false),
65 return "Lanai load / store optimization pass";
93 "Lanai memory ALU combiner pass", false, false)
96 bool isSpls(uint16_t Opcode) { return Lanai::splsIdempotent(Opcode) == Opcode; }
103 case Lanai::LDW_RI:
104 case Lanai::LDW_RR:
106 return Lanai::LDW_RI
[all...] |
| LanaiInstrInfo.h | 1 //===- LanaiInstrInfo.h - Lanai Instruction Information ---------*- C++ -*-===//
10 // This file contains the Lanai implementation of the TargetInstrInfo class.
101 // efficient. E.g., on Lanai register-register instructions can set the flag
115 // Lanai can optimize certain select instructions, for example by predicating
146 case Lanai::LDBs_RI:
147 case Lanai::LDBz_RI:
148 case Lanai::LDHs_RI:
149 case Lanai::LDHz_RI:
150 case Lanai::STB_RI:
151 case Lanai::STH_RI
[all...] |
| LanaiMachineFunctionInfo.cpp | 1 //===-- LanaiMachineFuctionInfo.cpp - Lanai machine function info ---===//
22 MF.getRegInfo().createVirtualRegister(&Lanai::GPRRegClass);
|
| LanaiFrameLowering.cpp | 1 //===-- LanaiFrameLowering.cpp - Lanai Frame Information ------------------===//
10 // This file contains the Lanai implementation of TargetFrameLowering class.
62 // ADJDYNALLOC pseudo instructions with a Lanai:ADDI with the
74 if (MI.getOpcode() == Lanai::ADJDYNALLOC) {
79 BuildMI(*MBB, MI, DL, LII.get(Lanai::ADD_I_LO), Dst)
114 BuildMI(MBB, MBBI, DL, LII.get(Lanai::SW_RI))
115 .addReg(Lanai::FP)
116 .addReg(Lanai::SP)
123 BuildMI(MBB, MBBI, DL, LII.get(Lanai::ADD_I_LO), Lanai::FP
[all...] |
| LanaiAsmPrinter.cpp | 1 //===-- LanaiAsmPrinter.cpp - Lanai LLVM assembly writer ------------------===//
11 // of machine-dependent LLVM code to the Lanai assembly language.
16 #include "Lanai.h"
48 StringRef getPassName() const override { return "Lanai Assembly Printer"; }
151 assert((MI->getOpcode() == Lanai::CALL || MI->getOpcode() == Lanai::CALLR) &&
159 OutStreamer->EmitInstruction(MCInstBuilder(Lanai::ADD_I_LO)
160 .addReg(Lanai::RCA)
161 .addReg(Lanai::PC)
167 OutStreamer->EmitInstruction(MCInstBuilder(Lanai::SW_RI
[all...] |
| /external/llvm/lib/Target/Lanai/Disassembler/ |
| LanaiDisassembler.cpp | 1 //===- LanaiDisassembler.cpp - Disassembler for Lanai -----------*- C++ -*-===//
10 // This file is part of the Lanai Disassembler.
16 #include "Lanai.h"
112 Instr.getOperand(2).setReg(Lanai::R0);
156 Lanai::R0, Lanai::R1, Lanai::PC, Lanai::R3, Lanai::SP, Lanai::FP
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/Disassembler/ |
| LanaiDisassembler.cpp | 1 //===- LanaiDisassembler.cpp - Disassembler for Lanai -----------*- C++ -*-===//
10 // This file is part of the Lanai Disassembler.
16 #include "Lanai.h"
112 Instr.getOperand(2).setReg(Lanai::R0);
154 Lanai::R0, Lanai::R1, Lanai::PC, Lanai::R3, Lanai::SP, Lanai::FP
[all...] |
| /external/swiftshader/third_party/llvm-7.0/configs/windows/include/llvm/Config/ |
| AsmParsers.def | 32 LLVM_ASM_PARSER(Lanai)
|
| AsmPrinters.def | 32 LLVM_ASM_PRINTER(Lanai)
|
