| /external/llvm/utils/TableGen/ |
| CodeGenSchedule.h | 30 typedef std::vector<Record*> RecVec;
36 void splitSchedReadWrites(const RecVec &RWDefs,
37 RecVec &WriteDefs, RecVec &ReadDefs);
56 RecVec Aliases;
100 RecVec PredTerm;
143 RecVec InstRWs;
186 RecVec ItinDefList;
190 RecVec ItinRWDefs;
194 RecVec UnsupportedFeaturesDefs
[all...] |
| CodeGenSchedule.cpp | 139 RecVec ProcRecords = Records.getAllDerivedDefinitions("Processor");
179 static void scanSchedRW(Record *RWDef, RecVec &RWDefs,
186 RecVec Seq = RWDef->getValueAsListOfDefs("Writes");
192 RecVec Vars = RWDef->getValueAsListOfDefs("Variants");
195 RecVec Selected = (*VI)->getValueAsListOfDefs("Selected");
212 RecVec SWDefs, SRDefs;
217 RecVec RWs = SchedDef->getValueAsListOfDefs("SchedRW");
228 RecVec InstRWDefs = Records.getAllDerivedDefinitions("InstRW");
231 RecVec RWDefs = (*OI)->getValueAsListOfDefs("OperandReadWrites");
243 RecVec ItinRWDefs = Records.getAllDerivedDefinitions("ItinRW")
[all...] |
| SubtargetEmitter.cpp | 97 void ExpandProcResources(RecVec &PRVec, std::vector<int64_t> &Cycles,
617 RecVec ResUnits = PRDef->getValueAsListOfDefs("Resources");
753 void SubtargetEmitter::ExpandProcResources(RecVec &PRVec,
760 RecVec SubResources;
783 RecVec SuperResources = PR->getValueAsListOfDefs("Resources");
875 RecVec Matched = I->getValueAsListOfDefs("MatchedItinClasses");
[all...] |
| RegisterInfoEmitter.cpp | [all...] |
| CodeGenRegisters.cpp | 676 const SetTheory::RecVec *Elements = RegBank.getSets().expand(R);
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/ |
| PredicateExpander.h | 54 using RecVec = std::vector<Record *>;
68 void expandCheckPseudo(formatted_raw_ostream &OS, const RecVec &Opcodes);
69 void expandCheckOpcode(formatted_raw_ostream &OS, const RecVec &Opcodes);
71 const RecVec &Sequence, bool IsCheckAll);
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| CodeGenSchedule.h | 31 using RecVec = std::vector<Record*>;
54 RecVec Aliases;
98 RecVec PredTerm;
141 RecVec InstRWs;
218 RecVec ItinDefList;
222 RecVec ItinRWDefs;
226 RecVec UnsupportedFeaturesDefs;
229 RecVec WriteResDefs;
230 RecVec ReadAdvanceDefs;
233 RecVec ProcResourceDefs
[all...] |
| CodeGenSchedule.cpp | 229 RecVec Units = Records.getAllDerivedDefinitions("RetireControlUnit");
259 RecVec ProcRecords = Records.getAllDerivedDefinitions("Processor");
300 static void scanSchedRW(Record *RWDef, RecVec &RWDefs,
307 RecVec Seq = RWDef->getValueAsListOfDefs("Writes");
313 RecVec Vars = RWDef->getValueAsListOfDefs("Variants");
316 RecVec Selected = Variant->getValueAsListOfDefs("Selected");
333 RecVec SWDefs, SRDefs;
338 RecVec RWs = SchedDef->getValueAsListOfDefs("SchedRW");
349 RecVec InstRWDefs = Records.getAllDerivedDefinitions("InstRW");
352 RecVec RWDefs = InstRWDef->getValueAsListOfDefs("OperandReadWrites")
[all...] |
| PredicateExpander.cpp | 74 const RecVec &Opcodes) {
104 const RecVec &Opcodes) {
112 const RecVec &Sequence,
|
| SubtargetEmitter.cpp | 108 void ExpandProcResources(RecVec &PRVec, std::vector<int64_t> &Cycles,
206 RecVec ImpliesList = Feature->getValueAsListOfDefs("Implies");
241 RecVec FeatureList = Processor->getValueAsListOfDefs("Features");
273 RecVec StageList = ItinData->getValueAsListOfDefs("Stages");
286 RecVec UnitList = Stage->getValueAsListOfDefs("Units");
333 RecVec BypassList = ItinData->getValueAsListOfDefs("Bypasses");
364 RecVec FUs = ProcModel.ItinsDef->getValueAsListOfDefs("FU");
378 RecVec BPs = ProcModel.ItinsDef->getValueAsListOfDefs("BP");
603 RecVec ResUnits = PRDef->getValueAsListOfDefs("Resources");
799 RecVec ResUnits = PRDef->getValueAsListOfDefs("Resources")
[all...] |
| InstrInfoEmitter.cpp | 355 RecVec TIIPredicates = Records.getAllDerivedDefinitions("TIIPredicate");
404 RecVec TIIPredicates = Records.getAllDerivedDefinitions("TIIPredicate");
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| RegisterInfoEmitter.cpp | [all...] |
| CodeGenRegisters.cpp | 749 const SetTheory::RecVec *Elements = RegBank.getSets().expand(R);
[all...] |
| /external/llvm/include/llvm/TableGen/ |
| SetTheory.h | 65 typedef std::vector<Record*> RecVec;
94 typedef std::map<Record*, RecVec> ExpandMap;
136 const RecVec *expand(Record *Set);
|
| /external/swiftshader/third_party/LLVM/utils/TableGen/ |
| SetTheory.h | 64 typedef std::vector<Record*> RecVec;
88 typedef std::map<Record*, RecVec> ExpandMap;
130 const RecVec *expand(Record *Set);
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| SetTheory.cpp | 26 typedef SetTheory::RecVec RecVec;
181 if (const RecVec *Result = ST.expand(Rec))
228 if (const RecVec *Result = expand(Def->getDef()))
251 const RecVec *SetTheory::expand(Record *Set) {
263 RecVec &EltVec = Expansions[Set];
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| CodeGenRegisters.cpp | 277 const SetTheory::RecVec *Elements = RegBank.getSets().expand(R);
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/TableGen/ |
| SetTheory.h | 67 using RecVec = std::vector<Record *>;
98 using ExpandMap = std::map<Record *, RecVec>;
140 const RecVec *expand(Record *Set);
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| /external/llvm/lib/TableGen/ |
| SetTheory.cpp | 26 typedef SetTheory::RecVec RecVec;
220 if (const RecVec *Result = ST.expand(Rec))
275 if (const RecVec *Result = expand(Def->getDef()))
298 const RecVec *SetTheory::expand(Record *Set) {
313 RecVec &EltVec = Expansions[Set];
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/TableGen/ |
| SetTheory.cpp | 37 using RecVec = SetTheory::RecVec;
231 if (const RecVec *Result = ST.expand(Rec))
286 if (const RecVec *Result = expand(Def->getDef()))
309 const RecVec *SetTheory::expand(Record *Set) {
324 RecVec &EltVec = Expansions[Set];
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