| /external/llvm/lib/Target/X86/ |
| X86TargetTransformInfo.cpp | [all...] |
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorOps.cpp | 165 case ISD::SETCC:
223 else if (Node->getOpcode() == ISD::SETCC)
361 Ops[i] = DAG.getNode(ISD::SETCC, dl, TLI.getSetCCResultType(TmpEltVT),
|
| LegalizeVectorTypes.cpp | 64 case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break;
256 // Turn it into a scalar SETCC.
257 return DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, N->getOperand(2));
283 // Turn it into a scalar SETCC.
284 SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS,
435 case ISD::SETCC:
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/PTX/ |
| PTXISelLowering.cpp | 75 // select_cc => setcc
92 // customise setcc to use bitwise logic if possible
94 setOperationAction(ISD::SETCC, MVT::i1, Custom);
113 case ISD::SETCC:
148 assert(Op.getValueType() == MVT::i1 && "SetCC type must be 1-bit integer");
166 return DAG.getNode(ISD::SETCC, dl, MVT::i1, Op0, Op1, Op2);
|
| /external/llvm/lib/Target/Lanai/ |
| LanaiISelLowering.h | 41 // SETCC - Store the conditional code to a register.
42 SETCC,
|
| LanaiISelLowering.cpp | 73 setOperationAction(ISD::SETCC, MVT::i32, Custom);
178 case ISD::SETCC:
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.h | 50 /// SetCC - Operand 0 is condition code, and operand 1 is the flag
52 SETCC,
|
| MSP430ISelLowering.cpp | 108 setOperationAction(ISD::SETCC, MVT::i8, Custom);
109 setOperationAction(ISD::SETCC, MVT::i16, Custom);
188 case ISD::SETCC: return LowerSETCC(Op, DAG);
[all...] |
| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| ISDOpcodes.h | 328 // Much like the scalar select and setcc, each bit in the condition selects
338 // SetCC operator - This evaluates to a true value iff the condition is
344 SETCC,
492 // compare, rather than as a combined SetCC node. The operands in order are
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/MSP430/ |
| MSP430ISelLowering.h | 50 /// SetCC - Operand 0 is condition code, and operand 1 is the flag
52 SETCC,
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/ |
| LanaiISelLowering.h | 41 // SETCC - Store the conditional code to a register.
42 SETCC,
|
| LanaiISelLowering.cpp | 89 setOperationAction(ISD::SETCC, MVT::i32, Custom);
193 case ISD::SETCC:
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| X86TargetTransformInfo.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/X86/ |
| X86GenDAGISel.inc | [all...] |
| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 353 /// Much like the scalar select and setcc, each bit in the condition selects
366 /// SetCC operator - This evaluates to a true value iff the condition is
372 SETCC,
374 /// Like SetCC, ops #0 and #1 are the LHS and RHS operands to compare, but
578 /// compare, rather than as a combined SetCC node. The operands in order
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | 117 setOperationAction(ISD::SETCC, MVT::i32, Expand);
118 setOperationAction(ISD::SETCC, MVT::i64, Expand);
119 setOperationAction(ISD::SETCC, MVT::f32, Expand);
120 setOperationAction(ISD::SETCC, MVT::f64, Expand);
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 396 /// Much like the scalar select and setcc, each bit in the condition selects
409 /// SetCC operator - This evaluates to a true value iff the condition is
415 SETCC,
417 /// Like SetCC, ops #0 and #1 are the LHS and RHS operands to compare, but
611 /// compare, rather than as a combined SetCC node. The operands in order
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.h | 50 /// SetCC - Operand 0 is condition code, and operand 1 is the flag
52 SETCC,
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorTypes.cpp | 64 case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break;
337 if (Cond->getOpcode() == ISD::SETCC) {
429 // Turn it into a scalar SETCC.
430 SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS,
481 case ISD::SETCC:
561 /// result must be v1i1, so just convert to a scalar SETCC and wrap
576 // Turn it into a scalar SETCC.
577 SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS,
671 case ISD::SETCC:
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| X86ISelLowering.cpp | 182 // X86 is weird, it always uses i8 for shift amounts and setcc results.
424 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
425 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
426 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
427 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
428 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
429 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
432 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
725 setOperationAction(ISD::SETCC, (MVT::SimpleValueType)VT, Expand);
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorTypes.cpp | 66 case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break;
301 if (Cond->getOpcode() == ISD::SETCC) {
362 // Turn it into a scalar SETCC.
363 return DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, N->getOperand(2));
403 // Turn it into a scalar SETCC.
404 SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS,
614 case ISD::SETCC:
[all...] |
| LegalizeVectorOps.cpp | 294 case ISD::SETCC:
697 case ISD::SETCC:
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/Alpha/ |
| AlphaISelDAGToDAG.cpp | 302 case ISD::SETCC:
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| AMDGPUISelLowering.h | 346 // This is SETCC with the full mask result which is used for a compare with a
348 SETCC,
|
| /external/llvm/lib/Target/AMDGPU/ |
| SIISelLowering.cpp | 111 setOperationAction(ISD::SETCC, MVT::i1, Promote);
112 setOperationAction(ISD::SETCC, MVT::v2i1, Expand);
113 setOperationAction(ISD::SETCC, MVT::v4i1, Expand);
229 setTargetDAGCombine(ISD::SETCC);
541 // create setcc with i1 operands. We don't have instructions for i1 setcc.
542 if (VT == MVT::i1 && Op == ISD::SETCC)
[all...] |
