| /device/linaro/bootloader/arm-trusted-firmware/plat/rockchip/rk3399/drivers/m0/src/ |
| suspend.c | 27 mmio_setbits_32(M0_SCR, SCR_SLEEPDEEP_SHIFT);
|
| dram.c | 21 mmio_setbits_32(PMU_BASE + PMU_BUS_IDLE_REQ,
60 mmio_setbits_32(PHY_REG(0, 927), (1 << 22));
61 mmio_setbits_32(PHY_REG(1, 927), (1 << 22));
|
| /device/linaro/bootloader/arm-trusted-firmware/plat/mediatek/mt6795/ |
| scu.c | 14 mmio_setbits_32((uintptr_t)&mt6795_mcucfg->mp1_miscdbg,
17 mmio_setbits_32((uintptr_t)&mt6795_mcucfg->mp0_axi_config,
|
| bl31_plat_setup.c | 133 mmio_setbits_32((uintptr_t)&mt6795_mcucfg->mp1_miscdbg, MP1_AINACTS);
134 mmio_setbits_32((uintptr_t)&mt6795_mcucfg->mp1_clkenm_div,
140 mmio_setbits_32((uintptr_t)&mt6795_mcucfg->mp1_cpucfg,
144 mmio_setbits_32((uintptr_t)&mt6795_mcucfg->mp0_rv_addr[0].rv_addr_hw,
|
| plat_pm.c | 440 mmio_setbits_32(MTK_WDT_BASE, (MTK_WDT_MODE_KEY | MTK_WDT_MODE_EXTEN));
441 mmio_setbits_32(MTK_WDT_SWRST, MTK_WDT_SWRST_KEY);
|
| /device/linaro/bootloader/arm-trusted-firmware/plat/mediatek/mt8173/ |
| scu.c | 14 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp1_miscdbg,
17 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp0_axi_config,
|
| bl31_plat_setup.c | 53 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp1_miscdbg, MP1_AINACTS);
54 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp1_clkenm_div,
60 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp1_cpucfg,
64 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp0_rv_addr[0].rv_addr_hw,
68 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->bus_fabric_dcm_ctrl,
72 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->l2c_sram_ctrl,
74 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->cci_clk_ctrl,
|
| plat_pm.c | 685 mmio_setbits_32(MTK_WDT_BASE, (MTK_WDT_MODE_KEY | MTK_WDT_MODE_EXTEN));
686 mmio_setbits_32(MTK_WDT_SWRST, MTK_WDT_SWRST_KEY);
|
| /device/linaro/bootloader/arm-trusted-firmware/plat/rockchip/rk3399/drivers/m0/include/ |
| rk3399_mcu.h | 20 #define mmio_setbits_32(addr, set) \ macro
|
| /device/linaro/bootloader/arm-trusted-firmware/plat/mediatek/mt8173/drivers/mtcmos/ |
| mtcmos.c | 135 mmio_setbits_32(reg_pwr_con, PWR_ISO);
136 mmio_setbits_32(reg_pwr_con, SRAM_CKISO);
138 mmio_setbits_32(reg_l1_pdn, L1_PDN);
144 mmio_setbits_32(reg_pwr_con, PWR_CLK_DIS);
203 mmio_setbits_32(SPM_PCM_RESERVE, MTCMOS_CTRL_EN);
263 mmio_setbits_32(SPM_PCM_RESERVE2, power_ctrl);
|
| /device/linaro/bootloader/arm-trusted-firmware/include/lib/ |
| mmio.h | 57 static inline void mmio_setbits_32(uintptr_t addr, uint32_t set) function
|
| /device/linaro/bootloader/arm-trusted-firmware/plat/rockchip/rk3399/drivers/pmu/ |
| m0_ctl.c | 33 mmio_setbits_32(PMUCRU_BASE + PMUCRU_GATEDIS_CON0, 0x02);
|
| pmu.c | 397 mmio_setbits_32(PMU_BASE + PMU_SFT_CON, BIT(L2_FLUSH_REQ_CLUSTER_B));
428 mmio_setbits_32(PMU_BASE + PMU_SFT_CON, BIT(ACINACTM_CLUSTER_B_CFG));
872 mmio_setbits_32(PMU_BASE + PMU_WKUP_CFG4, BIT(PMU_GPIO_WKUP_EN));
882 mmio_setbits_32(PMU_BASE + PMU_BUS_CLR, hw_idle);
[all...] |
| /device/linaro/bootloader/arm-trusted-firmware/plat/socionext/uniphier/ |
| uniphier_psci.c | 74 mmio_setbits_32(UNIPHIER_SLFRSTCTL, UNIPHIER_SLFRSTCTL_RST);
|
| /device/linaro/bootloader/arm-trusted-firmware/plat/hisilicon/hikey960/ |
| hikey960_bl1_setup.c | 539 mmio_setbits_32(UFS_SYS_PHY_CLK_CTRL_REG, BIT_SYSCTRL_REF_CLOCK_EN);
545 mmio_setbits_32(UFS_SYS_PSW_POWER_CTRL_REG, BIT_UFS_PSW_MTCMOS_EN);
547 mmio_setbits_32(UFS_SYS_HC_LP_CTRL_REG, BIT_SYSCTRL_PWR_READY);
562 mmio_setbits_32(UFS_SYS_CLOCK_GATE_BYPASS_REG,
564 mmio_setbits_32(UFS_SYS_UFS_SYSCTRL_REG, MASK_UFS_SYSCTRL_BYPASS);
566 mmio_setbits_32(UFS_SYS_PSW_CLK_CTRL_REG, BIT_SYSCTRL_PSW_CLK_EN);
571 mmio_setbits_32(UFS_SYS_RESET_CTRL_EN_REG, BIT_SYSCTRL_LP_RESET_N);
615 mmio_setbits_32(CRG_PERRSTDIS4_REG, 1);
|
| /device/linaro/bootloader/arm-trusted-firmware/plat/rockchip/rk3399/drivers/dram/ |
| suspend.c | 194 mmio_setbits_32(PHY_REG(ch, 927), (1 << 22));
471 mmio_setbits_32(CTL_REG(i, 276), 1 << 17);
512 mmio_setbits_32(PI_REG(ch, 0), START);
513 mmio_setbits_32(CTL_REG(ch, 0), START);
582 mmio_setbits_32(CTL_REG(0, 68), PWRUP_SREFRESH_EXIT);
583 mmio_setbits_32(CTL_REG(1, 68), PWRUP_SREFRESH_EXIT);
587 mmio_setbits_32(PMU_BASE + PMU_PWRMODE_CON, (1 << 19));
589 mmio_setbits_32(PMU_BASE + PMU_PWRMODE_CON, (1 << 23));
|
| dfs.c | 635 mmio_setbits_32(CTL_REG(i, 213), 1 << 16);
884 mmio_setbits_32(CTL_REG(i, 213), (1 << 24));
[all...] |
| /device/linaro/bootloader/arm-trusted-firmware/plat/hisilicon/hikey960/drivers/pwrc/ |
| hisi_pwrc.c | 140 mmio_setbits_32(CPUIDLE_FLAG_REG(cluster), BIT(core));
207 mmio_setbits_32(REG_SCBAKDATA3_OFFSET, flag);
|
| /device/linaro/bootloader/arm-trusted-firmware/plat/mediatek/mt8173/drivers/spm/ |
| spm.c | 192 mmio_setbits_32(SPM_PCM_CON1, CON1_CFG_KEY);
247 mmio_setbits_32(SPM_PCM_CON1, CON1_CFG_KEY | CON1_IM_SLAVE);
|
| spm_suspend.c | 282 mmio_setbits_32(ARMCA15PLL_PWR_CON0, ARMCA15PLL_PWR_ON);
284 mmio_setbits_32(ARMCA15PLL_CON0, ARMCA15PLL_EN);
290 mmio_setbits_32(ARMCA15PLL_PWR_CON0, ARMCA15PLL_ISO_EN);
|
| spm_mcdi.c | 254 mmio_setbits_32(SPM_CLK_CON, CC_DISABLE_DORM_PWR);
420 mmio_setbits_32(SPM_PCM_RESERVE,
430 mmio_setbits_32(SPM_PCM_RESERVE,
|
| /device/linaro/bootloader/arm-trusted-firmware/plat/rockchip/rk3328/drivers/pmu/ |
| pmu.c | 506 mmio_setbits_32(PMU_BASE + PMU_SFT_CON, BIT(0));
511 mmio_setbits_32(PMU_BASE + PMU_SFT_CON, BIT(2));
550 mmio_setbits_32(DDR_UPCTL_BASE + DDR_PCTL2_PWRCTL,
|
| /device/linaro/bootloader/arm-trusted-firmware/plat/rockchip/rk3399/drivers/gpio/ |
| rk3399_gpio.c | 255 mmio_setbits_32(gpio_port[port] + SWPORTA_DDR, !direction << num);
|
| /device/linaro/bootloader/arm-trusted-firmware/drivers/ufs/ |
| ufs.c | 409 mmio_setbits_32(ufs_params.reg_base + UTRLDBR, 1 << slot);
|
