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      1 /* SPDX-License-Identifier: GPL-2.0+ */
      2 /*
      3  * Copyright (C) 2011 Andes Technology Corporation
      4  * Shawn Lin, Andes Technology Corporation <nobuhiro (at) andestech.com>
      5  * Macpaul Lin, Andes Technology Corporation <macpaul (at) andestech.com>
      6  */
      7 
      8 .pic
      9 
     10 .text
     11 
     12 #include <common.h>
     13 #include <config.h>
     14 
     15 #include <asm/macro.h>
     16 #include <generated/asm-offsets.h>
     17 
     18 /*
     19  * parameters for the SDRAM controller
     20  */
     21 #define SDMC_TP1_A		(CONFIG_FTSDMC021_BASE + FTSDMC021_TP1)
     22 #define SDMC_TP2_A		(CONFIG_FTSDMC021_BASE + FTSDMC021_TP2)
     23 #define SDMC_CR1_A		(CONFIG_FTSDMC021_BASE + FTSDMC021_CR1)
     24 #define SDMC_CR2_A		(CONFIG_FTSDMC021_BASE + FTSDMC021_CR2)
     25 #define SDMC_B0_BSR_A		(CONFIG_FTSDMC021_BASE + FTSDMC021_BANK0_BSR)
     26 #define SDMC_B1_BSR_A		(CONFIG_FTSDMC021_BASE + FTSDMC021_BANK1_BSR)
     27 
     28 #define SDMC_TP1_D		CONFIG_SYS_FTSDMC021_TP1
     29 #define SDMC_TP2_D		CONFIG_SYS_FTSDMC021_TP2
     30 #define SDMC_CR1_D		CONFIG_SYS_FTSDMC021_CR1
     31 #define SDMC_CR2_D		CONFIG_SYS_FTSDMC021_CR2
     32 
     33 #define SDMC_B0_BSR_D		CONFIG_SYS_FTSDMC021_BANK0_BSR
     34 #define SDMC_B1_BSR_D		CONFIG_SYS_FTSDMC021_BANK1_BSR
     35 
     36 
     37 /*
     38  * for Orca and Emerald
     39  */
     40 #define BOARD_ID_REG		0x104
     41 #define BOARD_ID_FAMILY_MASK 	0xfff000
     42 #define BOARD_ID_FAMILY_V5   	0x556000
     43 #define BOARD_ID_FAMILY_K7   	0x74b000
     44 
     45 /*
     46  * parameters for the static memory controller
     47  */
     48 #define SMC_BANK0_CR_A		(CONFIG_FTSMC020_BASE + FTSMC020_BANK0_CR)
     49 #define SMC_BANK0_TPR_A		(CONFIG_FTSMC020_BASE + FTSMC020_BANK0_TPR)
     50 
     51 #define SMC_BANK0_CR_D		FTSMC020_BANK0_LOWLV_CONFIG
     52 #define SMC_BANK0_TPR_D		FTSMC020_BANK0_LOWLV_TIMING
     53 
     54 /*
     55  * parameters for the ahbc controller
     56  */
     57 #define AHBC_CR_A		(CONFIG_FTAHBC020S_BASE + FTAHBC020S_CR)
     58 #define AHBC_BSR6_A	(CONFIG_FTAHBC020S_BASE + FTAHBC020S_SLAVE_BSR_6)
     59 
     60 /*
     61  * for Orca and Emerald
     62  */
     63 #define AHBC_BSR4_A	(CONFIG_FTAHBC020S_BASE + FTAHBC020S_SLAVE_BSR_4)
     64 #define AHBC_BSR6_D		CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6
     65 
     66 /*
     67  * parameters for the pmu controoler
     68  */
     69 #define PMU_PDLLCR0_A		(CONFIG_FTPMU010_BASE + FTPMU010_PDLLCR0)
     70 
     71 /*
     72  * numeric 7 segment display
     73  */
     74 .macro	led, num
     75 	write32	CONFIG_DEBUG_LED, \num
     76 .endm
     77 
     78 /*
     79  * Waiting for SDRAM to set up
     80  */
     81 .macro	wait_sdram
     82 	li	$r0, CONFIG_FTSDMC021_BASE
     83 1:
     84 	lwi	$r1, [$r0+FTSDMC021_CR2]
     85 	bnez	$r1, 1b
     86 .endm
     87 
     88 .globl	mem_init
     89 mem_init:
     90 	move	$r11, $lp
     91 
     92 	/*
     93 	 * mem_init:
     94 	 *	There are 2 bank connected to FTSMC020 on AG101
     95 	 *	BANK0: FLASH/ROM (SW5, J16), BANK1: OnBoard SDRAM.
     96 	 *	we need to set onboard SDRAM before remap and relocation.
     97 	 */
     98 	led	0x01
     99 
    100   /*
    101    * for Orca and Emerald
    102    * disable write protection and reset bank size
    103    */
    104 	li	$r0, SMC_BANK0_CR_A
    105 	lwi $r1, [$r0+#0x00]
    106 	ori $r1, $r1, 0x8f0
    107 	xori $r1, $r1, 0x8f0
    108 	/* check board */
    109 	li      $r3, CONFIG_FTPMU010_BASE + BOARD_ID_REG
    110   lwi     $r3, [$r3]
    111   li      $r4, BOARD_ID_FAMILY_MASK
    112   and     $r3, $r3, $r4
    113   li      $r4, BOARD_ID_FAMILY_K7
    114   xor     $r4, $r3, $r4
    115   beqz    $r4, use_flash_16bit_boot
    116 	/* 32-bit mode */
    117 use_flash_32bit_boot:
    118 	ori     $r1, $r1, 0x50
    119   li      $r2, 0x00151151
    120   j       sdram_b0_cr
    121 	/* 16-bit mode */
    122 use_flash_16bit_boot:
    123   ori     $r1, $r1, 0x60
    124   li      $r2, 0x00153153
    125 	/* SRAM bank0 config */
    126 sdram_b0_cr:
    127   swi     $r1, [$r0+#0x00]
    128   swi     $r2, [$r0+#0x04]
    129 
    130 	/* config AHB Controller */
    131 	led	0x02
    132 
    133 	/*
    134 	 * config PMU controller
    135 	 */
    136 	/* ftpmu010_dlldis_disable, must do it in lowleve_init */
    137 	led	0x03
    138 	setbf32	PMU_PDLLCR0_A, FTPMU010_PDLLCR0_DLLDIS		! 0x00010000
    139 
    140 	/*
    141 	 * config SDRAM controller
    142 	 */
    143 	led	0x04
    144 	write32	SDMC_TP1_A, SDMC_TP1_D				! 0x00011312
    145 	led	0x05
    146 	write32	SDMC_TP2_A, SDMC_TP2_D				! 0x00480180
    147 	led	0x06
    148 	write32	SDMC_CR1_A, SDMC_CR1_D				! 0x00002326
    149 
    150 	led	0x07
    151 	write32	SDMC_CR2_A, FTSDMC021_CR2_IPREC			! 0x00000010
    152 	wait_sdram
    153 
    154 	led	0x08
    155 	write32	SDMC_CR2_A, FTSDMC021_CR2_ISMR			! 0x00000004
    156 	wait_sdram
    157 
    158 	led	0x09
    159 	write32	SDMC_CR2_A, FTSDMC021_CR2_IREF			! 0x00000008
    160 	wait_sdram
    161 
    162 	led	0x0a
    163 	move	$lp, $r11
    164 	ret
    165 
    166 
    167 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
    168 
    169 .globl	lowlevel_init
    170 lowlevel_init:
    171 	move	$r10, $lp
    172 	led	0x10
    173 	jal	remap
    174 #if (defined(NDS32_EXT_FPU_DP) || defined(NDS32_EXT_FPU_SP))
    175 	led	0x1f
    176 	jal	enable_fpu
    177 #endif
    178 	led	0x20
    179 	ret	$r10
    180 
    181 remap:
    182 	move	$r11, $lp
    183 #ifdef __NDS32_N1213_43U1H__	/* NDS32 V0 ISA - AG101 Only */
    184 	bal	2f
    185 relo_base:
    186 	move	$r0, $lp
    187 #else
    188 relo_base:
    189 	mfusr	$r0, $pc
    190 #endif /* __NDS32_N1213_43U1H__ */
    191 
    192 	/* Remapping */
    193 	led	0x1a
    194 	write32	SDMC_B0_BSR_A, SDMC_B0_BSR_D		! 0x00001800
    195 	write32	SDMC_B1_BSR_A, SDMC_B1_BSR_D		! 0x00001880
    196 
    197 	/* clear empty BSR registers */
    198 	led	0x1b
    199 	li	$r4, CONFIG_FTSDMC021_BASE
    200 	li	$r5, 0x0
    201 	swi	$r5, [$r4 + FTSDMC021_BANK2_BSR]
    202 	swi	$r5, [$r4 + FTSDMC021_BANK3_BSR]
    203 
    204 #ifdef CONFIG_MEM_REMAP
    205 	/*
    206 	 * Copy ROM code to SDRAM base for memory remap layout.
    207 	 * This is not the real relocation, the real relocation is the function
    208 	 * relocate_code() is start.S which supports the systems is memory
    209 	 * remapped or not.
    210 	 */
    211 	/*
    212 	 * Doing memory remap is essential for preparing some non-OS or RTOS
    213 	 * applications.
    214 	 *
    215 	 * This is also a must on ADP-AG101 board.
    216 	 * The reason is because the ROM/FLASH circuit on PCB board.
    217 	 * AG101-A0 board has 2 jumpers MA17 and SW5 to configure which
    218 	 * ROM/FLASH is used to boot.
    219 	 *
    220 	 * When SW5 = "0101", MA17 = LO, the ROM is connected to BANK0,
    221 	 * and the FLASH is connected to BANK1.
    222 	 * When SW5 = "1010", MA17 = HI, the ROM is disabled (still at BANK0),
    223 	 * and the FLASH is connected to BANK0.
    224 	 * It will occur problem when doing flash probing if the flash is at
    225 	 * BANK0 (0x00000000) while memory remapping was skipped.
    226 	 *
    227 	 * Other board like ADP-AG101P may not enable this since there is only
    228 	 * a FLASH connected to bank0.
    229 	 */
    230 	led	0x11
    231    /*
    232     * for Orca and Emerald
    233     * read sdram base address automatically
    234     */
    235 	li	$r5, AHBC_BSR6_A
    236 	lwi $r8, [$r5]
    237 	li	$r4, 0xfff00000   /* r4 = bank6 base */
    238 	and $r4, $r4, $r8
    239 
    240 	la	$r5, _start@GOTOFF
    241 	la  $r6, _end@GOTOFF
    242 1:
    243 	lwi.p	$r7, [$r5], #4
    244 	swi.p	$r7, [$r4], #4
    245 	blt	$r5, $r6, 1b
    246 
    247 	/* set remap bit */
    248 	/*
    249 	 * MEM remap bit is operational
    250 	 * - use it to map writeable memory at 0x00000000, in place of flash
    251 	 * - before remap: flash/rom 0x00000000, sdram: 0x10000000-0x4fffffff
    252 	 * - after  remap: flash/rom 0x80000000, sdram: 0x00000000
    253 	 */
    254 	led	0x1c
    255 	write32 SDMC_B0_BSR_A, 0x00001000
    256 	write32 SDMC_B1_BSR_A, 0x00001200
    257 	li $r5, CONFIG_SYS_TEXT_BASE	/* flash base address */
    258 	add $r11, $r11, $r5	/* add flash address offset for ret */
    259 	add $r10, $r10, $r5
    260 	move $lp, $r11
    261 	setbf15	AHBC_CR_A, FTAHBC020S_CR_REMAP		! 0x1
    262 
    263   /*
    264    * for Orca and Emerald
    265    * extend sdram size from 256MB to 2GB
    266    */
    267 	li	$r5, AHBC_BSR6_A
    268 	lwi $r6, [$r5]
    269 	li  $r4, 0xfff0ffff
    270 	and $r6 ,$r4, $r6
    271 	li	$r4, 0x000b0000
    272 	or  $r6, $r4, $r6
    273 	swi	$r6, [$r5]
    274 
    275   /*
    276    * for Orca and Emerald
    277    * extend rom base from 256MB to 2GB
    278    */
    279 	li	$r4, AHBC_BSR4_A
    280 	lwi $r5, [$r4]
    281 	li	$r6, 0xffffff
    282 	and $r5, $r5, $r6
    283 	li  $r6, 0x80000000
    284 	or  $r5, $r5, $r6
    285 	swi $r5,	[$r4]
    286 #endif /* #ifdef CONFIG_MEM_REMAP */
    287 	move $lp, $r11
    288 2:
    289 	ret
    290 
    291 	/*
    292 	 * enable_fpu:
    293 	 *  Some of Andes CPU version support FPU coprocessor, if so,
    294 	 *  and toolchain support FPU instruction set, we should enable it.
    295 	 */
    296 #if (defined(NDS32_EXT_FPU_DP) || defined(NDS32_EXT_FPU_SP))
    297 enable_fpu:
    298 	mfsr    $r0, $CPU_VER     /* enable FPU if it exists */
    299 	srli    $r0, $r0, 3
    300 	andi    $r0, $r0, 1
    301 	beqz    $r0, 1f           /* skip if no COP */
    302 	mfsr    $r0, $FUCOP_EXIST
    303 	srli    $r0, $r0, 31
    304 	beqz    $r0, 1f           /* skip if no FPU */
    305 	mfsr    $r0, $FUCOP_CTL
    306 	ori     $r0, $r0, 1
    307 	mtsr    $r0, $FUCOP_CTL
    308 1:
    309 	ret
    310 #endif
    311 
    312 .globl show_led
    313 show_led:
    314     li      $r8, (CONFIG_DEBUG_LED)
    315     swi     $r7, [$r8]
    316     ret
    317 #endif /* #ifndef CONFIG_SKIP_LOWLEVEL_INIT */
    318