/external/eigen/Eigen/src/Geometry/ |
Umeyama.h | 134 TransformationMatrixType Rt = TransformationMatrixType::Identity(m+1,m+1); 143 Rt.block(0,0,m,m).noalias() = svd.matrixU() * S.asDiagonal() * svd.matrixV().transpose(); 151 Rt.col(m).head(m) = dst_mean; 152 Rt.col(m).head(m).noalias() -= c*Rt.topLeftCorner(m,m)*src_mean; 153 Rt.block(0,0,m,m) *= c; 157 Rt.col(m).head(m) = dst_mean; 158 Rt.col(m).head(m).noalias() -= Rt.topLeftCorner(m,m)*src_mean; 161 return Rt; [all...] |
/external/llvm/test/MC/ARM/ |
thumb2-ldrb-ldrh.s | 4 @ Thumb2 LDRS?[BH] are not valid when Rt == PC (these encodings are used for
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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/ |
thumb2-ldrb-ldrh.s | 4 @ Thumb2 LDRS?[BH] are not valid when Rt == PC (these encodings are used for
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ldrd-strd-gnu-thumb.s | 22 @ Rt is allowed to be odd for Thumb (but not ARM)
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/external/llvm/lib/Target/Hexagon/ |
HexagonAsmPrinter.cpp | 326 // Vector reduce complex multiply by scalar, Rt & 1 map to :hi else :lo 330 MCOperand &Rt = Inst.getOperand(3); 331 assert (Rt.isReg() && "Expected register and none was found"); 332 unsigned Reg = RI->getEncodingValue(Rt.getReg()); 337 Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI)); 341 MCOperand &Rt = Inst.getOperand(2); 342 assert (Rt.isReg() && "Expected register and none was found"); 343 unsigned Reg = RI->getEncodingValue(Rt.getReg()); 348 Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI)) [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/Disassembler/ |
MipsDisassembler.cpp | 669 // BOVC if rs >= rt 670 // BEQZALC if rs == 0 && rt != 0 671 // BEQC if rs < rt && rs != 0 674 InsnType Rt = fieldFromInstruction(insn, 16, 5); 678 if (Rs >= Rt) { 681 } else if (Rs != 0 && Rs < Rt) { 692 Rt))); 702 InsnType Rt = fieldFromInstruction(insn, 21, 5); 706 if (Rs >= Rt) { 709 Rt))); [all...] |
/external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
HexagonMCCompound.cpp | 207 MCOperand Rs, Rt; 217 Rt = L.getOperand(0); 222 CompoundInsn->addOperand(Rt); 228 Rt = L.getOperand(0); 234 CompoundInsn->addOperand(Rt); 243 Rt = L.getOperand(2); 249 CompoundInsn->addOperand(Rt); 256 Rt = L.getOperand(2); 262 CompoundInsn->addOperand(Rt); 269 Rt = L.getOperand(2) [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/MCTargetDesc/ |
HexagonMCCompound.cpp | 202 MCOperand Rs, Rt; 212 Rt = L.getOperand(0); 217 CompoundInsn->addOperand(Rt); 223 Rt = L.getOperand(0); 229 CompoundInsn->addOperand(Rt); 238 Rt = L.getOperand(2); 244 CompoundInsn->addOperand(Rt); 251 Rt = L.getOperand(2); 257 CompoundInsn->addOperand(Rt); 264 Rt = L.getOperand(2) [all...] |
/external/capstone/arch/Mips/ |
MipsDisassembler.c | 532 // BOVC if rs >= rt 533 // BEQZALC if rs == 0 && rt != 0 534 // BEQC if rs < rt && rs != 0 537 uint32_t Rt = fieldFromInstruction(insn, 16, 5); 541 if (Rs >= Rt) { 544 } else if (Rs != 0 && Rs < Rt) { 553 MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt)); 568 // BNVC if rs >= rt 569 // BNEZALC if rs == 0 && rt != 0 570 // BNEC if rs < rt && rs != [all...] |
/external/capstone/arch/AArch64/ |
AArch64Disassembler.c | 943 unsigned Rt = fieldFromInstruction(insn, 0, 5); 951 // Rt is an immediate in prefetch. 952 MCOperand_CreateImm0(Inst, Rt); 962 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 969 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 973 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); 977 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); 981 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); 985 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder); 989 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder) [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
HexagonAsmPrinter.cpp | 378 // Vector reduce complex multiply by scalar, Rt & 1 map to :hi else :lo 382 MCOperand &Rt = Inst.getOperand(3); 383 assert(Rt.isReg() && "Expected register and none was found"); 384 unsigned Reg = RI->getEncodingValue(Rt.getReg()); 389 Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI)); 393 MCOperand &Rt = Inst.getOperand(2); 394 assert(Rt.isReg() && "Expected register and none was found"); 395 unsigned Reg = RI->getEncodingValue(Rt.getReg()); 400 Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI)) [all...] |
/external/llvm/lib/Target/Mips/Disassembler/ |
MipsDisassembler.cpp | 598 // BOVC if rs >= rt 599 // BEQZALC if rs == 0 && rt != 0 600 // BEQC if rs < rt && rs != 0 603 InsnType Rt = fieldFromInstruction(insn, 16, 5); 607 if (Rs >= Rt) { 610 } else if (Rs != 0 && Rs < Rt) { 621 Rt))); 631 InsnType Rt = fieldFromInstruction(insn, 21, 5); 635 if (Rs >= Rt) { 638 Rt))); [all...] |
/external/swiftshader/third_party/subzero/src/ |
IceAssemblerMIPS32.cpp | 210 const IValueT Rt = encodeGPRegister(OpRt, "Rt", InsnName); 213 Opcode |= Rt << 16; 221 const IValueT Rt = encodeGPRegister(OpRt, "Rt", InsnName); 225 Opcode |= Rt << 16; 236 const IValueT Rt = encodeGPRegister(OpRt, "Rt", InsnName); 249 Opcode |= Rt << 16; 272 const IValueT Rt = encodeGPRegister(OpRt, "Rt", InsnName) [all...] |
IceAssemblerARM32.cpp | [all...] |
/external/capstone/arch/ARM/ |
ARMDisassembler.c | [all...] |
/external/llvm/lib/Target/AArch64/Disassembler/ |
AArch64Disassembler.cpp | [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/Disassembler/ |
AArch64Disassembler.cpp | [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/Disassembler/ |
ARMDisassembler.cpp | [all...] |
/external/llvm/lib/Target/ARM/Disassembler/ |
ARMDisassembler.cpp | [all...] |
/device/linaro/bootloader/edk2/ArmPkg/Library/ArmDisassemblerLib/ |
ThumbDisassembler.c | 149 { "LDR" , 0x6800, 0xf800, LOAD_STORE_FORMAT1 }, // LDR <Rt>, [<Rn> {,#<imm>}]
150 { "LDR" , 0x5800, 0xfe00, LOAD_STORE_FORMAT2 }, // STR <Rt>, [<Rn>, <Rm>]
152 { "LDR" , 0x9800, 0xf800, LOAD_STORE_FORMAT4 }, // LDR <Rt>, [SP, #<imm>]
154 { "LDRB" , 0x5c00, 0xfe00, LOAD_STORE_FORMAT2 }, // STR <Rt>, [<Rn>, <Rm>]
157 { "LDRSB" , 0x5600, 0xfe00, LOAD_STORE_FORMAT2 }, // STR <Rt>, [<Rn>, <Rm>]
187 { "STR" , 0x6000, 0xf800, LOAD_STORE_FORMAT1 }, // STR <Rt>, [<Rn> {,#<imm>}]
188 { "STR" , 0x5000, 0xfe00, LOAD_STORE_FORMAT2 }, // STR <Rt>, [<Rn>, <Rm>]
189 { "STR" , 0x9000, 0xf800, LOAD_STORE_FORMAT4 }, // STR <Rt>, [SP, #<imm>]
190 { "STRB" , 0x7000, 0xf800, LOAD_STORE_FORMAT1_B }, // STRB <Rt>, [<Rn>, #<imm5>]
191 { "STRB" , 0x5400, 0xfe00, LOAD_STORE_FORMAT2 }, // STRB <Rt>, [<Rn>, <Rm>] [all...] |
/external/llvm/test/MC/AArch64/ |
arm64-diags.s | 155 ; Load pair instructions where Rt==Rt2 and writeback load/store instructions 156 ; where Rt==Rn or Rt2==Rn are unpredicatable. 194 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt 197 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt 200 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt 203 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt 206 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt 209 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt 212 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt 215 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/ARM/Disassembler/ |
ARMDisassembler.cpp | [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/ |
RISCVMergeBaseOffset.cpp | 140 unsigned Rt = TailAdd.getOperand(2).getReg(); 141 unsigned Reg = Rs == GAReg ? Rt : Rs;
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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/ |
arm64-diags.s | 155 ; Load pair instructions where Rt==Rt2 and writeback load/store instructions 156 ; where Rt==Rn or Rt2==Rn are unpredicatable. 194 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt 197 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt 200 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt 203 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt 206 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt 209 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt 212 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt 215 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt [all...] |
/external/llvm/lib/Target/Hexagon/AsmParser/ |
HexagonAsmParser.cpp | [all...] |