| /external/llvm/lib/Target/AVR/ |
| AVRRegisterInfo.cpp | 45 AVRRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
|
| /external/llvm/lib/Target/Lanai/ |
| LanaiRegisterInfo.cpp | 283 LanaiRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
|
| /external/llvm/lib/Target/Sparc/ |
| SparcRegisterInfo.cpp | 45 SparcRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| SIRegisterInfo.h | 66 const uint32_t *getCallPreservedMask(const MachineFunction &MF,
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARC/ |
| ARCRegisterInfo.cpp | 229 ARCRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
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| ARCISelLowering.cpp | 347 TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv);
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AVR/ |
| AVRRegisterInfo.cpp | 45 AVRRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/ |
| LanaiRegisterInfo.cpp | 268 LanaiRegisterInfo::getCallPreservedMask(const MachineFunction & /*MF*/,
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/ |
| SparcRegisterInfo.cpp | 45 SparcRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
|
| /external/llvm/lib/Target/X86/ |
| X86RegisterInfo.cpp | 341 X86RegisterInfo::getCallPreservedMask(const MachineFunction &MF,
456 const uint32_t *RegMask = getCallPreservedMask(MF, CC);
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| X86RegisterInfo.cpp | 390 X86RegisterInfo::getCallPreservedMask(const MachineFunction &MF,
523 const uint32_t *RegMask = getCallPreservedMask(MF, CC);
|
| X86CallLowering.cpp | 396 TRI->getCallPreservedMask(MF, CallConv));
|
| /external/llvm/lib/Target/Mips/ |
| MipsRegisterInfo.cpp | 128 MipsRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| MipsRegisterInfo.cpp | 125 MipsRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
|
| MipsCallLowering.cpp | 331 MIB.addRegMask(TRI->getCallPreservedMask(MF, F.getCallingConv()));
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/ |
| SystemZRegisterInfo.cpp | 123 SystemZRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
|
| /external/llvm/include/llvm/Target/ |
| TargetRegisterInfo.h | 467 virtual const uint32_t *getCallPreservedMask(const MachineFunction &MF,
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64RegisterInfo.cpp | 74 AArch64RegisterInfo::getCallPreservedMask(const MachineFunction &MF,
105 // getCallPreservedMask but that additionally preserves the register used for
|
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| TargetRegisterInfo.h | 482 virtual const uint32_t *getCallPreservedMask(const MachineFunction &MF,
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| AArch64CallLowering.cpp | 368 MIB.addRegMask(TRI->getCallPreservedMask(MF, F.getCallingConv()));
|
| AArch64RegisterInfo.cpp | 89 AArch64RegisterInfo::getCallPreservedMask(const MachineFunction &MF,
124 // getCallPreservedMask but that additionally preserves the register used for
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| HexagonRegisterInfo.cpp | 136 const uint32_t *HexagonRegisterInfo::getCallPreservedMask(
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| ARMCallLowering.cpp | 523 .addRegMask(TRI->getCallPreservedMask(MF, CallConv));
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/ |
| RISCVISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMBaseRegisterInfo.cpp | 111 ARMBaseRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
145 // getCallPreservedMask but that additionally preserves the register used for
|
