| /external/mesa3d/src/gallium/auxiliary/postprocess/ |
| pp_mlaa.c | 118 mstencil.stencil[0].valuemask = mstencil.stencil[0].writemask = ~0;
|
| /external/mesa3d/src/gallium/auxiliary/tgsi/ |
| tgsi_exec.h | 52 ((INST)->Dst[0].Register.WriteMask & (1 << (CHAN)))
62 ((INST)->Dst[1].Register.WriteMask & (1 << (CHAN)))
153 unsigned writemask; member in struct:tgsi_buffer_params
|
| tgsi_ureg.h | 77 unsigned WriteMask : 4; /* TGSI_WRITEMASK_ */
513 * writemask.
519 dst.WriteMask == 0;
[all...] |
| /external/mesa3d/src/gallium/drivers/radeonsi/ |
| si_state.h | 90 uint8_t writemask[2]; member in struct:si_dsa_stencil_ref_part
|
| si_state.c | [all...] |
| /external/mesa3d/src/gallium/tests/graw/ |
| graw_util.h | 166 depthStencilAlpha.depth.writemask = 1;
|
| /external/mesa3d/src/gallium/drivers/svga/ |
| svga_tgsi_vgpu10.c | 447 * writes we need to mask the declaration usage or instruction writemask
455 * declaration or instruction writemask.
457 * \param writemask the declaration usage mask or instruction writemask
464 unsigned writemask, unsigned clip_reg_index)
472 writemask &= ((emit->key.clip_plane_enable >> shift) & 0xf);
474 return writemask;
858 unsigned writemask = reg->Register.WriteMask; local
934 /* the operand has a writemask */
2552 unsigned writemask = VGPU10_OPERAND_4_COMPONENT_MASK_ALL; local
3293 unsigned writemask = VGPU10_OPERAND_4_COMPONENT_MASK_X << comp; local
3335 unsigned writemask = VGPU10_OPERAND_4_COMPONENT_MASK_X << comp; local
[all...] |
| svga_context.h | 115 uint8_t writemask; member in struct:svga_blend_state::__anon33919
147 /* SVGA3D has one ref/mask/writemask triple shared between front &
|
| svga_tgsi_decl_sm30.c | 193 reg = writemask( dst(emit->ps_true_pos),
|
| /external/mesa3d/src/gallium/drivers/r300/ |
| r300_state.c | 698 if (state->depth.writemask) {
725 (state->stencil[0].writemask << R300_STENCILWRITEMASK_SHIFT);
743 (state->stencil[1].writemask << R300_STENCILWRITEMASK_SHIFT);
750 state->stencil[0].writemask != state->stencil[1].writemask);
[all...] |
| /external/mesa3d/src/gallium/drivers/r600/ |
| r600_state_common.c | 297 S_028430_STENCILWRITEMASK(a->state.writemask[0]));
301 S_028434_STENCILWRITEMASK_BF(a->state.writemask[1]));
320 ref.writemask[0] = dsa->writemask[0];
321 ref.writemask[1] = dsa->writemask[1];
343 ref.writemask[0] = dsa->writemask[0];
344 ref.writemask[1] = dsa->writemask[1]
[all...] |
| r600_pipe.h | 235 ubyte writemask[2]; member in struct:r600_stencil_ref
332 ubyte writemask[2]; member in struct:r600_dsa_state
[all...] |
| r600_state.c | 415 dsa->writemask[0] = state->stencil[0].writemask;
416 dsa->writemask[1] = state->stencil[1].writemask;
417 dsa->zwritemask = state->depth.writemask;
420 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
[all...] |
| /external/mesa3d/src/gallium/drivers/nouveau/nv50/ |
| nv50_state.c | 368 SB_DATA (so, cso->depth.writemask);
396 SB_DATA (so, cso->stencil[0].writemask);
412 SB_DATA (so, cso->stencil[1].writemask);
[all...] |
| /external/mesa3d/src/mesa/state_tracker/tests/ |
| test_glsl_to_tgsi_lifetime.cpp | 87 st_dst_reg create_dst_register(int dst_idx,int writemask);
[all...] |
| /external/mesa3d/src/intel/compiler/ |
| brw_vec4_reg_allocate.cpp | 327 ~prev_inst->dst.writemask) == 0;
|
| brw_vec4_generator.cpp | 60 /* Can't do writemask because math can't be align16. */
61 assert(dst.writemask == WRITEMASK_XYZW);
[all...] |
| brw_fs_nir.cpp | [all...] |
| /external/mesa3d/src/mesa/main/ |
| ffvertex_prog.c | 544 dst->WriteMask = mask ? mask : WRITEMASK_XYZW;
[all...] |
| /external/mesa3d/src/gallium/auxiliary/util/ |
| u_dump_state.c | 526 util_dump_member(stream, bool, &state->depth, writemask);
547 util_dump_member(stream, uint, &state->stencil[i], writemask);
|
| /external/mesa3d/src/gallium/drivers/trace/ |
| tr_dump_state.c | 357 trace_dump_member(bool, &state->depth, writemask);
373 trace_dump_member(uint, &state->stencil[i], writemask);
|
| /external/mesa3d/src/gallium/drivers/vc5/ |
| vc5_state.c | 186 config.stencil_write_mask = front->writemask;
203 config.stencil_write_mask = back->writemask;
[all...] |
| /external/virglrenderer/src/gallium/auxiliary/tgsi/ |
| tgsi_ureg.h | 76 unsigned WriteMask : 4; /* TGSI_WRITEMASK_ */
433 * writemask.
439 dst.WriteMask == 0;
[all...] |
| /external/mesa3d/src/amd/common/ |
| ac_nir_to_llvm.c | 2494 unsigned writemask = nir_intrinsic_write_mask(instr); local
3301 int writemask = instr->const_index[0] << comp; local
3390 int writemask = instr->const_index[0]; local
[all...] |
| /external/mesa3d/src/gallium/drivers/llvmpipe/ |
| lp_state_fs.c | 359 if (key->stencil[0].enabled && (key->stencil[0].writemask ||
361 key->stencil[1].writemask)))
373 if (!(key->depth.enabled && key->depth.writemask) &&
374 !(key->stencil[0].enabled && (key->stencil[0].writemask ||
376 key->stencil[1].writemask))))
[all...] |
