1 //===-- MipsSEInstrInfo.h - Mips32/64 Instruction Information ---*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the Mips32/64 implementation of the TargetInstrInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_MIPS_MIPSSEINSTRINFO_H 15 #define LLVM_LIB_TARGET_MIPS_MIPSSEINSTRINFO_H 16 17 #include "MipsInstrInfo.h" 18 #include "MipsSERegisterInfo.h" 19 20 namespace llvm { 21 22 class MipsSEInstrInfo : public MipsInstrInfo { 23 const MipsSERegisterInfo RI; 24 25 public: 26 explicit MipsSEInstrInfo(const MipsSubtarget &STI); 27 28 const MipsRegisterInfo &getRegisterInfo() const override; 29 30 /// isLoadFromStackSlot - If the specified machine instruction is a direct 31 /// load from a stack slot, return the virtual or physical register number of 32 /// the destination along with the FrameIndex of the loaded stack slot. If 33 /// not, return 0. This predicate must return 0 if the instruction has 34 /// any side effects other than loading from the stack slot. 35 unsigned isLoadFromStackSlot(const MachineInstr &MI, 36 int &FrameIndex) const override; 37 38 /// isStoreToStackSlot - If the specified machine instruction is a direct 39 /// store to a stack slot, return the virtual or physical register number of 40 /// the source reg along with the FrameIndex of the loaded stack slot. If 41 /// not, return 0. This predicate must return 0 if the instruction has 42 /// any side effects other than storing to the stack slot. 43 unsigned isStoreToStackSlot(const MachineInstr &MI, 44 int &FrameIndex) const override; 45 46 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 47 const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, 48 bool KillSrc) const override; 49 50 bool isCopyInstr(const MachineInstr &MI, const MachineOperand *&Src, 51 const MachineOperand *&Dest) const override; 52 53 void storeRegToStack(MachineBasicBlock &MBB, 54 MachineBasicBlock::iterator MI, 55 unsigned SrcReg, bool isKill, int FrameIndex, 56 const TargetRegisterClass *RC, 57 const TargetRegisterInfo *TRI, 58 int64_t Offset) const override; 59 60 void loadRegFromStack(MachineBasicBlock &MBB, 61 MachineBasicBlock::iterator MI, 62 unsigned DestReg, int FrameIndex, 63 const TargetRegisterClass *RC, 64 const TargetRegisterInfo *TRI, 65 int64_t Offset) const override; 66 67 bool expandPostRAPseudo(MachineInstr &MI) const override; 68 69 unsigned getOppositeBranchOpc(unsigned Opc) const override; 70 71 /// Adjust SP by Amount bytes. 72 void adjustStackPtr(unsigned SP, int64_t Amount, MachineBasicBlock &MBB, 73 MachineBasicBlock::iterator I) const override; 74 75 /// Emit a series of instructions to load an immediate. If NewImm is a 76 /// non-NULL parameter, the last instruction is not emitted, but instead 77 /// its immediate operand is returned in NewImm. 78 unsigned loadImmediate(int64_t Imm, MachineBasicBlock &MBB, 79 MachineBasicBlock::iterator II, const DebugLoc &DL, 80 unsigned *NewImm) const; 81 82 private: 83 unsigned getAnalyzableBrOpc(unsigned Opc) const override; 84 85 void expandRetRA(MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const; 86 87 void expandERet(MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const; 88 89 std::pair<bool, bool> compareOpndSize(unsigned Opc, 90 const MachineFunction &MF) const; 91 92 void expandPseudoMFHiLo(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 93 unsigned NewOpc) const; 94 95 void expandPseudoMTLoHi(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 96 unsigned LoOpc, unsigned HiOpc, 97 bool HasExplicitDef) const; 98 99 /// Expand pseudo Int-to-FP conversion instructions. 100 /// 101 /// For example, the following pseudo instruction 102 /// PseudoCVT_D32_W D2, A5 103 /// gets expanded into these two instructions: 104 /// MTC1 F4, A5 105 /// CVT_D32_W D2, F4 106 /// 107 /// We do this expansion post-RA to avoid inserting a floating point copy 108 /// instruction between MTC1 and CVT_D32_W. 109 void expandCvtFPInt(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 110 unsigned CvtOpc, unsigned MovOpc, bool IsI64) const; 111 112 void expandExtractElementF64(MachineBasicBlock &MBB, 113 MachineBasicBlock::iterator I, bool isMicroMips, 114 bool FP64) const; 115 void expandBuildPairF64(MachineBasicBlock &MBB, 116 MachineBasicBlock::iterator I, bool isMicroMips, 117 bool FP64) const; 118 void expandEhReturn(MachineBasicBlock &MBB, 119 MachineBasicBlock::iterator I) const; 120 }; 121 122 } 123 124 #endif 125
