1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2013 Keymile AG 4 * Valentin Longchamp <valentin.longchamp (at) keymile.com> 5 * 6 * Copyright 2011,2012 Freescale Semiconductor, Inc. 7 */ 8 9 #include <common.h> 10 #include <command.h> 11 #include <netdev.h> 12 #include <linux/compiler.h> 13 #include <asm/mmu.h> 14 #include <asm/processor.h> 15 #include <asm/cache.h> 16 #include <asm/immap_85xx.h> 17 #include <asm/fsl_law.h> 18 #include <asm/fsl_serdes.h> 19 #include <asm/fsl_portals.h> 20 #include <asm/fsl_liodn.h> 21 #include <fm_eth.h> 22 23 #include "../common/common.h" 24 #include "kmp204x.h" 25 26 static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN]; 27 28 int checkboard(void) 29 { 30 printf("Board: Keymile %s\n", CONFIG_KM_BOARD_NAME); 31 32 return 0; 33 } 34 35 /* I2C deblocking uses the algorithm defined in board/keymile/common/common.c 36 * 2 dedicated QRIO GPIOs externally pull the SCL and SDA lines 37 * For I2C only the low state is activly driven and high state is pulled-up 38 * by a resistor. Therefore the deblock GPIOs are used 39 * -> as an active output to drive a low state 40 * -> as an open-drain input to have a pulled-up high state 41 */ 42 43 /* QRIO GPIOs used for deblocking */ 44 #define DEBLOCK_PORT1 GPIO_A 45 #define DEBLOCK_SCL1 20 46 #define DEBLOCK_SDA1 21 47 48 /* By default deblock GPIOs are floating */ 49 static void i2c_deblock_gpio_cfg(void) 50 { 51 /* set I2C bus 1 deblocking GPIOs input, but 0 value for open drain */ 52 qrio_gpio_direction_input(DEBLOCK_PORT1, DEBLOCK_SCL1); 53 qrio_gpio_direction_input(DEBLOCK_PORT1, DEBLOCK_SDA1); 54 55 qrio_set_gpio(DEBLOCK_PORT1, DEBLOCK_SCL1, 0); 56 qrio_set_gpio(DEBLOCK_PORT1, DEBLOCK_SDA1, 0); 57 } 58 59 void set_sda(int state) 60 { 61 qrio_set_opendrain_gpio(DEBLOCK_PORT1, DEBLOCK_SDA1, state); 62 } 63 64 void set_scl(int state) 65 { 66 qrio_set_opendrain_gpio(DEBLOCK_PORT1, DEBLOCK_SCL1, state); 67 } 68 69 int get_sda(void) 70 { 71 return qrio_get_gpio(DEBLOCK_PORT1, DEBLOCK_SDA1); 72 } 73 74 int get_scl(void) 75 { 76 return qrio_get_gpio(DEBLOCK_PORT1, DEBLOCK_SCL1); 77 } 78 79 80 #define ZL30158_RST 8 81 #define BFTIC4_RST 0 82 #define RSTRQSR1_WDT_RR 0x00200000 83 #define RSTRQSR1_SW_RR 0x00100000 84 85 int board_early_init_f(void) 86 { 87 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 88 bool cpuwd_flag = false; 89 90 /* configure mode for uP reset request */ 91 qrio_uprstreq(UPREQ_CORE_RST); 92 93 /* board only uses the DDR_MCK0, so disable the DDR_MCK1/2/3 */ 94 setbits_be32(&gur->ddrclkdr, 0x001f000f); 95 96 /* set reset reason according CPU register */ 97 if ((gur->rstrqsr1 & (RSTRQSR1_WDT_RR | RSTRQSR1_SW_RR)) == 98 RSTRQSR1_WDT_RR) 99 cpuwd_flag = true; 100 101 qrio_cpuwd_flag(cpuwd_flag); 102 /* clear CPU bits by writing 1 */ 103 setbits_be32(&gur->rstrqsr1, RSTRQSR1_WDT_RR | RSTRQSR1_SW_RR); 104 105 /* set the BFTIC's prstcfg to reset at power-up and unit reset only */ 106 qrio_prstcfg(BFTIC4_RST, PRSTCFG_POWUP_UNIT_RST); 107 /* and enable WD on it */ 108 qrio_wdmask(BFTIC4_RST, true); 109 110 /* set the ZL30138's prstcfg to reset at power-up only */ 111 qrio_prstcfg(ZL30158_RST, PRSTCFG_POWUP_RST); 112 /* and take it out of reset as soon as possible (needed for Hooper) */ 113 qrio_prst(ZL30158_RST, false, false); 114 115 return 0; 116 } 117 118 int board_early_init_r(void) 119 { 120 int ret = 0; 121 /* Flush d-cache and invalidate i-cache of any FLASH data */ 122 flush_dcache(); 123 invalidate_icache(); 124 125 set_liodns(); 126 setup_qbman_portals(); 127 128 ret = trigger_fpga_config(); 129 if (ret) 130 printf("error triggering PCIe FPGA config\n"); 131 132 /* enable the Unit LED (red) & Boot LED (on) */ 133 qrio_set_leds(); 134 135 /* enable Application Buffer */ 136 qrio_enable_app_buffer(); 137 138 return ret; 139 } 140 141 unsigned long get_board_sys_clk(unsigned long dummy) 142 { 143 return 66666666; 144 } 145 146 #define ETH_FRONT_PHY_RST 15 147 #define QSFP2_RST 11 148 #define QSFP1_RST 10 149 #define ZL30343_RST 9 150 151 int misc_init_f(void) 152 { 153 /* configure QRIO pis for i2c deblocking */ 154 i2c_deblock_gpio_cfg(); 155 156 /* configure the front phy's prstcfg and take it out of reset */ 157 qrio_prstcfg(ETH_FRONT_PHY_RST, PRSTCFG_POWUP_UNIT_CORE_RST); 158 qrio_prst(ETH_FRONT_PHY_RST, false, false); 159 160 /* set the ZL30343 prstcfg to reset at power-up only */ 161 qrio_prstcfg(ZL30343_RST, PRSTCFG_POWUP_RST); 162 /* and enable the WD on it */ 163 qrio_wdmask(ZL30343_RST, true); 164 165 /* set the QSFPs' prstcfg to reset at power-up and unit rst only */ 166 qrio_prstcfg(QSFP1_RST, PRSTCFG_POWUP_UNIT_RST); 167 qrio_prstcfg(QSFP2_RST, PRSTCFG_POWUP_UNIT_RST); 168 169 /* and enable the WD on them */ 170 qrio_wdmask(QSFP1_RST, true); 171 qrio_wdmask(QSFP2_RST, true); 172 173 return 0; 174 } 175 176 #define NUM_SRDS_BANKS 2 177 178 int misc_init_r(void) 179 { 180 serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; 181 u32 expected[NUM_SRDS_BANKS] = {SRDS_PLLCR0_RFCK_SEL_100, 182 SRDS_PLLCR0_RFCK_SEL_125}; 183 unsigned int i; 184 185 /* check SERDES reference clocks */ 186 for (i = 0; i < NUM_SRDS_BANKS; i++) { 187 u32 actual = in_be32(®s->bank[i].pllcr0); 188 actual &= SRDS_PLLCR0_RFCK_SEL_MASK; 189 if (actual != expected[i]) { 190 printf("Warning: SERDES bank %u expects reference \ 191 clock %sMHz, but actual is %sMHz\n", i + 1, 192 serdes_clock_to_string(expected[i]), 193 serdes_clock_to_string(actual)); 194 } 195 } 196 197 ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN); 198 return 0; 199 } 200 201 #if defined(CONFIG_HUSH_INIT_VAR) 202 int hush_init_var(void) 203 { 204 ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN); 205 return 0; 206 } 207 #endif 208 209 #if defined(CONFIG_LAST_STAGE_INIT) 210 211 int last_stage_init(void) 212 { 213 #if defined(CONFIG_KMCOGE4) 214 /* on KMCOGE4, the BFTIC4 is on the LBAPP2 */ 215 struct bfticu_iomap *bftic4 = 216 (struct bfticu_iomap *)CONFIG_SYS_LBAPP2_BASE; 217 u8 dip_switch = in_8((u8 *)&(bftic4->mswitch)) & BFTICU_DIPSWITCH_MASK; 218 219 if (dip_switch != 0) { 220 /* start bootloader */ 221 puts("DIP: Enabled\n"); 222 env_set("actual_bank", "0"); 223 } 224 #endif 225 set_km_env(); 226 227 return 0; 228 } 229 #endif 230 231 #ifdef CONFIG_SYS_DPAA_FMAN 232 void fdt_fixup_fman_mac_addresses(void *blob) 233 { 234 int node, i, ret; 235 char *tmp, *end; 236 unsigned char mac_addr[6]; 237 238 /* get the mac addr from env */ 239 tmp = env_get("ethaddr"); 240 if (!tmp) { 241 printf("ethaddr env variable not defined\n"); 242 return; 243 } 244 for (i = 0; i < 6; i++) { 245 mac_addr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0; 246 if (tmp) 247 tmp = (*end) ? end+1 : end; 248 } 249 250 /* find the correct fdt ethernet path and correct it */ 251 node = fdt_path_offset(blob, "/soc/fman/ethernet@e8000"); 252 if (node < 0) { 253 printf("no /soc/fman/ethernet path offset\n"); 254 return; 255 } 256 ret = fdt_setprop(blob, node, "local-mac-address", &mac_addr, 6); 257 if (ret) { 258 printf("error setting local-mac-address property\n"); 259 return; 260 } 261 } 262 #endif 263 264 int ft_board_setup(void *blob, bd_t *bd) 265 { 266 phys_addr_t base; 267 phys_size_t size; 268 269 ft_cpu_setup(blob, bd); 270 271 base = env_get_bootm_low(); 272 size = env_get_bootm_size(); 273 274 fdt_fixup_memory(blob, (u64)base, (u64)size); 275 276 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) 277 fsl_fdt_fixup_dr_usb(blob, bd); 278 #endif 279 280 #ifdef CONFIG_PCI 281 pci_of_setup(blob, bd); 282 #endif 283 284 fdt_fixup_liodn(blob); 285 #ifdef CONFIG_SYS_DPAA_FMAN 286 fdt_fixup_fman_ethernet(blob); 287 fdt_fixup_fman_mac_addresses(blob); 288 #endif 289 290 return 0; 291 } 292 293 #if defined(CONFIG_POST) 294 295 /* DIC26_SELFTEST GPIO used to start factory test sw */ 296 #define SELFTEST_PORT GPIO_A 297 #define SELFTEST_PIN 31 298 299 int post_hotkeys_pressed(void) 300 { 301 qrio_gpio_direction_input(SELFTEST_PORT, SELFTEST_PIN); 302 return qrio_get_gpio(SELFTEST_PORT, SELFTEST_PIN); 303 } 304 #endif 305
