1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the interfaces that X86 uses to lower LLVM code into a 11 // selection DAG. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef X86ISELLOWERING_H 16 #define X86ISELLOWERING_H 17 18 #include "X86Subtarget.h" 19 #include "X86RegisterInfo.h" 20 #include "X86MachineFunctionInfo.h" 21 #include "llvm/Target/TargetLowering.h" 22 #include "llvm/Target/TargetOptions.h" 23 #include "llvm/CodeGen/FastISel.h" 24 #include "llvm/CodeGen/SelectionDAG.h" 25 #include "llvm/CodeGen/CallingConvLower.h" 26 27 namespace llvm { 28 namespace X86ISD { 29 // X86 Specific DAG Nodes 30 enum NodeType { 31 // Start the numbering where the builtin ops leave off. 32 FIRST_NUMBER = ISD::BUILTIN_OP_END, 33 34 /// BSF - Bit scan forward. 35 /// BSR - Bit scan reverse. 36 BSF, 37 BSR, 38 39 /// SHLD, SHRD - Double shift instructions. These correspond to 40 /// X86::SHLDxx and X86::SHRDxx instructions. 41 SHLD, 42 SHRD, 43 44 /// FAND - Bitwise logical AND of floating point values. This corresponds 45 /// to X86::ANDPS or X86::ANDPD. 46 FAND, 47 48 /// FOR - Bitwise logical OR of floating point values. This corresponds 49 /// to X86::ORPS or X86::ORPD. 50 FOR, 51 52 /// FXOR - Bitwise logical XOR of floating point values. This corresponds 53 /// to X86::XORPS or X86::XORPD. 54 FXOR, 55 56 /// FSRL - Bitwise logical right shift of floating point values. These 57 /// corresponds to X86::PSRLDQ. 58 FSRL, 59 60 /// CALL - These operations represent an abstract X86 call 61 /// instruction, which includes a bunch of information. In particular the 62 /// operands of these node are: 63 /// 64 /// #0 - The incoming token chain 65 /// #1 - The callee 66 /// #2 - The number of arg bytes the caller pushes on the stack. 67 /// #3 - The number of arg bytes the callee pops off the stack. 68 /// #4 - The value to pass in AL/AX/EAX (optional) 69 /// #5 - The value to pass in DL/DX/EDX (optional) 70 /// 71 /// The result values of these nodes are: 72 /// 73 /// #0 - The outgoing token chain 74 /// #1 - The first register result value (optional) 75 /// #2 - The second register result value (optional) 76 /// 77 CALL, 78 79 /// RDTSC_DAG - This operation implements the lowering for 80 /// readcyclecounter 81 RDTSC_DAG, 82 83 /// X86 compare and logical compare instructions. 84 CMP, COMI, UCOMI, 85 86 /// X86 bit-test instructions. 87 BT, 88 89 /// X86 SetCC. Operand 0 is condition code, and operand 1 is the EFLAGS 90 /// operand, usually produced by a CMP instruction. 91 SETCC, 92 93 // Same as SETCC except it's materialized with a sbb and the value is all 94 // one's or all zero's. 95 SETCC_CARRY, // R = carry_bit ? ~0 : 0 96 97 /// X86 FP SETCC, implemented with CMP{cc}SS/CMP{cc}SD. 98 /// Operands are two FP values to compare; result is a mask of 99 /// 0s or 1s. Generally DTRT for C/C++ with NaNs. 100 FSETCCss, FSETCCsd, 101 102 /// X86 MOVMSK{pd|ps}, extracts sign bits of two or four FP values, 103 /// result in an integer GPR. Needs masking for scalar result. 104 FGETSIGNx86, 105 106 /// X86 conditional moves. Operand 0 and operand 1 are the two values 107 /// to select from. Operand 2 is the condition code, and operand 3 is the 108 /// flag operand produced by a CMP or TEST instruction. It also writes a 109 /// flag result. 110 CMOV, 111 112 /// X86 conditional branches. Operand 0 is the chain operand, operand 1 113 /// is the block to branch if condition is true, operand 2 is the 114 /// condition code, and operand 3 is the flag operand produced by a CMP 115 /// or TEST instruction. 116 BRCOND, 117 118 /// Return with a flag operand. Operand 0 is the chain operand, operand 119 /// 1 is the number of bytes of stack to pop. 120 RET_FLAG, 121 122 /// REP_STOS - Repeat fill, corresponds to X86::REP_STOSx. 123 REP_STOS, 124 125 /// REP_MOVS - Repeat move, corresponds to X86::REP_MOVSx. 126 REP_MOVS, 127 128 /// GlobalBaseReg - On Darwin, this node represents the result of the popl 129 /// at function entry, used for PIC code. 130 GlobalBaseReg, 131 132 /// Wrapper - A wrapper node for TargetConstantPool, 133 /// TargetExternalSymbol, and TargetGlobalAddress. 134 Wrapper, 135 136 /// WrapperRIP - Special wrapper used under X86-64 PIC mode for RIP 137 /// relative displacements. 138 WrapperRIP, 139 140 /// MOVQ2DQ - Copies a 64-bit value from an MMX vector to the low word 141 /// of an XMM vector, with the high word zero filled. 142 MOVQ2DQ, 143 144 /// MOVDQ2Q - Copies a 64-bit value from the low word of an XMM vector 145 /// to an MMX vector. If you think this is too close to the previous 146 /// mnemonic, so do I; blame Intel. 147 MOVDQ2Q, 148 149 /// PEXTRB - Extract an 8-bit value from a vector and zero extend it to 150 /// i32, corresponds to X86::PEXTRB. 151 PEXTRB, 152 153 /// PEXTRW - Extract a 16-bit value from a vector and zero extend it to 154 /// i32, corresponds to X86::PEXTRW. 155 PEXTRW, 156 157 /// INSERTPS - Insert any element of a 4 x float vector into any element 158 /// of a destination 4 x floatvector. 159 INSERTPS, 160 161 /// PINSRB - Insert the lower 8-bits of a 32-bit value to a vector, 162 /// corresponds to X86::PINSRB. 163 PINSRB, 164 165 /// PINSRW - Insert the lower 16-bits of a 32-bit value to a vector, 166 /// corresponds to X86::PINSRW. 167 PINSRW, MMX_PINSRW, 168 169 /// PSHUFB - Shuffle 16 8-bit values within a vector. 170 PSHUFB, 171 172 /// ANDNP - Bitwise Logical AND NOT of Packed FP values. 173 ANDNP, 174 175 /// PSIGNB/W/D - Copy integer sign. 176 PSIGNB, PSIGNW, PSIGND, 177 178 /// PBLENDVB - Variable blend 179 PBLENDVB, 180 181 /// FMAX, FMIN - Floating point max and min. 182 /// 183 FMAX, FMIN, 184 185 /// FRSQRT, FRCP - Floating point reciprocal-sqrt and reciprocal 186 /// approximation. Note that these typically require refinement 187 /// in order to obtain suitable precision. 188 FRSQRT, FRCP, 189 190 // TLSADDR - Thread Local Storage. 191 TLSADDR, 192 193 // TLSCALL - Thread Local Storage. When calling to an OS provided 194 // thunk at the address from an earlier relocation. 195 TLSCALL, 196 197 // EH_RETURN - Exception Handling helpers. 198 EH_RETURN, 199 200 /// TC_RETURN - Tail call return. 201 /// operand #0 chain 202 /// operand #1 callee (register or absolute) 203 /// operand #2 stack adjustment 204 /// operand #3 optional in flag 205 TC_RETURN, 206 207 // VZEXT_MOVL - Vector move low and zero extend. 208 VZEXT_MOVL, 209 210 // VSHL, VSRL - Vector logical left / right shift. 211 VSHL, VSRL, 212 213 // CMPPD, CMPPS - Vector double/float comparison. 214 // CMPPD, CMPPS - Vector double/float comparison. 215 CMPPD, CMPPS, 216 217 // PCMP* - Vector integer comparisons. 218 PCMPEQB, PCMPEQW, PCMPEQD, PCMPEQQ, 219 PCMPGTB, PCMPGTW, PCMPGTD, PCMPGTQ, 220 221 // ADD, SUB, SMUL, etc. - Arithmetic operations with FLAGS results. 222 ADD, SUB, ADC, SBB, SMUL, 223 INC, DEC, OR, XOR, AND, 224 225 UMUL, // LOW, HI, FLAGS = umul LHS, RHS 226 227 // MUL_IMM - X86 specific multiply by immediate. 228 MUL_IMM, 229 230 // PTEST - Vector bitwise comparisons 231 PTEST, 232 233 // TESTP - Vector packed fp sign bitwise comparisons 234 TESTP, 235 236 // Several flavors of instructions with vector shuffle behaviors. 237 PALIGN, 238 PSHUFD, 239 PSHUFHW, 240 PSHUFLW, 241 PSHUFHW_LD, 242 PSHUFLW_LD, 243 SHUFPD, 244 SHUFPS, 245 MOVDDUP, 246 MOVSHDUP, 247 MOVSLDUP, 248 MOVSHDUP_LD, 249 MOVSLDUP_LD, 250 MOVLHPS, 251 MOVLHPD, 252 MOVHLPS, 253 MOVHLPD, 254 MOVLPS, 255 MOVLPD, 256 MOVSD, 257 MOVSS, 258 UNPCKLPS, 259 UNPCKLPD, 260 VUNPCKLPS, 261 VUNPCKLPD, 262 VUNPCKLPSY, 263 VUNPCKLPDY, 264 UNPCKHPS, 265 UNPCKHPD, 266 PUNPCKLBW, 267 PUNPCKLWD, 268 PUNPCKLDQ, 269 PUNPCKLQDQ, 270 PUNPCKHBW, 271 PUNPCKHWD, 272 PUNPCKHDQ, 273 PUNPCKHQDQ, 274 275 // VASTART_SAVE_XMM_REGS - Save xmm argument registers to the stack, 276 // according to %al. An operator is needed so that this can be expanded 277 // with control flow. 278 VASTART_SAVE_XMM_REGS, 279 280 // WIN_ALLOCA - Windows's _chkstk call to do stack probing. 281 WIN_ALLOCA, 282 283 // Memory barrier 284 MEMBARRIER, 285 MFENCE, 286 SFENCE, 287 LFENCE, 288 289 // ATOMADD64_DAG, ATOMSUB64_DAG, ATOMOR64_DAG, ATOMAND64_DAG, 290 // ATOMXOR64_DAG, ATOMNAND64_DAG, ATOMSWAP64_DAG - 291 // Atomic 64-bit binary operations. 292 ATOMADD64_DAG = ISD::FIRST_TARGET_MEMORY_OPCODE, 293 ATOMSUB64_DAG, 294 ATOMOR64_DAG, 295 ATOMXOR64_DAG, 296 ATOMAND64_DAG, 297 ATOMNAND64_DAG, 298 ATOMSWAP64_DAG, 299 300 // LCMPXCHG_DAG, LCMPXCHG8_DAG - Compare and swap. 301 LCMPXCHG_DAG, 302 LCMPXCHG8_DAG, 303 304 // VZEXT_LOAD - Load, scalar_to_vector, and zero extend. 305 VZEXT_LOAD, 306 307 // FNSTCW16m - Store FP control world into i16 memory. 308 FNSTCW16m, 309 310 /// FP_TO_INT*_IN_MEM - This instruction implements FP_TO_SINT with the 311 /// integer destination in memory and a FP reg source. This corresponds 312 /// to the X86::FIST*m instructions and the rounding mode change stuff. It 313 /// has two inputs (token chain and address) and two outputs (int value 314 /// and token chain). 315 FP_TO_INT16_IN_MEM, 316 FP_TO_INT32_IN_MEM, 317 FP_TO_INT64_IN_MEM, 318 319 /// FILD, FILD_FLAG - This instruction implements SINT_TO_FP with the 320 /// integer source in memory and FP reg result. This corresponds to the 321 /// X86::FILD*m instructions. It has three inputs (token chain, address, 322 /// and source type) and two outputs (FP value and token chain). FILD_FLAG 323 /// also produces a flag). 324 FILD, 325 FILD_FLAG, 326 327 /// FLD - This instruction implements an extending load to FP stack slots. 328 /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain 329 /// operand, ptr to load from, and a ValueType node indicating the type 330 /// to load to. 331 FLD, 332 333 /// FST - This instruction implements a truncating store to FP stack 334 /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a 335 /// chain operand, value to store, address, and a ValueType to store it 336 /// as. 337 FST, 338 339 /// VAARG_64 - This instruction grabs the address of the next argument 340 /// from a va_list. (reads and modifies the va_list in memory) 341 VAARG_64 342 343 // WARNING: Do not add anything in the end unless you want the node to 344 // have memop! In fact, starting from ATOMADD64_DAG all opcodes will be 345 // thought as target memory ops! 346 }; 347 } 348 349 /// Define some predicates that are used for node matching. 350 namespace X86 { 351 /// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand 352 /// specifies a shuffle of elements that is suitable for input to PSHUFD. 353 bool isPSHUFDMask(ShuffleVectorSDNode *N); 354 355 /// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand 356 /// specifies a shuffle of elements that is suitable for input to PSHUFD. 357 bool isPSHUFHWMask(ShuffleVectorSDNode *N); 358 359 /// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand 360 /// specifies a shuffle of elements that is suitable for input to PSHUFD. 361 bool isPSHUFLWMask(ShuffleVectorSDNode *N); 362 363 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand 364 /// specifies a shuffle of elements that is suitable for input to SHUFP*. 365 bool isSHUFPMask(ShuffleVectorSDNode *N); 366 367 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand 368 /// specifies a shuffle of elements that is suitable for input to MOVHLPS. 369 bool isMOVHLPSMask(ShuffleVectorSDNode *N); 370 371 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form 372 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef, 373 /// <2, 3, 2, 3> 374 bool isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N); 375 376 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand 377 /// specifies a shuffle of elements that is suitable for MOVLP{S|D}. 378 bool isMOVLPMask(ShuffleVectorSDNode *N); 379 380 /// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand 381 /// specifies a shuffle of elements that is suitable for MOVHP{S|D}. 382 /// as well as MOVLHPS. 383 bool isMOVLHPSMask(ShuffleVectorSDNode *N); 384 385 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand 386 /// specifies a shuffle of elements that is suitable for input to UNPCKL. 387 bool isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat = false); 388 389 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand 390 /// specifies a shuffle of elements that is suitable for input to UNPCKH. 391 bool isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat = false); 392 393 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form 394 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef, 395 /// <0, 0, 1, 1> 396 bool isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N); 397 398 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form 399 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef, 400 /// <2, 2, 3, 3> 401 bool isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N); 402 403 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand 404 /// specifies a shuffle of elements that is suitable for input to MOVSS, 405 /// MOVSD, and MOVD, i.e. setting the lowest element. 406 bool isMOVLMask(ShuffleVectorSDNode *N); 407 408 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand 409 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP. 410 bool isMOVSHDUPMask(ShuffleVectorSDNode *N); 411 412 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand 413 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP. 414 bool isMOVSLDUPMask(ShuffleVectorSDNode *N); 415 416 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand 417 /// specifies a shuffle of elements that is suitable for input to MOVDDUP. 418 bool isMOVDDUPMask(ShuffleVectorSDNode *N); 419 420 /// isPALIGNRMask - Return true if the specified VECTOR_SHUFFLE operand 421 /// specifies a shuffle of elements that is suitable for input to PALIGNR. 422 bool isPALIGNRMask(ShuffleVectorSDNode *N); 423 424 /// isVEXTRACTF128Index - Return true if the specified 425 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is 426 /// suitable for input to VEXTRACTF128. 427 bool isVEXTRACTF128Index(SDNode *N); 428 429 /// isVINSERTF128Index - Return true if the specified 430 /// INSERT_SUBVECTOR operand specifies a subvector insert that is 431 /// suitable for input to VINSERTF128. 432 bool isVINSERTF128Index(SDNode *N); 433 434 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle 435 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP* 436 /// instructions. 437 unsigned getShuffleSHUFImmediate(SDNode *N); 438 439 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle 440 /// the specified VECTOR_SHUFFLE mask with PSHUFHW instruction. 441 unsigned getShufflePSHUFHWImmediate(SDNode *N); 442 443 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle 444 /// the specified VECTOR_SHUFFLE mask with PSHUFLW instruction. 445 unsigned getShufflePSHUFLWImmediate(SDNode *N); 446 447 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle 448 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction. 449 unsigned getShufflePALIGNRImmediate(SDNode *N); 450 451 /// getExtractVEXTRACTF128Immediate - Return the appropriate 452 /// immediate to extract the specified EXTRACT_SUBVECTOR index 453 /// with VEXTRACTF128 instructions. 454 unsigned getExtractVEXTRACTF128Immediate(SDNode *N); 455 456 /// getInsertVINSERTF128Immediate - Return the appropriate 457 /// immediate to insert at the specified INSERT_SUBVECTOR index 458 /// with VINSERTF128 instructions. 459 unsigned getInsertVINSERTF128Immediate(SDNode *N); 460 461 /// isZeroNode - Returns true if Elt is a constant zero or a floating point 462 /// constant +0.0. 463 bool isZeroNode(SDValue Elt); 464 465 /// isOffsetSuitableForCodeModel - Returns true of the given offset can be 466 /// fit into displacement field of the instruction. 467 bool isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M, 468 bool hasSymbolicDisplacement = true); 469 470 471 /// isCalleePop - Determines whether the callee is required to pop its 472 /// own arguments. Callee pop is necessary to support tail calls. 473 bool isCalleePop(CallingConv::ID CallingConv, 474 bool is64Bit, bool IsVarArg, bool TailCallOpt); 475 } 476 477 //===--------------------------------------------------------------------===// 478 // X86TargetLowering - X86 Implementation of the TargetLowering interface 479 class X86TargetLowering : public TargetLowering { 480 public: 481 explicit X86TargetLowering(X86TargetMachine &TM); 482 483 virtual unsigned getJumpTableEncoding() const; 484 485 virtual MVT getShiftAmountTy(EVT LHSTy) const { return MVT::i8; } 486 487 virtual const MCExpr * 488 LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, 489 const MachineBasicBlock *MBB, unsigned uid, 490 MCContext &Ctx) const; 491 492 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC 493 /// jumptable. 494 virtual SDValue getPICJumpTableRelocBase(SDValue Table, 495 SelectionDAG &DAG) const; 496 virtual const MCExpr * 497 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, 498 unsigned JTI, MCContext &Ctx) const; 499 500 /// getStackPtrReg - Return the stack pointer register we are using: either 501 /// ESP or RSP. 502 unsigned getStackPtrReg() const { return X86StackPtr; } 503 504 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 505 /// function arguments in the caller parameter area. For X86, aggregates 506 /// that contains are placed at 16-byte boundaries while the rest are at 507 /// 4-byte boundaries. 508 virtual unsigned getByValTypeAlignment(Type *Ty) const; 509 510 /// getOptimalMemOpType - Returns the target specific optimal type for load 511 /// and store operations as a result of memset, memcpy, and memmove 512 /// lowering. If DstAlign is zero that means it's safe to destination 513 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it 514 /// means there isn't a need to check it against alignment requirement, 515 /// probably because the source does not need to be loaded. If 516 /// 'NonScalarIntSafe' is true, that means it's safe to return a 517 /// non-scalar-integer type, e.g. empty string source, constant, or loaded 518 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is 519 /// constant so it does not need to be loaded. 520 /// It returns EVT::Other if the type should be determined using generic 521 /// target-independent logic. 522 virtual EVT 523 getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign, 524 bool NonScalarIntSafe, bool MemcpyStrSrc, 525 MachineFunction &MF) const; 526 527 /// allowsUnalignedMemoryAccesses - Returns true if the target allows 528 /// unaligned memory accesses. of the specified type. 529 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const { 530 return true; 531 } 532 533 /// LowerOperation - Provide custom lowering hooks for some operations. 534 /// 535 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 536 537 /// ReplaceNodeResults - Replace the results of node with an illegal result 538 /// type with new values built out of custom code. 539 /// 540 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, 541 SelectionDAG &DAG) const; 542 543 544 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 545 546 /// isTypeDesirableForOp - Return true if the target has native support for 547 /// the specified value type and it is 'desirable' to use the type for the 548 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16 549 /// instruction encodings are longer and some i16 instructions are slow. 550 virtual bool isTypeDesirableForOp(unsigned Opc, EVT VT) const; 551 552 /// isTypeDesirable - Return true if the target has native support for the 553 /// specified value type and it is 'desirable' to use the type. e.g. On x86 554 /// i16 is legal, but undesirable since i16 instruction encodings are longer 555 /// and some i16 instructions are slow. 556 virtual bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const; 557 558 virtual MachineBasicBlock * 559 EmitInstrWithCustomInserter(MachineInstr *MI, 560 MachineBasicBlock *MBB) const; 561 562 563 /// getTargetNodeName - This method returns the name of a target specific 564 /// DAG node. 565 virtual const char *getTargetNodeName(unsigned Opcode) const; 566 567 /// getSetCCResultType - Return the ISD::SETCC ValueType 568 virtual MVT::SimpleValueType getSetCCResultType(EVT VT) const; 569 570 /// computeMaskedBitsForTargetNode - Determine which of the bits specified 571 /// in Mask are known to be either zero or one and return them in the 572 /// KnownZero/KnownOne bitsets. 573 virtual void computeMaskedBitsForTargetNode(const SDValue Op, 574 const APInt &Mask, 575 APInt &KnownZero, 576 APInt &KnownOne, 577 const SelectionDAG &DAG, 578 unsigned Depth = 0) const; 579 580 // ComputeNumSignBitsForTargetNode - Determine the number of bits in the 581 // operation that are sign bits. 582 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op, 583 unsigned Depth) const; 584 585 virtual bool 586 isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const; 587 588 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const; 589 590 virtual bool ExpandInlineAsm(CallInst *CI) const; 591 592 ConstraintType getConstraintType(const std::string &Constraint) const; 593 594 /// Examine constraint string and operand type and determine a weight value. 595 /// The operand object must already have been set up with the operand type. 596 virtual ConstraintWeight getSingleConstraintMatchWeight( 597 AsmOperandInfo &info, const char *constraint) const; 598 599 virtual const char *LowerXConstraint(EVT ConstraintVT) const; 600 601 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 602 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is 603 /// true it means one of the asm constraint of the inline asm instruction 604 /// being processed is 'm'. 605 virtual void LowerAsmOperandForConstraint(SDValue Op, 606 std::string &Constraint, 607 std::vector<SDValue> &Ops, 608 SelectionDAG &DAG) const; 609 610 /// getRegForInlineAsmConstraint - Given a physical register constraint 611 /// (e.g. {edx}), return the register number and the register class for the 612 /// register. This should only be used for C_Register constraints. On 613 /// error, this returns a register number of 0. 614 std::pair<unsigned, const TargetRegisterClass*> 615 getRegForInlineAsmConstraint(const std::string &Constraint, 616 EVT VT) const; 617 618 /// isLegalAddressingMode - Return true if the addressing mode represented 619 /// by AM is legal for this target, for a load/store of the specified type. 620 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty)const; 621 622 /// isTruncateFree - Return true if it's free to truncate a value of 623 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in 624 /// register EAX to i16 by referencing its sub-register AX. 625 virtual bool isTruncateFree(Type *Ty1, Type *Ty2) const; 626 virtual bool isTruncateFree(EVT VT1, EVT VT2) const; 627 628 /// isZExtFree - Return true if any actual instruction that defines a 629 /// value of type Ty1 implicit zero-extends the value to Ty2 in the result 630 /// register. This does not necessarily include registers defined in 631 /// unknown ways, such as incoming arguments, or copies from unknown 632 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this 633 /// does not necessarily apply to truncate instructions. e.g. on x86-64, 634 /// all instructions that define 32-bit values implicit zero-extend the 635 /// result out to 64 bits. 636 virtual bool isZExtFree(Type *Ty1, Type *Ty2) const; 637 virtual bool isZExtFree(EVT VT1, EVT VT2) const; 638 639 /// isNarrowingProfitable - Return true if it's profitable to narrow 640 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow 641 /// from i32 to i8 but not from i32 to i16. 642 virtual bool isNarrowingProfitable(EVT VT1, EVT VT2) const; 643 644 /// isFPImmLegal - Returns true if the target can instruction select the 645 /// specified FP immediate natively. If false, the legalizer will 646 /// materialize the FP immediate as a load from a constant pool. 647 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const; 648 649 /// isShuffleMaskLegal - Targets can use this to indicate that they only 650 /// support *some* VECTOR_SHUFFLE operations, those with specific masks. 651 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask 652 /// values are assumed to be legal. 653 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask, 654 EVT VT) const; 655 656 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is 657 /// used by Targets can use this to indicate if there is a suitable 658 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant 659 /// pool entry. 660 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask, 661 EVT VT) const; 662 663 /// ShouldShrinkFPConstant - If true, then instruction selection should 664 /// seek to shrink the FP constant of the specified type to a smaller type 665 /// in order to save space and / or reduce runtime. 666 virtual bool ShouldShrinkFPConstant(EVT VT) const { 667 // Don't shrink FP constpool if SSE2 is available since cvtss2sd is more 668 // expensive than a straight movsd. On the other hand, it's important to 669 // shrink long double fp constant since fldt is very slow. 670 return !X86ScalarSSEf64 || VT == MVT::f80; 671 } 672 673 const X86Subtarget* getSubtarget() const { 674 return Subtarget; 675 } 676 677 /// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is 678 /// computed in an SSE register, not on the X87 floating point stack. 679 bool isScalarFPTypeInSSEReg(EVT VT) const { 680 return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2 681 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1 682 } 683 684 /// createFastISel - This method returns a target specific FastISel object, 685 /// or null if the target does not support "fast" ISel. 686 virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo) const; 687 688 /// getStackCookieLocation - Return true if the target stores stack 689 /// protector cookies at a fixed offset in some non-standard address 690 /// space, and populates the address space and offset as 691 /// appropriate. 692 virtual bool getStackCookieLocation(unsigned &AddressSpace, unsigned &Offset) const; 693 694 SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot, 695 SelectionDAG &DAG) const; 696 697 protected: 698 std::pair<const TargetRegisterClass*, uint8_t> 699 findRepresentativeClass(EVT VT) const; 700 701 private: 702 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can 703 /// make the right decision when generating code for different targets. 704 const X86Subtarget *Subtarget; 705 const X86RegisterInfo *RegInfo; 706 const TargetData *TD; 707 708 /// X86StackPtr - X86 physical register used as stack ptr. 709 unsigned X86StackPtr; 710 711 /// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87 712 /// floating point ops. 713 /// When SSE is available, use it for f32 operations. 714 /// When SSE2 is available, use it for f64 operations. 715 bool X86ScalarSSEf32; 716 bool X86ScalarSSEf64; 717 718 /// LegalFPImmediates - A list of legal fp immediates. 719 std::vector<APFloat> LegalFPImmediates; 720 721 /// addLegalFPImmediate - Indicate that this x86 target can instruction 722 /// select the specified FP immediate natively. 723 void addLegalFPImmediate(const APFloat& Imm) { 724 LegalFPImmediates.push_back(Imm); 725 } 726 727 SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 728 CallingConv::ID CallConv, bool isVarArg, 729 const SmallVectorImpl<ISD::InputArg> &Ins, 730 DebugLoc dl, SelectionDAG &DAG, 731 SmallVectorImpl<SDValue> &InVals) const; 732 SDValue LowerMemArgument(SDValue Chain, 733 CallingConv::ID CallConv, 734 const SmallVectorImpl<ISD::InputArg> &ArgInfo, 735 DebugLoc dl, SelectionDAG &DAG, 736 const CCValAssign &VA, MachineFrameInfo *MFI, 737 unsigned i) const; 738 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg, 739 DebugLoc dl, SelectionDAG &DAG, 740 const CCValAssign &VA, 741 ISD::ArgFlagsTy Flags) const; 742 743 // Call lowering helpers. 744 745 /// IsEligibleForTailCallOptimization - Check whether the call is eligible 746 /// for tail call optimization. Targets which want to do tail call 747 /// optimization should implement this function. 748 bool IsEligibleForTailCallOptimization(SDValue Callee, 749 CallingConv::ID CalleeCC, 750 bool isVarArg, 751 bool isCalleeStructRet, 752 bool isCallerStructRet, 753 const SmallVectorImpl<ISD::OutputArg> &Outs, 754 const SmallVectorImpl<SDValue> &OutVals, 755 const SmallVectorImpl<ISD::InputArg> &Ins, 756 SelectionDAG& DAG) const; 757 bool IsCalleePop(bool isVarArg, CallingConv::ID CallConv) const; 758 SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr, 759 SDValue Chain, bool IsTailCall, bool Is64Bit, 760 int FPDiff, DebugLoc dl) const; 761 762 unsigned GetAlignedArgumentStackSize(unsigned StackSize, 763 SelectionDAG &DAG) const; 764 765 std::pair<SDValue,SDValue> FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, 766 bool isSigned) const; 767 768 SDValue LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl, 769 SelectionDAG &DAG) const; 770 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const; 771 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const; 772 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const; 773 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 774 SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) const; 775 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 776 SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) const; 777 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const; 778 SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const; 779 SDValue LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const; 780 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 781 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 782 SDValue LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl, 783 int64_t Offset, SelectionDAG &DAG) const; 784 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 785 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 786 SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const; 787 SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) const; 788 SDValue LowerBITCAST(SDValue op, SelectionDAG &DAG) const; 789 SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const; 790 SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const; 791 SDValue LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) const; 792 SDValue LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) const; 793 SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const; 794 SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const; 795 SDValue LowerFABS(SDValue Op, SelectionDAG &DAG) const; 796 SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG) const; 797 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const; 798 SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) const; 799 SDValue LowerToBT(SDValue And, ISD::CondCode CC, 800 DebugLoc dl, SelectionDAG &DAG) const; 801 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const; 802 SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) const; 803 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const; 804 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const; 805 SDValue LowerMEMSET(SDValue Op, SelectionDAG &DAG) const; 806 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const; 807 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const; 808 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const; 809 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const; 810 SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const; 811 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 812 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 813 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 814 SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const; 815 SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const; 816 SDValue LowerTRAMPOLINE(SDValue Op, SelectionDAG &DAG) const; 817 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const; 818 SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) const; 819 SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) const; 820 SDValue LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) const; 821 SDValue LowerShift(SDValue Op, SelectionDAG &DAG) const; 822 SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) const; 823 824 SDValue LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const; 825 SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const; 826 SDValue LowerREADCYCLECOUNTER(SDValue Op, SelectionDAG &DAG) const; 827 SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const; 828 SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const; 829 830 // Utility functions to help LowerVECTOR_SHUFFLE 831 SDValue LowerVECTOR_SHUFFLEv8i16(SDValue Op, SelectionDAG &DAG) const; 832 833 virtual SDValue 834 LowerFormalArguments(SDValue Chain, 835 CallingConv::ID CallConv, bool isVarArg, 836 const SmallVectorImpl<ISD::InputArg> &Ins, 837 DebugLoc dl, SelectionDAG &DAG, 838 SmallVectorImpl<SDValue> &InVals) const; 839 virtual SDValue 840 LowerCall(SDValue Chain, SDValue Callee, 841 CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, 842 const SmallVectorImpl<ISD::OutputArg> &Outs, 843 const SmallVectorImpl<SDValue> &OutVals, 844 const SmallVectorImpl<ISD::InputArg> &Ins, 845 DebugLoc dl, SelectionDAG &DAG, 846 SmallVectorImpl<SDValue> &InVals) const; 847 848 virtual SDValue 849 LowerReturn(SDValue Chain, 850 CallingConv::ID CallConv, bool isVarArg, 851 const SmallVectorImpl<ISD::OutputArg> &Outs, 852 const SmallVectorImpl<SDValue> &OutVals, 853 DebugLoc dl, SelectionDAG &DAG) const; 854 855 virtual bool isUsedByReturnOnly(SDNode *N) const; 856 857 virtual bool mayBeEmittedAsTailCall(CallInst *CI) const; 858 859 virtual EVT 860 getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT, 861 ISD::NodeType ExtendKind) const; 862 863 virtual bool 864 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, 865 bool isVarArg, 866 const SmallVectorImpl<ISD::OutputArg> &Outs, 867 LLVMContext &Context) const; 868 869 void ReplaceATOMIC_BINARY_64(SDNode *N, SmallVectorImpl<SDValue> &Results, 870 SelectionDAG &DAG, unsigned NewOp) const; 871 872 /// Utility function to emit string processing sse4.2 instructions 873 /// that return in xmm0. 874 /// This takes the instruction to expand, the associated machine basic 875 /// block, the number of args, and whether or not the second arg is 876 /// in memory or not. 877 MachineBasicBlock *EmitPCMP(MachineInstr *BInstr, MachineBasicBlock *BB, 878 unsigned argNum, bool inMem) const; 879 880 /// Utility functions to emit monitor and mwait instructions. These 881 /// need to make sure that the arguments to the intrinsic are in the 882 /// correct registers. 883 MachineBasicBlock *EmitMonitor(MachineInstr *MI, 884 MachineBasicBlock *BB) const; 885 MachineBasicBlock *EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const; 886 887 /// Utility function to emit atomic bitwise operations (and, or, xor). 888 /// It takes the bitwise instruction to expand, the associated machine basic 889 /// block, and the associated X86 opcodes for reg/reg and reg/imm. 890 MachineBasicBlock *EmitAtomicBitwiseWithCustomInserter( 891 MachineInstr *BInstr, 892 MachineBasicBlock *BB, 893 unsigned regOpc, 894 unsigned immOpc, 895 unsigned loadOpc, 896 unsigned cxchgOpc, 897 unsigned notOpc, 898 unsigned EAXreg, 899 TargetRegisterClass *RC, 900 bool invSrc = false) const; 901 902 MachineBasicBlock *EmitAtomicBit6432WithCustomInserter( 903 MachineInstr *BInstr, 904 MachineBasicBlock *BB, 905 unsigned regOpcL, 906 unsigned regOpcH, 907 unsigned immOpcL, 908 unsigned immOpcH, 909 bool invSrc = false) const; 910 911 /// Utility function to emit atomic min and max. It takes the min/max 912 /// instruction to expand, the associated basic block, and the associated 913 /// cmov opcode for moving the min or max value. 914 MachineBasicBlock *EmitAtomicMinMaxWithCustomInserter(MachineInstr *BInstr, 915 MachineBasicBlock *BB, 916 unsigned cmovOpc) const; 917 918 // Utility function to emit the low-level va_arg code for X86-64. 919 MachineBasicBlock *EmitVAARG64WithCustomInserter( 920 MachineInstr *MI, 921 MachineBasicBlock *MBB) const; 922 923 /// Utility function to emit the xmm reg save portion of va_start. 924 MachineBasicBlock *EmitVAStartSaveXMMRegsWithCustomInserter( 925 MachineInstr *BInstr, 926 MachineBasicBlock *BB) const; 927 928 MachineBasicBlock *EmitLoweredSelect(MachineInstr *I, 929 MachineBasicBlock *BB) const; 930 931 MachineBasicBlock *EmitLoweredWinAlloca(MachineInstr *MI, 932 MachineBasicBlock *BB) const; 933 934 MachineBasicBlock *EmitLoweredTLSCall(MachineInstr *MI, 935 MachineBasicBlock *BB) const; 936 937 MachineBasicBlock *emitLoweredTLSAddr(MachineInstr *MI, 938 MachineBasicBlock *BB) const; 939 940 /// Emit nodes that will be selected as "test Op0,Op0", or something 941 /// equivalent, for use with the given x86 condition code. 942 SDValue EmitTest(SDValue Op0, unsigned X86CC, SelectionDAG &DAG) const; 943 944 /// Emit nodes that will be selected as "cmp Op0,Op1", or something 945 /// equivalent, for use with the given x86 condition code. 946 SDValue EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, 947 SelectionDAG &DAG) const; 948 }; 949 950 namespace X86 { 951 FastISel *createFastISel(FunctionLoweringInfo &funcInfo); 952 } 953 } 954 955 #endif // X86ISELLOWERING_H 956
