1 // Copyright 2011 the V8 project authors. All rights reserved. 2 // Redistribution and use in source and binary forms, with or without 3 // modification, are permitted provided that the following conditions are 4 // met: 5 // 6 // * Redistributions of source code must retain the above copyright 7 // notice, this list of conditions and the following disclaimer. 8 // * Redistributions in binary form must reproduce the above 9 // copyright notice, this list of conditions and the following 10 // disclaimer in the documentation and/or other materials provided 11 // with the distribution. 12 // * Neither the name of Google Inc. nor the names of its 13 // contributors may be used to endorse or promote products derived 14 // from this software without specific prior written permission. 15 // 16 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 28 #ifndef V8_ARM_CONSTANTS_ARM_H_ 29 #define V8_ARM_CONSTANTS_ARM_H_ 30 31 // ARM EABI is required. 32 #if defined(__arm__) && !defined(__ARM_EABI__) 33 #error ARM EABI support is required. 34 #endif 35 36 // This means that interwork-compatible jump instructions are generated. We 37 // want to generate them on the simulator too so it makes snapshots that can 38 // be used on real hardware. 39 #if defined(__THUMB_INTERWORK__) || !defined(__arm__) 40 # define USE_THUMB_INTERWORK 1 41 #endif 42 43 #if defined(__ARM_ARCH_7A__) || \ 44 defined(__ARM_ARCH_7R__) || \ 45 defined(__ARM_ARCH_7__) 46 # define CAN_USE_ARMV7_INSTRUCTIONS 1 47 #endif 48 49 #if defined(__ARM_ARCH_6__) || \ 50 defined(__ARM_ARCH_6J__) || \ 51 defined(__ARM_ARCH_6K__) || \ 52 defined(__ARM_ARCH_6Z__) || \ 53 defined(__ARM_ARCH_6ZK__) || \ 54 defined(__ARM_ARCH_6T2__) || \ 55 defined(CAN_USE_ARMV7_INSTRUCTIONS) 56 # define CAN_USE_ARMV6_INSTRUCTIONS 1 57 #endif 58 59 #if defined(__ARM_ARCH_5T__) || \ 60 defined(__ARM_ARCH_5TE__) || \ 61 defined(CAN_USE_ARMV6_INSTRUCTIONS) 62 # define CAN_USE_ARMV5_INSTRUCTIONS 1 63 # define CAN_USE_THUMB_INSTRUCTIONS 1 64 #endif 65 66 // Simulator should support ARM5 instructions and unaligned access by default. 67 #if !defined(__arm__) 68 # define CAN_USE_ARMV5_INSTRUCTIONS 1 69 # define CAN_USE_THUMB_INSTRUCTIONS 1 70 71 # ifndef CAN_USE_UNALIGNED_ACCESSES 72 # define CAN_USE_UNALIGNED_ACCESSES 1 73 # endif 74 75 #endif 76 77 #if CAN_USE_UNALIGNED_ACCESSES 78 #define V8_TARGET_CAN_READ_UNALIGNED 1 79 #endif 80 81 // Using blx may yield better code, so use it when required or when available 82 #if defined(USE_THUMB_INTERWORK) || defined(CAN_USE_ARMV5_INSTRUCTIONS) 83 #define USE_BLX 1 84 #endif 85 86 namespace v8 { 87 namespace internal { 88 89 // Constant pool marker. 90 static const int kConstantPoolMarkerMask = 0xffe00000; 91 static const int kConstantPoolMarker = 0x0c000000; 92 static const int kConstantPoolLengthMask = 0x001ffff; 93 94 // Number of registers in normal ARM mode. 95 static const int kNumRegisters = 16; 96 97 // VFP support. 98 static const int kNumVFPSingleRegisters = 32; 99 static const int kNumVFPDoubleRegisters = 16; 100 static const int kNumVFPRegisters = 101 kNumVFPSingleRegisters + kNumVFPDoubleRegisters; 102 103 // PC is register 15. 104 static const int kPCRegister = 15; 105 static const int kNoRegister = -1; 106 107 // ----------------------------------------------------------------------------- 108 // Conditions. 109 110 // Defines constants and accessor classes to assemble, disassemble and 111 // simulate ARM instructions. 112 // 113 // Section references in the code refer to the "ARM Architecture Reference 114 // Manual" from July 2005 (available at http://www.arm.com/miscPDFs/14128.pdf) 115 // 116 // Constants for specific fields are defined in their respective named enums. 117 // General constants are in an anonymous enum in class Instr. 118 119 // Values for the condition field as defined in section A3.2 120 enum Condition { 121 kNoCondition = -1, 122 123 eq = 0 << 28, // Z set Equal. 124 ne = 1 << 28, // Z clear Not equal. 125 cs = 2 << 28, // C set Unsigned higher or same. 126 cc = 3 << 28, // C clear Unsigned lower. 127 mi = 4 << 28, // N set Negative. 128 pl = 5 << 28, // N clear Positive or zero. 129 vs = 6 << 28, // V set Overflow. 130 vc = 7 << 28, // V clear No overflow. 131 hi = 8 << 28, // C set, Z clear Unsigned higher. 132 ls = 9 << 28, // C clear or Z set Unsigned lower or same. 133 ge = 10 << 28, // N == V Greater or equal. 134 lt = 11 << 28, // N != V Less than. 135 gt = 12 << 28, // Z clear, N == V Greater than. 136 le = 13 << 28, // Z set or N != V Less then or equal 137 al = 14 << 28, // Always. 138 139 kSpecialCondition = 15 << 28, // Special condition (refer to section A3.2.1). 140 kNumberOfConditions = 16, 141 142 // Aliases. 143 hs = cs, // C set Unsigned higher or same. 144 lo = cc // C clear Unsigned lower. 145 }; 146 147 148 inline Condition NegateCondition(Condition cond) { 149 ASSERT(cond != al); 150 return static_cast<Condition>(cond ^ ne); 151 } 152 153 154 // Corresponds to transposing the operands of a comparison. 155 inline Condition ReverseCondition(Condition cond) { 156 switch (cond) { 157 case lo: 158 return hi; 159 case hi: 160 return lo; 161 case hs: 162 return ls; 163 case ls: 164 return hs; 165 case lt: 166 return gt; 167 case gt: 168 return lt; 169 case ge: 170 return le; 171 case le: 172 return ge; 173 default: 174 return cond; 175 }; 176 } 177 178 179 // ----------------------------------------------------------------------------- 180 // Instructions encoding. 181 182 // Instr is merely used by the Assembler to distinguish 32bit integers 183 // representing instructions from usual 32 bit values. 184 // Instruction objects are pointers to 32bit values, and provide methods to 185 // access the various ISA fields. 186 typedef int32_t Instr; 187 188 189 // Opcodes for Data-processing instructions (instructions with a type 0 and 1) 190 // as defined in section A3.4 191 enum Opcode { 192 AND = 0 << 21, // Logical AND. 193 EOR = 1 << 21, // Logical Exclusive OR. 194 SUB = 2 << 21, // Subtract. 195 RSB = 3 << 21, // Reverse Subtract. 196 ADD = 4 << 21, // Add. 197 ADC = 5 << 21, // Add with Carry. 198 SBC = 6 << 21, // Subtract with Carry. 199 RSC = 7 << 21, // Reverse Subtract with Carry. 200 TST = 8 << 21, // Test. 201 TEQ = 9 << 21, // Test Equivalence. 202 CMP = 10 << 21, // Compare. 203 CMN = 11 << 21, // Compare Negated. 204 ORR = 12 << 21, // Logical (inclusive) OR. 205 MOV = 13 << 21, // Move. 206 BIC = 14 << 21, // Bit Clear. 207 MVN = 15 << 21 // Move Not. 208 }; 209 210 211 // The bits for bit 7-4 for some type 0 miscellaneous instructions. 212 enum MiscInstructionsBits74 { 213 // With bits 22-21 01. 214 BX = 1 << 4, 215 BXJ = 2 << 4, 216 BLX = 3 << 4, 217 BKPT = 7 << 4, 218 219 // With bits 22-21 11. 220 CLZ = 1 << 4 221 }; 222 223 224 // Instruction encoding bits and masks. 225 enum { 226 H = 1 << 5, // Halfword (or byte). 227 S6 = 1 << 6, // Signed (or unsigned). 228 L = 1 << 20, // Load (or store). 229 S = 1 << 20, // Set condition code (or leave unchanged). 230 W = 1 << 21, // Writeback base register (or leave unchanged). 231 A = 1 << 21, // Accumulate in multiply instruction (or not). 232 B = 1 << 22, // Unsigned byte (or word). 233 N = 1 << 22, // Long (or short). 234 U = 1 << 23, // Positive (or negative) offset/index. 235 P = 1 << 24, // Offset/pre-indexed addressing (or post-indexed addressing). 236 I = 1 << 25, // Immediate shifter operand (or not). 237 238 B4 = 1 << 4, 239 B5 = 1 << 5, 240 B6 = 1 << 6, 241 B7 = 1 << 7, 242 B8 = 1 << 8, 243 B9 = 1 << 9, 244 B12 = 1 << 12, 245 B16 = 1 << 16, 246 B18 = 1 << 18, 247 B19 = 1 << 19, 248 B20 = 1 << 20, 249 B21 = 1 << 21, 250 B22 = 1 << 22, 251 B23 = 1 << 23, 252 B24 = 1 << 24, 253 B25 = 1 << 25, 254 B26 = 1 << 26, 255 B27 = 1 << 27, 256 B28 = 1 << 28, 257 258 // Instruction bit masks. 259 kCondMask = 15 << 28, 260 kALUMask = 0x6f << 21, 261 kRdMask = 15 << 12, // In str instruction. 262 kCoprocessorMask = 15 << 8, 263 kOpCodeMask = 15 << 21, // In data-processing instructions. 264 kImm24Mask = (1 << 24) - 1, 265 kOff12Mask = (1 << 12) - 1 266 }; 267 268 269 // ----------------------------------------------------------------------------- 270 // Addressing modes and instruction variants. 271 272 // Condition code updating mode. 273 enum SBit { 274 SetCC = 1 << 20, // Set condition code. 275 LeaveCC = 0 << 20 // Leave condition code unchanged. 276 }; 277 278 279 // Status register selection. 280 enum SRegister { 281 CPSR = 0 << 22, 282 SPSR = 1 << 22 283 }; 284 285 286 // Shifter types for Data-processing operands as defined in section A5.1.2. 287 enum ShiftOp { 288 LSL = 0 << 5, // Logical shift left. 289 LSR = 1 << 5, // Logical shift right. 290 ASR = 2 << 5, // Arithmetic shift right. 291 ROR = 3 << 5, // Rotate right. 292 293 // RRX is encoded as ROR with shift_imm == 0. 294 // Use a special code to make the distinction. The RRX ShiftOp is only used 295 // as an argument, and will never actually be encoded. The Assembler will 296 // detect it and emit the correct ROR shift operand with shift_imm == 0. 297 RRX = -1, 298 kNumberOfShifts = 4 299 }; 300 301 302 // Status register fields. 303 enum SRegisterField { 304 CPSR_c = CPSR | 1 << 16, 305 CPSR_x = CPSR | 1 << 17, 306 CPSR_s = CPSR | 1 << 18, 307 CPSR_f = CPSR | 1 << 19, 308 SPSR_c = SPSR | 1 << 16, 309 SPSR_x = SPSR | 1 << 17, 310 SPSR_s = SPSR | 1 << 18, 311 SPSR_f = SPSR | 1 << 19 312 }; 313 314 // Status register field mask (or'ed SRegisterField enum values). 315 typedef uint32_t SRegisterFieldMask; 316 317 318 // Memory operand addressing mode. 319 enum AddrMode { 320 // Bit encoding P U W. 321 Offset = (8|4|0) << 21, // Offset (without writeback to base). 322 PreIndex = (8|4|1) << 21, // Pre-indexed addressing with writeback. 323 PostIndex = (0|4|0) << 21, // Post-indexed addressing with writeback. 324 NegOffset = (8|0|0) << 21, // Negative offset (without writeback to base). 325 NegPreIndex = (8|0|1) << 21, // Negative pre-indexed with writeback. 326 NegPostIndex = (0|0|0) << 21 // Negative post-indexed with writeback. 327 }; 328 329 330 // Load/store multiple addressing mode. 331 enum BlockAddrMode { 332 // Bit encoding P U W . 333 da = (0|0|0) << 21, // Decrement after. 334 ia = (0|4|0) << 21, // Increment after. 335 db = (8|0|0) << 21, // Decrement before. 336 ib = (8|4|0) << 21, // Increment before. 337 da_w = (0|0|1) << 21, // Decrement after with writeback to base. 338 ia_w = (0|4|1) << 21, // Increment after with writeback to base. 339 db_w = (8|0|1) << 21, // Decrement before with writeback to base. 340 ib_w = (8|4|1) << 21, // Increment before with writeback to base. 341 342 // Alias modes for comparison when writeback does not matter. 343 da_x = (0|0|0) << 21, // Decrement after. 344 ia_x = (0|4|0) << 21, // Increment after. 345 db_x = (8|0|0) << 21, // Decrement before. 346 ib_x = (8|4|0) << 21, // Increment before. 347 348 kBlockAddrModeMask = (8|4|1) << 21 349 }; 350 351 352 // Coprocessor load/store operand size. 353 enum LFlag { 354 Long = 1 << 22, // Long load/store coprocessor. 355 Short = 0 << 22 // Short load/store coprocessor. 356 }; 357 358 359 // ----------------------------------------------------------------------------- 360 // Supervisor Call (svc) specific support. 361 362 // Special Software Interrupt codes when used in the presence of the ARM 363 // simulator. 364 // svc (formerly swi) provides a 24bit immediate value. Use bits 22:0 for 365 // standard SoftwareInterrupCode. Bit 23 is reserved for the stop feature. 366 enum SoftwareInterruptCodes { 367 // transition to C code 368 kCallRtRedirected= 0x10, 369 // break point 370 kBreakpoint= 0x20, 371 // stop 372 kStopCode = 1 << 23 373 }; 374 static const uint32_t kStopCodeMask = kStopCode - 1; 375 static const uint32_t kMaxStopCode = kStopCode - 1; 376 static const int32_t kDefaultStopCode = -1; 377 378 379 // Type of VFP register. Determines register encoding. 380 enum VFPRegPrecision { 381 kSinglePrecision = 0, 382 kDoublePrecision = 1 383 }; 384 385 386 // VFP FPSCR constants. 387 enum VFPConversionMode { 388 kFPSCRRounding = 0, 389 kDefaultRoundToZero = 1 390 }; 391 392 // This mask does not include the "inexact" or "input denormal" cumulative 393 // exceptions flags, because we usually don't want to check for it. 394 static const uint32_t kVFPExceptionMask = 0xf; 395 static const uint32_t kVFPInvalidOpExceptionBit = 1 << 0; 396 static const uint32_t kVFPOverflowExceptionBit = 1 << 2; 397 static const uint32_t kVFPUnderflowExceptionBit = 1 << 3; 398 static const uint32_t kVFPInexactExceptionBit = 1 << 4; 399 static const uint32_t kVFPFlushToZeroMask = 1 << 24; 400 401 static const uint32_t kVFPNConditionFlagBit = 1 << 31; 402 static const uint32_t kVFPZConditionFlagBit = 1 << 30; 403 static const uint32_t kVFPCConditionFlagBit = 1 << 29; 404 static const uint32_t kVFPVConditionFlagBit = 1 << 28; 405 406 407 // VFP rounding modes. See ARM DDI 0406B Page A2-29. 408 enum VFPRoundingMode { 409 RN = 0 << 22, // Round to Nearest. 410 RP = 1 << 22, // Round towards Plus Infinity. 411 RM = 2 << 22, // Round towards Minus Infinity. 412 RZ = 3 << 22, // Round towards zero. 413 414 // Aliases. 415 kRoundToNearest = RN, 416 kRoundToPlusInf = RP, 417 kRoundToMinusInf = RM, 418 kRoundToZero = RZ 419 }; 420 421 static const uint32_t kVFPRoundingModeMask = 3 << 22; 422 423 enum CheckForInexactConversion { 424 kCheckForInexactConversion, 425 kDontCheckForInexactConversion 426 }; 427 428 // ----------------------------------------------------------------------------- 429 // Hints. 430 431 // Branch hints are not used on the ARM. They are defined so that they can 432 // appear in shared function signatures, but will be ignored in ARM 433 // implementations. 434 enum Hint { no_hint }; 435 436 // Hints are not used on the arm. Negating is trivial. 437 inline Hint NegateHint(Hint ignored) { return no_hint; } 438 439 440 // ----------------------------------------------------------------------------- 441 // Specific instructions, constants, and masks. 442 // These constants are declared in assembler-arm.cc, as they use named registers 443 // and other constants. 444 445 446 // add(sp, sp, 4) instruction (aka Pop()) 447 extern const Instr kPopInstruction; 448 449 // str(r, MemOperand(sp, 4, NegPreIndex), al) instruction (aka push(r)) 450 // register r is not encoded. 451 extern const Instr kPushRegPattern; 452 453 // ldr(r, MemOperand(sp, 4, PostIndex), al) instruction (aka pop(r)) 454 // register r is not encoded. 455 extern const Instr kPopRegPattern; 456 457 // mov lr, pc 458 extern const Instr kMovLrPc; 459 // ldr rd, [pc, #offset] 460 extern const Instr kLdrPCMask; 461 extern const Instr kLdrPCPattern; 462 // blxcc rm 463 extern const Instr kBlxRegMask; 464 465 extern const Instr kBlxRegPattern; 466 467 extern const Instr kMovMvnMask; 468 extern const Instr kMovMvnPattern; 469 extern const Instr kMovMvnFlip; 470 extern const Instr kMovLeaveCCMask; 471 extern const Instr kMovLeaveCCPattern; 472 extern const Instr kMovwMask; 473 extern const Instr kMovwPattern; 474 extern const Instr kMovwLeaveCCFlip; 475 extern const Instr kCmpCmnMask; 476 extern const Instr kCmpCmnPattern; 477 extern const Instr kCmpCmnFlip; 478 extern const Instr kAddSubFlip; 479 extern const Instr kAndBicFlip; 480 481 // A mask for the Rd register for push, pop, ldr, str instructions. 482 extern const Instr kLdrRegFpOffsetPattern; 483 484 extern const Instr kStrRegFpOffsetPattern; 485 486 extern const Instr kLdrRegFpNegOffsetPattern; 487 488 extern const Instr kStrRegFpNegOffsetPattern; 489 490 extern const Instr kLdrStrInstrTypeMask; 491 extern const Instr kLdrStrInstrArgumentMask; 492 extern const Instr kLdrStrOffsetMask; 493 494 495 // ----------------------------------------------------------------------------- 496 // Instruction abstraction. 497 498 // The class Instruction enables access to individual fields defined in the ARM 499 // architecture instruction set encoding as described in figure A3-1. 500 // Note that the Assembler uses typedef int32_t Instr. 501 // 502 // Example: Test whether the instruction at ptr does set the condition code 503 // bits. 504 // 505 // bool InstructionSetsConditionCodes(byte* ptr) { 506 // Instruction* instr = Instruction::At(ptr); 507 // int type = instr->TypeValue(); 508 // return ((type == 0) || (type == 1)) && instr->HasS(); 509 // } 510 // 511 class Instruction { 512 public: 513 enum { 514 kInstrSize = 4, 515 kInstrSizeLog2 = 2, 516 kPCReadOffset = 8 517 }; 518 519 // Helper macro to define static accessors. 520 // We use the cast to char* trick to bypass the strict anti-aliasing rules. 521 #define DECLARE_STATIC_TYPED_ACCESSOR(return_type, Name) \ 522 static inline return_type Name(Instr instr) { \ 523 char* temp = reinterpret_cast<char*>(&instr); \ 524 return reinterpret_cast<Instruction*>(temp)->Name(); \ 525 } 526 527 #define DECLARE_STATIC_ACCESSOR(Name) DECLARE_STATIC_TYPED_ACCESSOR(int, Name) 528 529 // Get the raw instruction bits. 530 inline Instr InstructionBits() const { 531 return *reinterpret_cast<const Instr*>(this); 532 } 533 534 // Set the raw instruction bits to value. 535 inline void SetInstructionBits(Instr value) { 536 *reinterpret_cast<Instr*>(this) = value; 537 } 538 539 // Read one particular bit out of the instruction bits. 540 inline int Bit(int nr) const { 541 return (InstructionBits() >> nr) & 1; 542 } 543 544 // Read a bit field's value out of the instruction bits. 545 inline int Bits(int hi, int lo) const { 546 return (InstructionBits() >> lo) & ((2 << (hi - lo)) - 1); 547 } 548 549 // Read a bit field out of the instruction bits. 550 inline int BitField(int hi, int lo) const { 551 return InstructionBits() & (((2 << (hi - lo)) - 1) << lo); 552 } 553 554 // Static support. 555 556 // Read one particular bit out of the instruction bits. 557 static inline int Bit(Instr instr, int nr) { 558 return (instr >> nr) & 1; 559 } 560 561 // Read the value of a bit field out of the instruction bits. 562 static inline int Bits(Instr instr, int hi, int lo) { 563 return (instr >> lo) & ((2 << (hi - lo)) - 1); 564 } 565 566 567 // Read a bit field out of the instruction bits. 568 static inline int BitField(Instr instr, int hi, int lo) { 569 return instr & (((2 << (hi - lo)) - 1) << lo); 570 } 571 572 573 // Accessors for the different named fields used in the ARM encoding. 574 // The naming of these accessor corresponds to figure A3-1. 575 // 576 // Two kind of accessors are declared: 577 // - <Name>Field() will return the raw field, ie the field's bits at their 578 // original place in the instruction encoding. 579 // eg. if instr is the 'addgt r0, r1, r2' instruction, encoded as 0xC0810002 580 // ConditionField(instr) will return 0xC0000000. 581 // - <Name>Value() will return the field value, shifted back to bit 0. 582 // eg. if instr is the 'addgt r0, r1, r2' instruction, encoded as 0xC0810002 583 // ConditionField(instr) will return 0xC. 584 585 586 // Generally applicable fields 587 inline Condition ConditionValue() const { 588 return static_cast<Condition>(Bits(31, 28)); 589 } 590 inline Condition ConditionField() const { 591 return static_cast<Condition>(BitField(31, 28)); 592 } 593 DECLARE_STATIC_TYPED_ACCESSOR(Condition, ConditionValue); 594 DECLARE_STATIC_TYPED_ACCESSOR(Condition, ConditionField); 595 596 inline int TypeValue() const { return Bits(27, 25); } 597 598 inline int RnValue() const { return Bits(19, 16); } 599 DECLARE_STATIC_ACCESSOR(RnValue); 600 inline int RdValue() const { return Bits(15, 12); } 601 DECLARE_STATIC_ACCESSOR(RdValue); 602 603 inline int CoprocessorValue() const { return Bits(11, 8); } 604 // Support for VFP. 605 // Vn(19-16) | Vd(15-12) | Vm(3-0) 606 inline int VnValue() const { return Bits(19, 16); } 607 inline int VmValue() const { return Bits(3, 0); } 608 inline int VdValue() const { return Bits(15, 12); } 609 inline int NValue() const { return Bit(7); } 610 inline int MValue() const { return Bit(5); } 611 inline int DValue() const { return Bit(22); } 612 inline int RtValue() const { return Bits(15, 12); } 613 inline int PValue() const { return Bit(24); } 614 inline int UValue() const { return Bit(23); } 615 inline int Opc1Value() const { return (Bit(23) << 2) | Bits(21, 20); } 616 inline int Opc2Value() const { return Bits(19, 16); } 617 inline int Opc3Value() const { return Bits(7, 6); } 618 inline int SzValue() const { return Bit(8); } 619 inline int VLValue() const { return Bit(20); } 620 inline int VCValue() const { return Bit(8); } 621 inline int VAValue() const { return Bits(23, 21); } 622 inline int VBValue() const { return Bits(6, 5); } 623 inline int VFPNRegValue(VFPRegPrecision pre) { 624 return VFPGlueRegValue(pre, 16, 7); 625 } 626 inline int VFPMRegValue(VFPRegPrecision pre) { 627 return VFPGlueRegValue(pre, 0, 5); 628 } 629 inline int VFPDRegValue(VFPRegPrecision pre) { 630 return VFPGlueRegValue(pre, 12, 22); 631 } 632 633 // Fields used in Data processing instructions 634 inline int OpcodeValue() const { 635 return static_cast<Opcode>(Bits(24, 21)); 636 } 637 inline Opcode OpcodeField() const { 638 return static_cast<Opcode>(BitField(24, 21)); 639 } 640 inline int SValue() const { return Bit(20); } 641 // with register 642 inline int RmValue() const { return Bits(3, 0); } 643 DECLARE_STATIC_ACCESSOR(RmValue); 644 inline int ShiftValue() const { return static_cast<ShiftOp>(Bits(6, 5)); } 645 inline ShiftOp ShiftField() const { 646 return static_cast<ShiftOp>(BitField(6, 5)); 647 } 648 inline int RegShiftValue() const { return Bit(4); } 649 inline int RsValue() const { return Bits(11, 8); } 650 inline int ShiftAmountValue() const { return Bits(11, 7); } 651 // with immediate 652 inline int RotateValue() const { return Bits(11, 8); } 653 inline int Immed8Value() const { return Bits(7, 0); } 654 inline int Immed4Value() const { return Bits(19, 16); } 655 inline int ImmedMovwMovtValue() const { 656 return Immed4Value() << 12 | Offset12Value(); } 657 658 // Fields used in Load/Store instructions 659 inline int PUValue() const { return Bits(24, 23); } 660 inline int PUField() const { return BitField(24, 23); } 661 inline int BValue() const { return Bit(22); } 662 inline int WValue() const { return Bit(21); } 663 inline int LValue() const { return Bit(20); } 664 // with register uses same fields as Data processing instructions above 665 // with immediate 666 inline int Offset12Value() const { return Bits(11, 0); } 667 // multiple 668 inline int RlistValue() const { return Bits(15, 0); } 669 // extra loads and stores 670 inline int SignValue() const { return Bit(6); } 671 inline int HValue() const { return Bit(5); } 672 inline int ImmedHValue() const { return Bits(11, 8); } 673 inline int ImmedLValue() const { return Bits(3, 0); } 674 675 // Fields used in Branch instructions 676 inline int LinkValue() const { return Bit(24); } 677 inline int SImmed24Value() const { return ((InstructionBits() << 8) >> 8); } 678 679 // Fields used in Software interrupt instructions 680 inline SoftwareInterruptCodes SvcValue() const { 681 return static_cast<SoftwareInterruptCodes>(Bits(23, 0)); 682 } 683 684 // Test for special encodings of type 0 instructions (extra loads and stores, 685 // as well as multiplications). 686 inline bool IsSpecialType0() const { return (Bit(7) == 1) && (Bit(4) == 1); } 687 688 // Test for miscellaneous instructions encodings of type 0 instructions. 689 inline bool IsMiscType0() const { return (Bit(24) == 1) 690 && (Bit(23) == 0) 691 && (Bit(20) == 0) 692 && ((Bit(7) == 0)); } 693 694 // Test for a stop instruction. 695 inline bool IsStop() const { 696 return (TypeValue() == 7) && (Bit(24) == 1) && (SvcValue() >= kStopCode); 697 } 698 699 // Special accessors that test for existence of a value. 700 inline bool HasS() const { return SValue() == 1; } 701 inline bool HasB() const { return BValue() == 1; } 702 inline bool HasW() const { return WValue() == 1; } 703 inline bool HasL() const { return LValue() == 1; } 704 inline bool HasU() const { return UValue() == 1; } 705 inline bool HasSign() const { return SignValue() == 1; } 706 inline bool HasH() const { return HValue() == 1; } 707 inline bool HasLink() const { return LinkValue() == 1; } 708 709 // Decoding the double immediate in the vmov instruction. 710 double DoubleImmedVmov() const; 711 712 // Instructions are read of out a code stream. The only way to get a 713 // reference to an instruction is to convert a pointer. There is no way 714 // to allocate or create instances of class Instruction. 715 // Use the At(pc) function to create references to Instruction. 716 static Instruction* At(byte* pc) { 717 return reinterpret_cast<Instruction*>(pc); 718 } 719 720 721 private: 722 // Join split register codes, depending on single or double precision. 723 // four_bit is the position of the least-significant bit of the four 724 // bit specifier. one_bit is the position of the additional single bit 725 // specifier. 726 inline int VFPGlueRegValue(VFPRegPrecision pre, int four_bit, int one_bit) { 727 if (pre == kSinglePrecision) { 728 return (Bits(four_bit + 3, four_bit) << 1) | Bit(one_bit); 729 } 730 return (Bit(one_bit) << 4) | Bits(four_bit + 3, four_bit); 731 } 732 733 // We need to prevent the creation of instances of class Instruction. 734 DISALLOW_IMPLICIT_CONSTRUCTORS(Instruction); 735 }; 736 737 738 // Helper functions for converting between register numbers and names. 739 class Registers { 740 public: 741 // Return the name of the register. 742 static const char* Name(int reg); 743 744 // Lookup the register number for the name provided. 745 static int Number(const char* name); 746 747 struct RegisterAlias { 748 int reg; 749 const char* name; 750 }; 751 752 private: 753 static const char* names_[kNumRegisters]; 754 static const RegisterAlias aliases_[]; 755 }; 756 757 // Helper functions for converting between VFP register numbers and names. 758 class VFPRegisters { 759 public: 760 // Return the name of the register. 761 static const char* Name(int reg, bool is_double); 762 763 // Lookup the register number for the name provided. 764 // Set flag pointed by is_double to true if register 765 // is double-precision. 766 static int Number(const char* name, bool* is_double); 767 768 private: 769 static const char* names_[kNumVFPRegisters]; 770 }; 771 772 773 } } // namespace v8::internal 774 775 #endif // V8_ARM_CONSTANTS_ARM_H_ 776
