| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.h | 1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
11 // selection DAG.
29 // X86 Specific DAG Nodes
511 SelectionDAG &DAG) const;
551 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
557 SelectionDAG &DAG) const;
580 /// DAG node.
593 const SelectionDAG &DAG,
604 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
624 SelectionDAG &DAG) const
[all...] |
| X86SelectionDAGInfo.cpp | 30 X86SelectionDAGInfo::EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl,
57 Type *IntPtrTy = getTargetData()->getIntPtrType(*DAG.getContext());
66 TLI.LowerCallTo(Chain, Type::getVoidTy(*DAG.getContext()),
69 DAG.getExternalSymbol(bzeroEntry, IntPtr), Args,
70 DAG, dl);
110 Count = DAG.getIntPtrConstant(SizeVal);
116 Count = DAG.getIntPtrConstant(SizeVal / UBytes);
120 Chain = DAG.getCopyToReg(Chain, dl, ValReg, DAG.getConstant(Val, AVT),
125 Count = DAG.getIntPtrConstant(SizeVal)
[all...] |
| X86ISelLowering.cpp | 1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
11 // selection DAG.
61 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
67 SelectionDAG &DAG,
72 SelectionDAG &DAG,
75 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
82 SelectionDAG &DAG,
88 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
93 return DAG.getNode(ISD::UNDEF, dl, ResultVT);
107 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32)
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeDAG.cpp | 52 SelectionDAG &DAG;
78 DAG.TransferDbgValues(From, To);
82 explicit SelectionDAGLegalize(SelectionDAG &DAG);
175 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]);
189 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]);
192 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
193 : TM(dag.getTarget()), TLI(dag.getTargetLoweringInfo()),
194 DAG(dag) {
[all...] |
| LegalizeIntegerTypes.cpp | 37 DEBUG(dbgs() << "Promote integer result: "; N->dump(&DAG); dbgs() << "\n");
48 N->dump(&DAG); dbgs() << "\n";
155 return DAG.getNode(ISD::AssertSext, N->getDebugLoc(),
162 return DAG.getNode(ISD::AssertZext, N->getDebugLoc(),
167 EVT ResVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
168 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(),
181 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(),
195 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(),
208 EVT NInVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT);
210 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT)
[all...] |
| SelectionDAGBuilder.cpp | 1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
72 // Limit the width of DAG chains. This is important in general to prevent
73 // prevent DAG-based analysis from blowing up. For example, alias analysis and
76 // future analyses are likely to have the same behavior. Limiting DAG width is
88 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL,
97 static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc DL,
102 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT);
105 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
119 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
122 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2)
[all...] |
| LegalizeVectorTypes.cpp | 36 N->dump(&DAG);
44 N->dump(&DAG);
128 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
140 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
147 return DAG.getConvertRndSat(NewVT, N->getDebugLoc(),
148 Op0, DAG.getValueType(NewVT),
149 DAG.getValueType(Op0.getValueType()),
156 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(),
164 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(),
170 return DAG.getNode(ISD::FPOWI, N->getDebugLoc()
[all...] |
| LegalizeVectorOps.cpp | 36 SelectionDAG& DAG;
77 VectorLegalizer(SelectionDAG& dag) :
78 DAG(dag), TLI(dag.getTargetLoweringInfo()), Changed(false) {}
88 DAG.AssignTopologicalOrder();
89 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
90 E = prior(DAG.allnodes_end()); I != llvm::next(E); ++I)
94 SDValue OldRoot = DAG.getRoot();
96 DAG.setRoot(LegalizedNodes[OldRoot])
[all...] |
| LegalizeTypesGeneric.cpp | 42 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
57 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo);
58 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi);
64 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo);
65 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi);
71 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo);
72 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi);
77 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo);
78 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi);
83 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), InVT.getVectorElementType()
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.h | 1 //==-- MSP430ISelLowering.h - MSP430 DAG Lowering Interface ------*- C++ -*-==//
11 // selection DAG.
79 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
82 /// DAG node.
85 SDValue LowerShifts(SDValue Op, SelectionDAG &DAG) const;
86 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
87 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
88 SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
89 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
90 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const
[all...] |
| /external/llvm/lib/Target/CellSPU/ |
| SPUISelLowering.cpp | 1 //===-- SPUISelLowering.cpp - Cell SPU DAG Lowering Implementation --------===//
53 //! Expand a library call into an actual call DAG node
61 ExpandLibCall(RTLIB::Libcall LC, SDValue Op, SelectionDAG &DAG,
66 SDValue InChain = DAG.getEntryNode();
72 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
79 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
84 Op.getNode()->getValueType(0).getTypeForEVT(*DAG.getContext());
89 Callee, Args, DAG, Op.getDebugLoc());
458 // We have target-specific dag combine patterns for the following nodes:
558 LowerLOAD(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST)
[all...] |
| SPUISelLowering.h | 1 //===-- SPUISelLowering.h - Cell SPU DAG Lowering Interface -----*- C++ -*-===//
11 // a selection DAG.
64 SDValue get_vec_u18imm(SDNode *N, SelectionDAG &DAG,
66 SDValue get_vec_i16imm(SDNode *N, SelectionDAG &DAG,
68 SDValue get_vec_i10imm(SDNode *N, SelectionDAG &DAG,
70 SDValue get_vec_i8imm(SDNode *N, SelectionDAG &DAG,
72 SDValue get_ILHUvec_imm(SDNode *N, SelectionDAG &DAG,
74 SDValue get_v4i32_imm(SDNode *N, SelectionDAG &DAG);
75 SDValue get_v2i64_imm(SDNode *N, SelectionDAG &DAG);
77 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG,
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 1 //===-- SparcISelLowering.cpp - Sparc DAG Lowering Implementation ---------===//
11 // selection DAG.
85 DebugLoc dl, SelectionDAG &DAG) const {
87 MachineFunction &MF = DAG.getMachineFunction();
93 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
94 DAG.getTarget(), RVLocs, *DAG.getContext());
114 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
128 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
129 Chain = DAG.getCopyToReg(Chain, dl, SP::I0, Val, Flag)
[all...] |
| SparcISelLowering.h | 1 //===-- SparcISelLowering.h - Sparc DAG Lowering Interface ------*- C++ -*-===//
11 // selection DAG.
47 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
56 const SelectionDAG &DAG,
76 DebugLoc dl, SelectionDAG &DAG,
86 DebugLoc dl, SelectionDAG &DAG,
94 DebugLoc dl, SelectionDAG &DAG) const;
96 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
97 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
99 unsigned getSRetArgSize(SelectionDAG &DAG, SDValue Callee) const
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.h | 1 //===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
11 // selection DAG.
104 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
107 // DAG node.
124 DebugLoc dl, SelectionDAG &DAG,
128 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
129 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
130 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
131 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
132 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const
[all...] |
| /external/llvm/lib/Target/PTX/ |
| PTXSelectionDAGInfo.cpp | 29 PTXSelectionDAGInfo::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
69 Loads[i] = DAG.getLoad(VT, dl, Chain,
70 DAG.getNode(ISD::ADD, dl, PointerType, Src,
71 DAG.getConstant(SrcOff, PointerType)),
77 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
81 TFOps[i] = DAG.getStore(Chain, dl, Loads[i],
82 DAG.getNode(ISD::ADD, dl, PointerType, Dst,
83 DAG.getConstant(DstOff, PointerType)),
88 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
108 Loads[i] = DAG.getLoad(VT, dl, Chain
[all...] |
| PTXISelLowering.h | 1 //==-- PTXISelLowering.h - PTX DAG Lowering Interface ------------*- C++ -*-==//
11 // selection DAG.
44 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
46 virtual SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
54 SelectionDAG &DAG,
64 SelectionDAG &DAG) const;
73 DebugLoc dl, SelectionDAG &DAG,
81 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
|
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.h | 1 //===-- XCoreISelLowering.h - XCore DAG Lowering Interface ------*- C++ -*-===//
11 // selection DAG.
87 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
93 SelectionDAG &DAG) const;
96 // DAG node.
115 DebugLoc dl, SelectionDAG &DAG,
123 DebugLoc dl, SelectionDAG &DAG,
128 DebugLoc dl, SelectionDAG &DAG,
130 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
132 SelectionDAG &DAG) const
[all...] |
| XCoreISelLowering.cpp | 1 //===-- XCoreISelLowering.cpp - XCore DAG Lowering Implementation ------===//
158 // We have target-specific dag combine patterns for the following nodes:
166 LowerOperation(SDValue Op, SelectionDAG &DAG) const {
169 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
170 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
171 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
172 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
173 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
174 case ISD::LOAD: return LowerLOAD(Op, DAG);
175 case ISD::STORE: return LowerSTORE(Op, DAG);
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.h | 1 //===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===//
11 // selection DAG.
233 SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
243 /// DAG node.
257 SelectionDAG &DAG) const;
263 SelectionDAG &DAG) const;
269 SelectionDAG &DAG) const;
274 SelectionDAG &DAG) const;
280 SelectionDAG &DAG) const;
285 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const
[all...] |
| PPCISelLowering.cpp | 1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
385 // We have target-specific dag combine patterns for the following nodes:
667 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
710 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
713 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
717 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
720 return DAG.getTargetConstant(Val, MVT::i32);
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMSelectionDAGInfo.cpp | 29 ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
66 Loads[i] = DAG.getLoad(VT, dl, Chain,
67 DAG.getNode(ISD::ADD, dl, MVT::i32, Src,
68 DAG.getConstant(SrcOff, MVT::i32)),
74 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
78 TFOps[i] = DAG.getStore(Chain, dl, Loads[i],
79 DAG.getNode(ISD::ADD, dl, MVT::i32, Dst,
80 DAG.getConstant(DstOff, MVT::i32)),
85 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
105 Loads[i] = DAG.getLoad(VT, dl, Chain
[all...] |
| ARMISelLowering.h | 1 //===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===//
11 // selection DAG.
30 // ARM Specific DAG Nodes
242 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
248 SelectionDAG &DAG) const;
262 SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const;
295 SelectionDAG &DAG) const;
303 SelectionDAG &DAG) const;
309 const SelectionDAG &DAG,
333 SelectionDAG &DAG) const
[all...] |
| /external/llvm/lib/Target/Blackfin/ |
| BlackfinISelLowering.h | 1 //===- BlackfinISelLowering.h - Blackfin DAG Lowering Interface -*- C++ -*-===//
11 // selection DAG.
37 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
40 SelectionDAG &DAG) const;
55 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
56 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
57 SDValue LowerADDE(SDValue Op, SelectionDAG &DAG) const;
63 DebugLoc dl, SelectionDAG &DAG,
71 DebugLoc dl, SelectionDAG &DAG,
79 DebugLoc dl, SelectionDAG &DAG) const
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | 1 //===-- SystemZISelLowering.cpp - SystemZ DAG Lowering Implementation -----==//
164 SelectionDAG &DAG) const {
166 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
167 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
168 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
169 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
170 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
241 SelectionDAG &DAG,
250 return LowerCCCArguments(Chain, CallConv, isVarArg, Ins, dl, DAG, InVals);
261 DebugLoc dl, SelectionDAG &DAG,
[all...] |
