| /external/llvm/lib/Target/XCore/ |
| XCoreRegisterInfo.cpp | 147 int Opcode = isU6 ? XCore::EXTSP_u6 : XCore::EXTSP_lu6;
148 New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode))
152 int Opcode = isU6 ? XCore::LDAWSP_ru6_RRegs : XCore::LDAWSP_lru6_RRegs;
153 New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode), XCore::SP)
255 llvm_unreachable("Unexpected Opcode");
276 llvm_unreachable("Unexpected Opcode");
304 llvm_unreachable("Unexpected Opcode");
319 int Opcode = isImmU6(Value) ? XCore::LDC_ru6 : XCore::LDC_lru6;
320 BuildMI(MBB, I, dl, TII.get(Opcode), DstReg).addImm(Value);
|
| /external/llvm/lib/Target/ARM/ |
| Thumb1RegisterInfo.cpp | 371 /// convertToNonSPOpcode - Change the opcode to the non-SP version, because
373 static unsigned convertToNonSPOpcode(unsigned Opcode) {
374 switch (Opcode) {
382 return Opcode;
392 unsigned Opcode = MI.getOpcode();
396 if (Opcode == ARM::tADDrSPi) {
403 Opcode = ARM::tADDi3;
427 if (Opcode == ARM::tADDi3) {
428 MI.setDesc(TII.get(Opcode));
442 unsigned NumMIs = calcNumMI(Opcode, 0, Bytes, NumBits, Scale)
[all...] |
| Thumb2InstrInfo.cpp | 288 negativeOffsetOpcode(unsigned opcode)
290 switch (opcode) {
308 return opcode;
318 positiveOffsetOpcode(unsigned opcode)
320 switch (opcode) {
338 return opcode;
348 immediateOffsetOpcode(unsigned opcode)
350 switch (opcode) {
376 return opcode;
388 unsigned Opcode = MI.getOpcode()
[all...] |
| ARMBaseInstrInfo.h | 39 // if there is not such an opcode.
272 /// isFpMLxInstruction - Return true if the specified opcode is a fp MLA / MLS
274 bool isFpMLxInstruction(unsigned Opcode) const {
275 return MLxEntryMap.count(Opcode);
278 /// isFpMLxInstruction - This version also returns the multiply opcode and the
279 /// addition / subtraction opcode to expand to. Return true for 'HasLane' for
281 bool isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
285 /// canCauseFpMLxStall - Return true if an instruction of the specified opcode
288 bool canCauseFpMLxStall(unsigned Opcode) const {
289 return MLxHazardOpcodes.count(Opcode);
[all...] |
| /external/llvm/lib/Target/Mips/InstPrinter/ |
| MipsInstPrinter.cpp | 64 StringRef MipsInstPrinter::getOpcodeName(unsigned Opcode) const {
65 return getInstructionName(Opcode);
|
| /external/llvm/lib/Target/PTX/ |
| PTXInstrInfo.h | 115 static MachineSDNode *GetPTXMachineNode(SelectionDAG *DAG, unsigned Opcode,
119 static MachineSDNode *GetPTXMachineNode(SelectionDAG *DAG, unsigned Opcode,
|
| PTXISelLowering.h | 42 virtual const char *getTargetNodeName(unsigned Opcode) const;
|
| /external/llvm/lib/Target/X86/InstPrinter/ |
| X86ATTInstPrinter.cpp | 55 StringRef X86ATTInstPrinter::getOpcodeName(unsigned Opcode) const {
56 return getInstructionName(Opcode);
|
| X86ATTInstPrinter.h | 29 virtual StringRef getOpcodeName(unsigned Opcode) const;
38 static const char *getInstructionName(unsigned Opcode);
|
| X86IntelInstPrinter.cpp | 45 StringRef X86IntelInstPrinter::getOpcodeName(unsigned Opcode) const {
46 return getInstructionName(Opcode);
|
| X86IntelInstPrinter.h | 31 virtual StringRef getOpcodeName(unsigned Opcode) const;
36 static const char *getInstructionName(unsigned Opcode);
|
| /sdk/emulator/qtools/ |
| armdis.cpp | 6 #include "opcode.h"
45 Opcode opcode = decode(insn); local
46 switch (opcode) {
69 return disasm_alu(opcode, insn, ptr);
72 return disasm_branch(addr, opcode, insn, ptr);
90 return disasm_memblock(opcode, insn, ptr);
107 return disasm_mcr(opcode, insn, ptr);
109 return disasm_mla(opcode, insn, ptr);
115 return disasm_mul(opcode, insn, ptr)
761 uint8_t opcode = (insn >> 21) & 0x7; local
852 uint8_t opcode = (insn >> 21) & 0xf; local
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAG.cpp | 242 static int isSignedOp(ISD::CondCode Opcode) {
243 switch (Opcode) {
314 /// AddNodeIDOpcode - Add the node opcode to the NodeID data.
593 // Set the opcode to DELETED_NODE to help catch bugs when node
[all...] |
| /external/clang/lib/StaticAnalyzer/Checkers/ |
| DivZeroChecker.cpp | 34 BinaryOperator::Opcode Op = B->getOpcode();
|
| /external/clang/lib/StaticAnalyzer/Core/ |
| SimpleConstraintManager.cpp | 123 static BinaryOperator::Opcode NegateComparison(BinaryOperator::Opcode op) {
128 llvm_unreachable("Invalid opcode.");
177 BinaryOperator::Opcode op = SE->getOpcode();
207 BinaryOperator::Opcode op,
|
| SimpleSValBuilder.cpp | 34 virtual SVal evalBinOpNN(const ProgramState *state, BinaryOperator::Opcode op,
36 virtual SVal evalBinOpLL(const ProgramState *state, BinaryOperator::Opcode op,
38 virtual SVal evalBinOpLN(const ProgramState *state, BinaryOperator::Opcode op,
45 SVal MakeSymIntVal(const SymExpr *LHS, BinaryOperator::Opcode op,
171 static BinaryOperator::Opcode NegateComparison(BinaryOperator::Opcode op) {
174 llvm_unreachable("Invalid opcode.");
184 static BinaryOperator::Opcode ReverseComparison(BinaryOperator::Opcode op) {
187 llvm_unreachable("Invalid opcode.")
[all...] |
| /external/javassist/src/main/javassist/ |
| CtBehavior.java | 805 if (c == Opcode.ARETURN || c == Opcode.IRETURN
806 || c == Opcode.FRETURN || c == Opcode.LRETURN
807 || c == Opcode.DRETURN || c == Opcode.RETURN) {
831 code.addOpcode(Opcode.ACONST_NULL);
834 code.addOpcode(Opcode.RETURN);
845 code.addOpcode(Opcode.ARETURN);
857 iterator.writeByte(Opcode.NOP, pos)
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelDAGToDAG.cpp | 165 unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr;
166 return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS,
174 unsigned Opcode = N->getOpcode() == ISD::MULHU ? SP::UMULrr : SP::SMULrr;
175 SDNode *Mul = CurDAG->getMachineNode(Opcode, dl, MVT::i32, MVT::Glue,
|
| /external/llvm/lib/VMCore/ |
| ConstantFold.h | 31 unsigned opcode, ///< The opcode of the cast
46 Constant *ConstantFoldBinaryInstruction(unsigned Opcode, Constant *V1,
|
| /dalvik/vm/compiler/ |
| Loop.cpp | 89 LOGE(" opcode %d", loopAnalysis->loopBranchOpcode);
122 static Opcode negateOpcode(Opcode opcode)
124 switch (opcode) {
152 LOGE("opcode %d cannot be negated", opcode);
156 return (Opcode)-1; // unreached
207 Opcode opcode = branch->dalvikInsn.opcode local
[all...] |
| /dalvik/vm/analysis/ |
| Optimize.cpp | 41 static void rewriteInstField(Method* method, u2* insns, Opcode quickOpc,
42 Opcode volatileOpc);
44 Opcode volatileOpc);
45 static void rewriteStaticField(Method* method, u2* insns, Opcode volatileOpc);
47 Opcode volatileOpc);
48 static void rewriteVirtualInvoke(Method* method, u2* insns, Opcode newOpc);
168 Opcode opc, quickOpc, volatileOpc;
449 * Update an instruction's opcode.
451 * If "opcode" is an 8-bit op, we just replace that portion. If it's a
452 * 16-bit op, we convert the opcode from "packed" form (e.g. 0x0108) t
[all...] |
| /external/llvm/lib/Target/ARM/InstPrinter/ |
| ARMInstPrinter.cpp | 45 StringRef ARMInstPrinter::getOpcodeName(unsigned Opcode) const {
46 return getInstructionName(Opcode);
55 unsigned Opcode = MI->getOpcode();
58 if (Opcode == ARM::MOVsr) {
78 if (Opcode == ARM::MOVsi) {
103 if ((Opcode == ARM::STMDB_UPD || Opcode == ARM::t2STMDB_UPD) &&
107 if (Opcode == ARM::t2STMDB_UPD)
114 if (Opcode == ARM::STR_PRE_IMM && MI->getOperand(2).getReg() == ARM::SP &&
124 if ((Opcode == ARM::LDMIA_UPD || Opcode == ARM::t2LDMIA_UPD) &
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelDAGToDAG.cpp | 367 unsigned Opcode = Addr.getOpcode();
368 if (Opcode != ISD::Constant && Opcode != ISD::FrameIndex) {
416 unsigned Opcode = Addr.getOpcode();
417 if (Opcode != ISD::Constant && Opcode != ISD::FrameIndex) {
459 unsigned Opcode = Addr.getOpcode();
460 if (Opcode != ISD::Constant && Opcode != ISD::FrameIndex) {
508 unsigned Opcode = Addr.getOpcode()
[all...] |
| /external/llvm/utils/TableGen/ |
| X86RecognizableInstr.cpp | 75 // If rows are added to the opcode extension tables, then corresponding entries
89 // switch(Opcode) just below the case X86Local::T8: or case X86Local::TA: line
214 Opcode = byteFromRec(Rec, "Opcode");
639 // Operand 1 is added to the opcode.
648 // Operand 2 is a register operand in the Reg/Opcode field.
670 // Operand 2 is a register operand in the Reg/Opcode field.
690 // Operand 1 is a register operand in the Reg/Opcode field.
717 // Operand 1 is a register operand in the Reg/Opcode field.
828 switch (Opcode) {
[all...] |
| /external/llvm/lib/Analysis/ |
| InstructionSimplify.cpp | 92 /// it into "(A op B) op' (A op C)". Here "op" is given by Opcode and "op'" is
96 static Value *ExpandBinOp(unsigned Opcode, Value *LHS, Value *RHS,
110 if (Value *L = SimplifyBinOp(Opcode, A, C, TD, DT, MaxRecurse))
111 if (Value *R = SimplifyBinOp(Opcode, B, C, TD, DT, MaxRecurse)) {
134 if (Value *L = SimplifyBinOp(Opcode, A, B, TD, DT, MaxRecurse))
135 if (Value *R = SimplifyBinOp(Opcode, A, C, TD, DT, MaxRecurse)) {
155 /// FactorizeBinOp - Simplify "LHS Opcode RHS" by factorizing out a common term
156 /// using the operation OpCodeToExtract. For example, when Opcode is Add and
159 static Value *FactorizeBinOp(unsigned Opcode, Value *LHS, Value *RHS,
185 if (Value *V = SimplifyBinOp(Opcode, B, DD, TD, DT, MaxRecurse))
[all...] |
