| /external/llvm/lib/Target/Mips/ |
| MipsCodeEmitter.cpp | 154 if (Form == MipsII::FrmI && MI.getOpcode() == Mips::LUi)
244 switch (MI.getOpcode()) {
|
| MipsInstrInfo.cpp | 51 unsigned Opc = MI->getOpcode();
76 unsigned Opc = MI->getOpcode();
295 unsigned LastOpc = LastInst->getOpcode();
307 SecondLastOpc = GetAnalyzableBrOpc(SecondLastInst->getOpcode());
417 if (!GetAnalyzableBrOpc(I->getOpcode()))
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCHazardRecognizers.cpp | 144 GetInstrType(Node->getOpcode(), isFirst, isSingle, isCracked,
243 GetInstrType(Node->getOpcode(), isFirst, isSingle, isCracked,
|
| /external/llvm/lib/VMCore/ |
| Globals.cpp | 234 assert((CE->getOpcode() == Instruction::BitCast ||
235 CE->getOpcode() == Instruction::GetElementPtr) &&
|
| Instructions.cpp | [all...] |
| /external/clang/lib/StaticAnalyzer/Checkers/ |
| IdempotentOperationChecker.cpp | 154 BinaryOperator::Opcode Op = B->getOpcode();
385 if (B->getOpcode() == BO_Assign)
673 if (B->getOpcode() == BO_Sub || B->getOpcode() == BO_Add)
683 switch (U->getOpcode()) {
|
| /external/llvm/lib/MC/ |
| MCExpr.cpp | 72 switch (UE.getOpcode()) {
93 switch (BE.getOpcode()) {
472 switch (AUE->getOpcode()) {
511 switch (ABE->getOpcode()) {
534 switch (ABE->getOpcode()) {
|
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | [all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineVectorOps.cpp | 37 if (I->getOpcode() == Instruction::InsertElement && isConstant &&
40 if (I->getOpcode() == Instruction::Load && I->hasOneUse())
198 return BinaryOperator::Create(BO->getOpcode(), newEI0, newEI1);
237 (CI->getOpcode() != Instruction::BitCast)) {
240 return CastInst::Create(CI->getOpcode(), EE, EI.getType());
|
| InstCombineCompares.cpp | 758 bool DivIsSigned = DivI->getOpcode() == Instruction::SDiv;
[all...] |
| /external/llvm/tools/llvm-diff/ |
| DifferenceEngine.cpp | 254 if (L->getOpcode() != R->getOpcode()) {
399 if (L->getOpcode() != R->getOpcode())
402 switch (L->getOpcode()) {
|
| /external/llvm/lib/Target/X86/ |
| X86InstrInfo.cpp | [all...] |
| /external/llvm/lib/Analysis/ |
| ValueTracking.cpp | 154 switch (I->getOpcode()) {
426 if (I->getOpcode() == Instruction::Add) {
447 if (I->getOpcode() == Instruction::Add) {
601 unsigned Opcode = LU->getOpcode();
[all...] |
| /external/llvm/lib/Target/ARM/Disassembler/ |
| ARMDisassembler.cpp | 566 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
567 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
591 switch (MI.getOpcode()) {
633 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
634 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
672 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
674 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
731 if (MI.getOpcode() == ARM::t2IT && !ITBlock.empty())
739 if (MI.getOpcode() == ARM::t2IT) {
[all...] |
| /dalvik/dx/src/com/android/dx/ssa/back/ |
| FirstFitLocalCombiningAllocator.java | 222 Rop opcode = defInsn.getOpcode();
225 if (opcode != null && opcode.getOpcode() == RegOps.MOVE_PARAM) {
476 if (checkCastInsn.getOpcode().getOpcode() != RegOps.CHECK_CAST) {
668 if (insn.getOpcode().getOpcode() ==
672 insn.getOriginalRopInsn().getOpcode(),
[all...] |
| /external/llvm/lib/CodeGen/ |
| PrologEpilogInserter.cpp | 170 if (I->getOpcode() == FrameSetupOpcode ||
171 I->getOpcode() == FrameDestroyOpcode) {
739 if (I->getOpcode() == FrameSetupOpcode ||
740 I->getOpcode() == FrameDestroyOpcode) {
743 SPAdjCount += I->getOpcode() == FrameSetupOpcode ? 1 : -1;
749 if ((!StackGrowsDown && I->getOpcode() == FrameSetupOpcode) ||
750 (StackGrowsDown && I->getOpcode() == FrameDestroyOpcode))
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.cpp | 96 if (User->getOpcode() == ISD::CopyToReg &&
177 if (User->getOpcode() == ISD::CopyToReg &&
212 if (User->getOpcode() == ISD::CopyToReg &&
315 Op.getNode()->getOpcode() != ISD::CopyFromReg &&
437 if (User->getOpcode() == ISD::CopyToReg &&
710 if (F->getOpcode() == ISD::CopyFromReg)
[all...] |
| /external/llvm/lib/Target/Alpha/ |
| AlphaISelDAGToDAG.cpp | 213 switch (N->getOpcode()) {
359 if (N->getOperand(0).getOpcode() == ISD::SRL &&
400 if (Addr.getOpcode() == AlphaISD::GPRelLo) {
|
| /external/llvm/lib/Target/Blackfin/ |
| BlackfinRegisterInfo.cpp | 164 if (I->getOpcode() == BF::ADJCALLSTACKDOWN) {
167 assert(I->getOpcode() == BF::ADJCALLSTACKUP &&
217 switch (MI.getOpcode()) {
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelDAGToDAG.cpp | 187 switch (N.getOpcode()) {
356 if (N1.getOpcode() == ISD::LOAD &&
401 switch (Node->getOpcode()) {
|
| /external/llvm/lib/Target/PTX/ |
| PTXInstrInfo.cpp | 92 switch (MI.getOpcode()) {
119 return !isPredicated(MI) && get(MI->getOpcode()).isTerminator();
198 DEBUG(dbgs() << "AnalyzeBranch: opcode: " << instLast1.getOpcode() << "\n");
|
| /external/llvm/lib/Transforms/Utils/ |
| AddrModeMatcher.cpp | 124 switch (I->getOpcode()) {
330 if (MatchOperationAddr(I, I->getOpcode(), Depth)) {
346 if (MatchOperationAddr(CE, CE->getOpcode(), Depth))
|
| /dalvik/dexgen/src/com/android/dexgen/dex/code/ |
| DalvInsnList.java | 204 (insn.getOpcode().getFamily() == DalvOps.INVOKE_STATIC);
|
| /dalvik/dx/src/com/android/dx/dex/code/ |
| DalvInsnList.java | 205 (insn.getOpcode().getFamily() == Opcodes.INVOKE_STATIC);
|
| /external/clang/lib/ARCMigrate/ |
| TransRetainReleaseDealloc.cpp | 200 if (bopE->getOpcode() == BO_Comma && bopE->getLHS() == E &&
|
