1 //===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the pass that transforms the ARM machine instructions into 11 // relocatable machine code. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #define DEBUG_TYPE "jit" 16 #include "ARM.h" 17 #include "ARMConstantPoolValue.h" 18 #include "ARMInstrInfo.h" 19 #include "ARMRelocations.h" 20 #include "ARMSubtarget.h" 21 #include "ARMTargetMachine.h" 22 #include "MCTargetDesc/ARMAddressingModes.h" 23 #include "llvm/Constants.h" 24 #include "llvm/DerivedTypes.h" 25 #include "llvm/Function.h" 26 #include "llvm/PassManager.h" 27 #include "llvm/CodeGen/JITCodeEmitter.h" 28 #include "llvm/CodeGen/MachineConstantPool.h" 29 #include "llvm/CodeGen/MachineFunctionPass.h" 30 #include "llvm/CodeGen/MachineInstr.h" 31 #include "llvm/CodeGen/MachineJumpTableInfo.h" 32 #include "llvm/CodeGen/MachineModuleInfo.h" 33 #include "llvm/CodeGen/Passes.h" 34 #include "llvm/ADT/Statistic.h" 35 #include "llvm/Support/Debug.h" 36 #include "llvm/Support/ErrorHandling.h" 37 #include "llvm/Support/raw_ostream.h" 38 #ifndef NDEBUG 39 #include <iomanip> 40 #endif 41 using namespace llvm; 42 43 STATISTIC(NumEmitted, "Number of machine instructions emitted"); 44 45 namespace { 46 47 class ARMCodeEmitter : public MachineFunctionPass { 48 ARMJITInfo *JTI; 49 const ARMInstrInfo *II; 50 const TargetData *TD; 51 const ARMSubtarget *Subtarget; 52 TargetMachine &TM; 53 JITCodeEmitter &MCE; 54 MachineModuleInfo *MMI; 55 const std::vector<MachineConstantPoolEntry> *MCPEs; 56 const std::vector<MachineJumpTableEntry> *MJTEs; 57 bool IsPIC; 58 bool IsThumb; 59 60 void getAnalysisUsage(AnalysisUsage &AU) const { 61 AU.addRequired<MachineModuleInfo>(); 62 MachineFunctionPass::getAnalysisUsage(AU); 63 } 64 65 static char ID; 66 public: 67 ARMCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce) 68 : MachineFunctionPass(ID), JTI(0), 69 II((const ARMInstrInfo *)tm.getInstrInfo()), 70 TD(tm.getTargetData()), TM(tm), 71 MCE(mce), MCPEs(0), MJTEs(0), 72 IsPIC(TM.getRelocationModel() == Reloc::PIC_), IsThumb(false) {} 73 74 /// getBinaryCodeForInstr - This function, generated by the 75 /// CodeEmitterGenerator using TableGen, produces the binary encoding for 76 /// machine instructions. 77 unsigned getBinaryCodeForInstr(const MachineInstr &MI) const; 78 79 bool runOnMachineFunction(MachineFunction &MF); 80 81 virtual const char *getPassName() const { 82 return "ARM Machine Code Emitter"; 83 } 84 85 void emitInstruction(const MachineInstr &MI); 86 87 private: 88 89 void emitWordLE(unsigned Binary); 90 void emitDWordLE(uint64_t Binary); 91 void emitConstantToMemory(unsigned CPI, const Constant *CV); 92 void emitConstPoolInstruction(const MachineInstr &MI); 93 void emitMOVi32immInstruction(const MachineInstr &MI); 94 void emitMOVi2piecesInstruction(const MachineInstr &MI); 95 void emitLEApcrelInstruction(const MachineInstr &MI); 96 void emitLEApcrelJTInstruction(const MachineInstr &MI); 97 void emitPseudoMoveInstruction(const MachineInstr &MI); 98 void addPCLabel(unsigned LabelID); 99 void emitPseudoInstruction(const MachineInstr &MI); 100 unsigned getMachineSoRegOpValue(const MachineInstr &MI, 101 const MCInstrDesc &MCID, 102 const MachineOperand &MO, 103 unsigned OpIdx); 104 105 unsigned getMachineSoImmOpValue(unsigned SoImm); 106 unsigned getAddrModeSBit(const MachineInstr &MI, 107 const MCInstrDesc &MCID) const; 108 109 void emitDataProcessingInstruction(const MachineInstr &MI, 110 unsigned ImplicitRd = 0, 111 unsigned ImplicitRn = 0); 112 113 void emitLoadStoreInstruction(const MachineInstr &MI, 114 unsigned ImplicitRd = 0, 115 unsigned ImplicitRn = 0); 116 117 void emitMiscLoadStoreInstruction(const MachineInstr &MI, 118 unsigned ImplicitRn = 0); 119 120 void emitLoadStoreMultipleInstruction(const MachineInstr &MI); 121 122 void emitMulFrmInstruction(const MachineInstr &MI); 123 124 void emitExtendInstruction(const MachineInstr &MI); 125 126 void emitMiscArithInstruction(const MachineInstr &MI); 127 128 void emitSaturateInstruction(const MachineInstr &MI); 129 130 void emitBranchInstruction(const MachineInstr &MI); 131 132 void emitInlineJumpTable(unsigned JTIndex); 133 134 void emitMiscBranchInstruction(const MachineInstr &MI); 135 136 void emitVFPArithInstruction(const MachineInstr &MI); 137 138 void emitVFPConversionInstruction(const MachineInstr &MI); 139 140 void emitVFPLoadStoreInstruction(const MachineInstr &MI); 141 142 void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI); 143 144 void emitMiscInstruction(const MachineInstr &MI); 145 146 void emitNEONLaneInstruction(const MachineInstr &MI); 147 void emitNEONDupInstruction(const MachineInstr &MI); 148 void emitNEON1RegModImmInstruction(const MachineInstr &MI); 149 void emitNEON2RegInstruction(const MachineInstr &MI); 150 void emitNEON3RegInstruction(const MachineInstr &MI); 151 152 /// getMachineOpValue - Return binary encoding of operand. If the machine 153 /// operand requires relocation, record the relocation and return zero. 154 unsigned getMachineOpValue(const MachineInstr &MI, 155 const MachineOperand &MO) const; 156 unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) const { 157 return getMachineOpValue(MI, MI.getOperand(OpIdx)); 158 } 159 160 // FIXME: The legacy JIT ARMCodeEmitter doesn't rely on the the 161 // TableGen'erated getBinaryCodeForInstr() function to encode any 162 // operand values, instead querying getMachineOpValue() directly for 163 // each operand it needs to encode. Thus, any of the new encoder 164 // helper functions can simply return 0 as the values the return 165 // are already handled elsewhere. They are placeholders to allow this 166 // encoder to continue to function until the MC encoder is sufficiently 167 // far along that this one can be eliminated entirely. 168 unsigned NEONThumb2DataIPostEncoder(const MachineInstr &MI, unsigned Val) 169 const { return 0; } 170 unsigned NEONThumb2LoadStorePostEncoder(const MachineInstr &MI,unsigned Val) 171 const { return 0; } 172 unsigned NEONThumb2DupPostEncoder(const MachineInstr &MI,unsigned Val) 173 const { return 0; } 174 unsigned VFPThumb2PostEncoder(const MachineInstr&MI, unsigned Val) 175 const { 176 if (IsThumb) { 177 Val &= 0x0FFFFFFF; 178 Val |= 0xE0000000; 179 } 180 return Val; 181 } 182 unsigned getAdrLabelOpValue(const MachineInstr &MI, unsigned Op) 183 const { return 0; } 184 unsigned getThumbAdrLabelOpValue(const MachineInstr &MI, unsigned Op) 185 const { return 0; } 186 unsigned getThumbBLTargetOpValue(const MachineInstr &MI, unsigned Op) 187 const { return 0; } 188 unsigned getThumbBLXTargetOpValue(const MachineInstr &MI, unsigned Op) 189 const { return 0; } 190 unsigned getThumbBRTargetOpValue(const MachineInstr &MI, unsigned Op) 191 const { return 0; } 192 unsigned getThumbBCCTargetOpValue(const MachineInstr &MI, unsigned Op) 193 const { return 0; } 194 unsigned getThumbCBTargetOpValue(const MachineInstr &MI, unsigned Op) 195 const { return 0; } 196 unsigned getBranchTargetOpValue(const MachineInstr &MI, unsigned Op) 197 const { return 0; } 198 unsigned getUnconditionalBranchTargetOpValue(const MachineInstr &MI, 199 unsigned Op) const { return 0; } 200 unsigned getARMBranchTargetOpValue(const MachineInstr &MI, unsigned Op) 201 const { return 0; } 202 unsigned getARMBLXTargetOpValue(const MachineInstr &MI, unsigned Op) 203 const { return 0; } 204 unsigned getCCOutOpValue(const MachineInstr &MI, unsigned Op) 205 const { return 0; } 206 unsigned getSOImmOpValue(const MachineInstr &MI, unsigned Op) 207 const { return 0; } 208 unsigned getT2SOImmOpValue(const MachineInstr &MI, unsigned Op) 209 const { return 0; } 210 unsigned getSORegRegOpValue(const MachineInstr &MI, unsigned Op) 211 const { return 0; } 212 unsigned getSORegImmOpValue(const MachineInstr &MI, unsigned Op) 213 const { return 0; } 214 unsigned getThumbAddrModeRegRegOpValue(const MachineInstr &MI, unsigned Op) 215 const { return 0; } 216 unsigned getT2AddrModeImm12OpValue(const MachineInstr &MI, unsigned Op) 217 const { return 0; } 218 unsigned getT2AddrModeImm8OpValue(const MachineInstr &MI, unsigned Op) 219 const { return 0; } 220 unsigned getT2Imm8s4OpValue(const MachineInstr &MI, unsigned Op) 221 const { return 0; } 222 unsigned getT2AddrModeImm8s4OpValue(const MachineInstr &MI, unsigned Op) 223 const { return 0; } 224 unsigned getT2AddrModeImm0_1020s4OpValue(const MachineInstr &MI,unsigned Op) 225 const { return 0; } 226 unsigned getT2AddrModeImm8OffsetOpValue(const MachineInstr &MI, unsigned Op) 227 const { return 0; } 228 unsigned getT2AddrModeImm12OffsetOpValue(const MachineInstr &MI,unsigned Op) 229 const { return 0; } 230 unsigned getT2AddrModeSORegOpValue(const MachineInstr &MI, unsigned Op) 231 const { return 0; } 232 unsigned getT2SORegOpValue(const MachineInstr &MI, unsigned Op) 233 const { return 0; } 234 unsigned getT2AdrLabelOpValue(const MachineInstr &MI, unsigned Op) 235 const { return 0; } 236 unsigned getAddrMode6AddressOpValue(const MachineInstr &MI, unsigned Op) 237 const { return 0; } 238 unsigned getAddrMode6OneLane32AddressOpValue(const MachineInstr &MI, 239 unsigned Op) 240 const { return 0; } 241 unsigned getAddrMode6DupAddressOpValue(const MachineInstr &MI, unsigned Op) 242 const { return 0; } 243 unsigned getAddrMode6OffsetOpValue(const MachineInstr &MI, unsigned Op) 244 const { return 0; } 245 unsigned getBitfieldInvertedMaskOpValue(const MachineInstr &MI, 246 unsigned Op) const { return 0; } 247 unsigned getSsatBitPosValue(const MachineInstr &MI, 248 unsigned Op) const { return 0; } 249 uint32_t getLdStmModeOpValue(const MachineInstr &MI, unsigned OpIdx) 250 const {return 0; } 251 uint32_t getLdStSORegOpValue(const MachineInstr &MI, unsigned OpIdx) 252 const { return 0; } 253 254 unsigned getAddrModeImm12OpValue(const MachineInstr &MI, unsigned Op) 255 const { 256 // {17-13} = reg 257 // {12} = (U)nsigned (add == '1', sub == '0') 258 // {11-0} = imm12 259 const MachineOperand &MO = MI.getOperand(Op); 260 const MachineOperand &MO1 = MI.getOperand(Op + 1); 261 if (!MO.isReg()) { 262 emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry); 263 return 0; 264 } 265 unsigned Reg = getARMRegisterNumbering(MO.getReg()); 266 int32_t Imm12 = MO1.getImm(); 267 uint32_t Binary; 268 Binary = Imm12 & 0xfff; 269 if (Imm12 >= 0) 270 Binary |= (1 << 12); 271 Binary |= (Reg << 13); 272 return Binary; 273 } 274 275 unsigned getHiLo16ImmOpValue(const MachineInstr &MI, unsigned Op) 276 const { 277 const MCInstrDesc &MCID = MI.getDesc(); 278 const MachineOperand &MO = MI.getOperand(Op); 279 280 unsigned Reloc = (MCID.Opcode == ARM::MOVi16 ? 281 ARM::reloc_arm_movw : ARM::reloc_arm_movt); 282 283 if (!MO.isImm()) { 284 emitGlobalAddress(MO.getGlobal(), Reloc, true, false); 285 return 0; 286 } 287 unsigned Imm16 = static_cast<unsigned>(MO.getImm()); 288 return Imm16; 289 } 290 291 uint32_t getAddrMode2OpValue(const MachineInstr &MI, unsigned OpIdx) 292 const { return 0;} 293 uint32_t getAddrMode2OffsetOpValue(const MachineInstr &MI, unsigned OpIdx) 294 const { return 0;} 295 uint32_t getPostIdxRegOpValue(const MachineInstr &MI, unsigned OpIdx) 296 const { return 0;} 297 uint32_t getAddrMode3OffsetOpValue(const MachineInstr &MI, unsigned OpIdx) 298 const { return 0;} 299 uint32_t getAddrMode3OpValue(const MachineInstr &MI, unsigned Op) 300 const { return 0; } 301 uint32_t getAddrModeThumbSPOpValue(const MachineInstr &MI, unsigned Op) 302 const { return 0; } 303 uint32_t getAddrModeSOpValue(const MachineInstr &MI, unsigned Op) 304 const { return 0; } 305 uint32_t getAddrModeISOpValue(const MachineInstr &MI, unsigned Op) 306 const { return 0; } 307 uint32_t getAddrModePCOpValue(const MachineInstr &MI, unsigned Op) 308 const { return 0; } 309 uint32_t getAddrMode5OpValue(const MachineInstr &MI, unsigned Op) const { 310 // {12-9} = reg 311 // {8} = (U)nsigned (add == '1', sub == '0') 312 // {7-0} = imm8 313 uint32_t Binary = 0; 314 const MachineOperand &MO = MI.getOperand(Op); 315 uint32_t Reg = getMachineOpValue(MI, MO); 316 Binary |= (Reg << 9); 317 318 // If there is a non-zero immediate offset, encode it. 319 if (MO.isReg()) { 320 const MachineOperand &MO1 = MI.getOperand(Op + 1); 321 if (uint32_t ImmOffs = ARM_AM::getAM5Offset(MO1.getImm())) { 322 if (ARM_AM::getAM5Op(MO1.getImm()) == ARM_AM::add) 323 Binary |= 1 << 8; 324 Binary |= ImmOffs & 0xff; 325 return Binary; 326 } 327 } 328 329 // If immediate offset is omitted, default to +0. 330 Binary |= 1 << 8; 331 return Binary; 332 } 333 unsigned getNEONVcvtImm32OpValue(const MachineInstr &MI, unsigned Op) 334 const { return 0; } 335 336 unsigned getRegisterListOpValue(const MachineInstr &MI, unsigned Op) 337 const { return 0; } 338 339 unsigned getShiftRight8Imm(const MachineInstr &MI, unsigned Op) 340 const { return 0; } 341 unsigned getShiftRight16Imm(const MachineInstr &MI, unsigned Op) 342 const { return 0; } 343 unsigned getShiftRight32Imm(const MachineInstr &MI, unsigned Op) 344 const { return 0; } 345 unsigned getShiftRight64Imm(const MachineInstr &MI, unsigned Op) 346 const { return 0; } 347 348 /// getMovi32Value - Return binary encoding of operand for movw/movt. If the 349 /// machine operand requires relocation, record the relocation and return 350 /// zero. 351 unsigned getMovi32Value(const MachineInstr &MI,const MachineOperand &MO, 352 unsigned Reloc); 353 354 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value. 355 /// 356 unsigned getShiftOp(unsigned Imm) const ; 357 358 /// Routines that handle operands which add machine relocations which are 359 /// fixed up by the relocation stage. 360 void emitGlobalAddress(const GlobalValue *GV, unsigned Reloc, 361 bool MayNeedFarStub, bool Indirect, 362 intptr_t ACPV = 0) const; 363 void emitExternalSymbolAddress(const char *ES, unsigned Reloc) const; 364 void emitConstPoolAddress(unsigned CPI, unsigned Reloc) const; 365 void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const; 366 void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc, 367 intptr_t JTBase = 0) const; 368 }; 369 } 370 371 char ARMCodeEmitter::ID = 0; 372 373 /// createARMJITCodeEmitterPass - Return a pass that emits the collected ARM 374 /// code to the specified MCE object. 375 FunctionPass *llvm::createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM, 376 JITCodeEmitter &JCE) { 377 return new ARMCodeEmitter(TM, JCE); 378 } 379 380 bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) { 381 assert((MF.getTarget().getRelocationModel() != Reloc::Default || 382 MF.getTarget().getRelocationModel() != Reloc::Static) && 383 "JIT relocation model must be set to static or default!"); 384 JTI = ((ARMTargetMachine &)MF.getTarget()).getJITInfo(); 385 II = ((const ARMTargetMachine &)MF.getTarget()).getInstrInfo(); 386 TD = ((const ARMTargetMachine &)MF.getTarget()).getTargetData(); 387 Subtarget = &TM.getSubtarget<ARMSubtarget>(); 388 MCPEs = &MF.getConstantPool()->getConstants(); 389 MJTEs = 0; 390 if (MF.getJumpTableInfo()) MJTEs = &MF.getJumpTableInfo()->getJumpTables(); 391 IsPIC = TM.getRelocationModel() == Reloc::PIC_; 392 IsThumb = MF.getInfo<ARMFunctionInfo>()->isThumbFunction(); 393 JTI->Initialize(MF, IsPIC); 394 MMI = &getAnalysis<MachineModuleInfo>(); 395 MCE.setModuleInfo(MMI); 396 397 do { 398 DEBUG(errs() << "JITTing function '" 399 << MF.getFunction()->getName() << "'\n"); 400 MCE.startFunction(MF); 401 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end(); 402 MBB != E; ++MBB) { 403 MCE.StartMachineBasicBlock(MBB); 404 for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end(); 405 I != E; ++I) 406 emitInstruction(*I); 407 } 408 } while (MCE.finishFunction(MF)); 409 410 return false; 411 } 412 413 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value. 414 /// 415 unsigned ARMCodeEmitter::getShiftOp(unsigned Imm) const { 416 switch (ARM_AM::getAM2ShiftOpc(Imm)) { 417 default: llvm_unreachable("Unknown shift opc!"); 418 case ARM_AM::asr: return 2; 419 case ARM_AM::lsl: return 0; 420 case ARM_AM::lsr: return 1; 421 case ARM_AM::ror: 422 case ARM_AM::rrx: return 3; 423 } 424 return 0; 425 } 426 427 /// getMovi32Value - Return binary encoding of operand for movw/movt. If the 428 /// machine operand requires relocation, record the relocation and return zero. 429 unsigned ARMCodeEmitter::getMovi32Value(const MachineInstr &MI, 430 const MachineOperand &MO, 431 unsigned Reloc) { 432 assert(((Reloc == ARM::reloc_arm_movt) || (Reloc == ARM::reloc_arm_movw)) 433 && "Relocation to this function should be for movt or movw"); 434 435 if (MO.isImm()) 436 return static_cast<unsigned>(MO.getImm()); 437 else if (MO.isGlobal()) 438 emitGlobalAddress(MO.getGlobal(), Reloc, true, false); 439 else if (MO.isSymbol()) 440 emitExternalSymbolAddress(MO.getSymbolName(), Reloc); 441 else if (MO.isMBB()) 442 emitMachineBasicBlock(MO.getMBB(), Reloc); 443 else { 444 #ifndef NDEBUG 445 errs() << MO; 446 #endif 447 llvm_unreachable("Unsupported operand type for movw/movt"); 448 } 449 return 0; 450 } 451 452 /// getMachineOpValue - Return binary encoding of operand. If the machine 453 /// operand requires relocation, record the relocation and return zero. 454 unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI, 455 const MachineOperand &MO) const { 456 if (MO.isReg()) 457 return getARMRegisterNumbering(MO.getReg()); 458 else if (MO.isImm()) 459 return static_cast<unsigned>(MO.getImm()); 460 else if (MO.isFPImm()) 461 return static_cast<unsigned>(MO.getFPImm()->getValueAPF() 462 .bitcastToAPInt().getHiBits(32).getLimitedValue()); 463 else if (MO.isGlobal()) 464 emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true, false); 465 else if (MO.isSymbol()) 466 emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch); 467 else if (MO.isCPI()) { 468 const MCInstrDesc &MCID = MI.getDesc(); 469 // For VFP load, the immediate offset is multiplied by 4. 470 unsigned Reloc = ((MCID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm) 471 ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry; 472 emitConstPoolAddress(MO.getIndex(), Reloc); 473 } else if (MO.isJTI()) 474 emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative); 475 else if (MO.isMBB()) 476 emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch); 477 else 478 llvm_unreachable("Unable to encode MachineOperand!"); 479 return 0; 480 } 481 482 /// emitGlobalAddress - Emit the specified address to the code stream. 483 /// 484 void ARMCodeEmitter::emitGlobalAddress(const GlobalValue *GV, unsigned Reloc, 485 bool MayNeedFarStub, bool Indirect, 486 intptr_t ACPV) const { 487 MachineRelocation MR = Indirect 488 ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc, 489 const_cast<GlobalValue *>(GV), 490 ACPV, MayNeedFarStub) 491 : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc, 492 const_cast<GlobalValue *>(GV), ACPV, 493 MayNeedFarStub); 494 MCE.addRelocation(MR); 495 } 496 497 /// emitExternalSymbolAddress - Arrange for the address of an external symbol to 498 /// be emitted to the current location in the function, and allow it to be PC 499 /// relative. 500 void ARMCodeEmitter:: 501 emitExternalSymbolAddress(const char *ES, unsigned Reloc) const { 502 MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(), 503 Reloc, ES)); 504 } 505 506 /// emitConstPoolAddress - Arrange for the address of an constant pool 507 /// to be emitted to the current location in the function, and allow it to be PC 508 /// relative. 509 void ARMCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc) const { 510 // Tell JIT emitter we'll resolve the address. 511 MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(), 512 Reloc, CPI, 0, true)); 513 } 514 515 /// emitJumpTableAddress - Arrange for the address of a jump table to 516 /// be emitted to the current location in the function, and allow it to be PC 517 /// relative. 518 void ARMCodeEmitter:: 519 emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const { 520 MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(), 521 Reloc, JTIndex, 0, true)); 522 } 523 524 /// emitMachineBasicBlock - Emit the specified address basic block. 525 void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB, 526 unsigned Reloc, 527 intptr_t JTBase) const { 528 MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(), 529 Reloc, BB, JTBase)); 530 } 531 532 void ARMCodeEmitter::emitWordLE(unsigned Binary) { 533 DEBUG(errs() << " 0x"; 534 errs().write_hex(Binary) << "\n"); 535 MCE.emitWordLE(Binary); 536 } 537 538 void ARMCodeEmitter::emitDWordLE(uint64_t Binary) { 539 DEBUG(errs() << " 0x"; 540 errs().write_hex(Binary) << "\n"); 541 MCE.emitDWordLE(Binary); 542 } 543 544 void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) { 545 DEBUG(errs() << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI); 546 547 MCE.processDebugLoc(MI.getDebugLoc(), true); 548 549 ++NumEmitted; // Keep track of the # of mi's emitted 550 switch (MI.getDesc().TSFlags & ARMII::FormMask) { 551 default: { 552 llvm_unreachable("Unhandled instruction encoding format!"); 553 break; 554 } 555 case ARMII::MiscFrm: 556 if (MI.getOpcode() == ARM::LEApcrelJT) { 557 // Materialize jumptable address. 558 emitLEApcrelJTInstruction(MI); 559 break; 560 } 561 llvm_unreachable("Unhandled instruction encoding!"); 562 break; 563 case ARMII::Pseudo: 564 emitPseudoInstruction(MI); 565 break; 566 case ARMII::DPFrm: 567 case ARMII::DPSoRegFrm: 568 emitDataProcessingInstruction(MI); 569 break; 570 case ARMII::LdFrm: 571 case ARMII::StFrm: 572 emitLoadStoreInstruction(MI); 573 break; 574 case ARMII::LdMiscFrm: 575 case ARMII::StMiscFrm: 576 emitMiscLoadStoreInstruction(MI); 577 break; 578 case ARMII::LdStMulFrm: 579 emitLoadStoreMultipleInstruction(MI); 580 break; 581 case ARMII::MulFrm: 582 emitMulFrmInstruction(MI); 583 break; 584 case ARMII::ExtFrm: 585 emitExtendInstruction(MI); 586 break; 587 case ARMII::ArithMiscFrm: 588 emitMiscArithInstruction(MI); 589 break; 590 case ARMII::SatFrm: 591 emitSaturateInstruction(MI); 592 break; 593 case ARMII::BrFrm: 594 emitBranchInstruction(MI); 595 break; 596 case ARMII::BrMiscFrm: 597 emitMiscBranchInstruction(MI); 598 break; 599 // VFP instructions. 600 case ARMII::VFPUnaryFrm: 601 case ARMII::VFPBinaryFrm: 602 emitVFPArithInstruction(MI); 603 break; 604 case ARMII::VFPConv1Frm: 605 case ARMII::VFPConv2Frm: 606 case ARMII::VFPConv3Frm: 607 case ARMII::VFPConv4Frm: 608 case ARMII::VFPConv5Frm: 609 emitVFPConversionInstruction(MI); 610 break; 611 case ARMII::VFPLdStFrm: 612 emitVFPLoadStoreInstruction(MI); 613 break; 614 case ARMII::VFPLdStMulFrm: 615 emitVFPLoadStoreMultipleInstruction(MI); 616 break; 617 case ARMII::VFPMiscFrm: 618 emitMiscInstruction(MI); 619 break; 620 // NEON instructions. 621 case ARMII::NGetLnFrm: 622 case ARMII::NSetLnFrm: 623 emitNEONLaneInstruction(MI); 624 break; 625 case ARMII::NDupFrm: 626 emitNEONDupInstruction(MI); 627 break; 628 case ARMII::N1RegModImmFrm: 629 emitNEON1RegModImmInstruction(MI); 630 break; 631 case ARMII::N2RegFrm: 632 emitNEON2RegInstruction(MI); 633 break; 634 case ARMII::N3RegFrm: 635 emitNEON3RegInstruction(MI); 636 break; 637 } 638 MCE.processDebugLoc(MI.getDebugLoc(), false); 639 } 640 641 void ARMCodeEmitter::emitConstantToMemory(unsigned CPI, const Constant *C) { 642 DEBUG({ 643 errs() << " ** Constant pool #" << CPI << " @ " 644 << (void*)MCE.getCurrentPCValue() << " "; 645 if (const Function *F = dyn_cast<Function>(C)) 646 errs() << F->getName(); 647 else 648 errs() << *C; 649 errs() << '\n'; 650 }); 651 652 switch (C->getValueID()) { 653 default: { 654 llvm_unreachable("Unable to handle this constantpool entry!"); 655 break; 656 } 657 case Value::GlobalVariableVal: { 658 emitGlobalAddress(static_cast<const GlobalValue*>(C), 659 ARM::reloc_arm_absolute, isa<Function>(C), false); 660 emitWordLE(0); 661 break; 662 } 663 case Value::ConstantIntVal: { 664 const ConstantInt *CI = static_cast<const ConstantInt*>(C); 665 uint32_t Val = *(uint32_t*)CI->getValue().getRawData(); 666 emitWordLE(Val); 667 break; 668 } 669 case Value::ConstantFPVal: { 670 const ConstantFP *CFP = static_cast<const ConstantFP*>(C); 671 if (CFP->getType()->isFloatTy()) 672 emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue()); 673 else if (CFP->getType()->isDoubleTy()) 674 emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue()); 675 else { 676 llvm_unreachable("Unable to handle this constantpool entry!"); 677 } 678 break; 679 } 680 case Value::ConstantArrayVal: { 681 const ConstantArray *CA = static_cast<const ConstantArray*>(C); 682 for (unsigned i = 0, e = CA->getNumOperands(); i != e; ++i) 683 emitConstantToMemory(CPI, CA->getOperand(i)); 684 break; 685 } 686 case Value::ConstantVectorVal:{ 687 //FIXME:emit vector 688 const ConstantVector *CV = static_cast<const ConstantVector*>(C); 689 break; 690 } 691 } 692 693 return; 694 } 695 696 void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) { 697 unsigned CPI = MI.getOperand(0).getImm(); // CP instruction index. 698 unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index. 699 const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex]; 700 701 // Remember the CONSTPOOL_ENTRY address for later relocation. 702 JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue()); 703 704 // Emit constpool island entry. In most cases, the actual values will be 705 // resolved and relocated after code emission. 706 if (MCPE.isMachineConstantPoolEntry()) { 707 ARMConstantPoolValue *ACPV = 708 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal); 709 710 DEBUG(errs() << " ** ARM constant pool #" << CPI << " @ " 711 << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n'); 712 713 assert(ACPV->isGlobalValue() && "unsupported constant pool value"); 714 const GlobalValue *GV = cast<ARMConstantPoolConstant>(ACPV)->getGV(); 715 if (GV) { 716 Reloc::Model RelocM = TM.getRelocationModel(); 717 emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry, 718 isa<Function>(GV), 719 Subtarget->GVIsIndirectSymbol(GV, RelocM), 720 (intptr_t)ACPV); 721 } else { 722 const char *Sym = cast<ARMConstantPoolSymbol>(ACPV)->getSymbol(); 723 emitExternalSymbolAddress(Sym, ARM::reloc_arm_absolute); 724 } 725 emitWordLE(0); 726 } else { 727 emitConstantToMemory(CPI, MCPE.Val.ConstVal); 728 } 729 } 730 731 void ARMCodeEmitter::emitMOVi32immInstruction(const MachineInstr &MI) { 732 const MachineOperand &MO0 = MI.getOperand(0); 733 const MachineOperand &MO1 = MI.getOperand(1); 734 735 // Emit the 'movw' instruction. 736 unsigned Binary = 0x30 << 20; // mov: Insts{27-20} = 0b00110000 737 738 unsigned Lo16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movw) & 0xFFFF; 739 740 // Set the conditional execution predicate. 741 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 742 743 // Encode Rd. 744 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift; 745 746 // Encode imm16 as imm4:imm12 747 Binary |= Lo16 & 0xFFF; // Insts{11-0} = imm12 748 Binary |= ((Lo16 >> 12) & 0xF) << 16; // Insts{19-16} = imm4 749 emitWordLE(Binary); 750 751 unsigned Hi16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movt) >> 16; 752 // Emit the 'movt' instruction. 753 Binary = 0x34 << 20; // movt: Insts{27-20} = 0b00110100 754 755 // Set the conditional execution predicate. 756 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 757 758 // Encode Rd. 759 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift; 760 761 // Encode imm16 as imm4:imm1, same as movw above. 762 Binary |= Hi16 & 0xFFF; 763 Binary |= ((Hi16 >> 12) & 0xF) << 16; 764 emitWordLE(Binary); 765 } 766 767 void ARMCodeEmitter::emitMOVi2piecesInstruction(const MachineInstr &MI) { 768 const MachineOperand &MO0 = MI.getOperand(0); 769 const MachineOperand &MO1 = MI.getOperand(1); 770 assert(MO1.isImm() && ARM_AM::isSOImmTwoPartVal(MO1.getImm()) && 771 "Not a valid so_imm value!"); 772 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm()); 773 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm()); 774 775 // Emit the 'mov' instruction. 776 unsigned Binary = 0xd << 21; // mov: Insts{24-21} = 0b1101 777 778 // Set the conditional execution predicate. 779 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 780 781 // Encode Rd. 782 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift; 783 784 // Encode so_imm. 785 // Set bit I(25) to identify this is the immediate form of <shifter_op> 786 Binary |= 1 << ARMII::I_BitShift; 787 Binary |= getMachineSoImmOpValue(V1); 788 emitWordLE(Binary); 789 790 // Now the 'orr' instruction. 791 Binary = 0xc << 21; // orr: Insts{24-21} = 0b1100 792 793 // Set the conditional execution predicate. 794 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 795 796 // Encode Rd. 797 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift; 798 799 // Encode Rn. 800 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift; 801 802 // Encode so_imm. 803 // Set bit I(25) to identify this is the immediate form of <shifter_op> 804 Binary |= 1 << ARMII::I_BitShift; 805 Binary |= getMachineSoImmOpValue(V2); 806 emitWordLE(Binary); 807 } 808 809 void ARMCodeEmitter::emitLEApcrelInstruction(const MachineInstr &MI) { 810 // It's basically add r, pc, (LCPI - $+8) 811 const MCInstrDesc &MCID = MI.getDesc(); 812 813 unsigned Binary = 0; 814 815 // Set the conditional execution predicate 816 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 817 818 // Encode S bit if MI modifies CPSR. 819 Binary |= getAddrModeSBit(MI, MCID); 820 821 // Encode Rd. 822 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift; 823 824 // Encode Rn which is PC. 825 Binary |= getARMRegisterNumbering(ARM::PC) << ARMII::RegRnShift; 826 827 // Encode the displacement which is a so_imm. 828 // Set bit I(25) to identify this is the immediate form of <shifter_op> 829 Binary |= 1 << ARMII::I_BitShift; 830 emitConstPoolAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_so_imm_cp_entry); 831 832 emitWordLE(Binary); 833 } 834 835 void ARMCodeEmitter::emitLEApcrelJTInstruction(const MachineInstr &MI) { 836 // It's basically add r, pc, (LJTI - $+8) 837 838 const MCInstrDesc &MCID = MI.getDesc(); 839 840 // Emit the 'add' instruction. 841 unsigned Binary = 0x4 << 21; // add: Insts{24-21} = 0b0100 842 843 // Set the conditional execution predicate 844 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 845 846 // Encode S bit if MI modifies CPSR. 847 Binary |= getAddrModeSBit(MI, MCID); 848 849 // Encode Rd. 850 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift; 851 852 // Encode Rn which is PC. 853 Binary |= getARMRegisterNumbering(ARM::PC) << ARMII::RegRnShift; 854 855 // Encode the displacement. 856 Binary |= 1 << ARMII::I_BitShift; 857 emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base); 858 859 emitWordLE(Binary); 860 } 861 862 void ARMCodeEmitter::emitPseudoMoveInstruction(const MachineInstr &MI) { 863 unsigned Opcode = MI.getDesc().Opcode; 864 865 // Part of binary is determined by TableGn. 866 unsigned Binary = getBinaryCodeForInstr(MI); 867 868 // Set the conditional execution predicate 869 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 870 871 // Encode S bit if MI modifies CPSR. 872 if (Opcode == ARM::MOVsrl_flag || Opcode == ARM::MOVsra_flag) 873 Binary |= 1 << ARMII::S_BitShift; 874 875 // Encode register def if there is one. 876 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift; 877 878 // Encode the shift operation. 879 switch (Opcode) { 880 default: break; 881 case ARM::RRX: 882 // rrx 883 Binary |= 0x6 << 4; 884 break; 885 case ARM::MOVsrl_flag: 886 // lsr #1 887 Binary |= (0x2 << 4) | (1 << 7); 888 break; 889 case ARM::MOVsra_flag: 890 // asr #1 891 Binary |= (0x4 << 4) | (1 << 7); 892 break; 893 } 894 895 // Encode register Rm. 896 Binary |= getMachineOpValue(MI, 1); 897 898 emitWordLE(Binary); 899 } 900 901 void ARMCodeEmitter::addPCLabel(unsigned LabelID) { 902 DEBUG(errs() << " ** LPC" << LabelID << " @ " 903 << (void*)MCE.getCurrentPCValue() << '\n'); 904 JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue()); 905 } 906 907 void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) { 908 unsigned Opcode = MI.getDesc().Opcode; 909 switch (Opcode) { 910 default: 911 llvm_unreachable("ARMCodeEmitter::emitPseudoInstruction"); 912 case ARM::B: 913 emitBranchInstruction(MI); 914 break; 915 case ARM::BR_JTr: 916 case ARM::BR_JTm: 917 case ARM::BR_JTadd: 918 emitMiscBranchInstruction(MI); 919 break; 920 case ARM::BX_CALL: 921 case ARM::BMOVPCRX_CALL: 922 case ARM::BXr9_CALL: 923 case ARM::BMOVPCRXr9_CALL: { 924 // First emit mov lr, pc 925 unsigned Binary = 0x01a0e00f; 926 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 927 emitWordLE(Binary); 928 929 // and then emit the branch. 930 emitMiscBranchInstruction(MI); 931 break; 932 } 933 case TargetOpcode::INLINEASM: { 934 // We allow inline assembler nodes with empty bodies - they can 935 // implicitly define registers, which is ok for JIT. 936 if (MI.getOperand(0).getSymbolName()[0]) { 937 report_fatal_error("JIT does not support inline asm!"); 938 } 939 break; 940 } 941 case TargetOpcode::PROLOG_LABEL: 942 case TargetOpcode::EH_LABEL: 943 MCE.emitLabel(MI.getOperand(0).getMCSymbol()); 944 break; 945 case TargetOpcode::IMPLICIT_DEF: 946 case TargetOpcode::KILL: 947 // Do nothing. 948 break; 949 case ARM::CONSTPOOL_ENTRY: 950 emitConstPoolInstruction(MI); 951 break; 952 case ARM::LDMIA_RET: 953 emitLoadStoreMultipleInstruction(MI); 954 break; 955 case ARM::PICADD: { 956 // Remember of the address of the PC label for relocation later. 957 addPCLabel(MI.getOperand(2).getImm()); 958 // PICADD is just an add instruction that implicitly read pc. 959 emitDataProcessingInstruction(MI, 0, ARM::PC); 960 break; 961 } 962 case ARM::PICLDR: 963 case ARM::PICLDRB: 964 case ARM::PICSTR: 965 case ARM::PICSTRB: { 966 // Remember of the address of the PC label for relocation later. 967 addPCLabel(MI.getOperand(2).getImm()); 968 // These are just load / store instructions that implicitly read pc. 969 emitLoadStoreInstruction(MI, 0, ARM::PC); 970 break; 971 } 972 case ARM::PICLDRH: 973 case ARM::PICLDRSH: 974 case ARM::PICLDRSB: 975 case ARM::PICSTRH: { 976 // Remember of the address of the PC label for relocation later. 977 addPCLabel(MI.getOperand(2).getImm()); 978 // These are just load / store instructions that implicitly read pc. 979 emitMiscLoadStoreInstruction(MI, ARM::PC); 980 break; 981 } 982 983 case ARM::MOVi32imm: 984 // Two instructions to materialize a constant. 985 if (Subtarget->hasV6T2Ops()) 986 emitMOVi32immInstruction(MI); 987 else 988 emitMOVi2piecesInstruction(MI); 989 break; 990 case ARM::LEApcrel: 991 // Materialize constantpool index address. 992 emitLEApcrelInstruction(MI); 993 break; 994 case ARM::LEApcrelJT: 995 // Materialize jumptable address. 996 emitLEApcrelJTInstruction(MI); 997 break; 998 case ARM::RRX: 999 case ARM::MOVsrl_flag: 1000 case ARM::MOVsra_flag: 1001 emitPseudoMoveInstruction(MI); 1002 break; 1003 } 1004 } 1005 1006 unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI, 1007 const MCInstrDesc &MCID, 1008 const MachineOperand &MO, 1009 unsigned OpIdx) { 1010 unsigned Binary = getMachineOpValue(MI, MO); 1011 1012 const MachineOperand &MO1 = MI.getOperand(OpIdx + 1); 1013 const MachineOperand &MO2 = MI.getOperand(OpIdx + 2); 1014 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm()); 1015 1016 // Encode the shift opcode. 1017 unsigned SBits = 0; 1018 unsigned Rs = MO1.getReg(); 1019 if (Rs) { 1020 // Set shift operand (bit[7:4]). 1021 // LSL - 0001 1022 // LSR - 0011 1023 // ASR - 0101 1024 // ROR - 0111 1025 // RRX - 0110 and bit[11:8] clear. 1026 switch (SOpc) { 1027 default: llvm_unreachable("Unknown shift opc!"); 1028 case ARM_AM::lsl: SBits = 0x1; break; 1029 case ARM_AM::lsr: SBits = 0x3; break; 1030 case ARM_AM::asr: SBits = 0x5; break; 1031 case ARM_AM::ror: SBits = 0x7; break; 1032 case ARM_AM::rrx: SBits = 0x6; break; 1033 } 1034 } else { 1035 // Set shift operand (bit[6:4]). 1036 // LSL - 000 1037 // LSR - 010 1038 // ASR - 100 1039 // ROR - 110 1040 switch (SOpc) { 1041 default: llvm_unreachable("Unknown shift opc!"); 1042 case ARM_AM::lsl: SBits = 0x0; break; 1043 case ARM_AM::lsr: SBits = 0x2; break; 1044 case ARM_AM::asr: SBits = 0x4; break; 1045 case ARM_AM::ror: SBits = 0x6; break; 1046 } 1047 } 1048 Binary |= SBits << 4; 1049 if (SOpc == ARM_AM::rrx) 1050 return Binary; 1051 1052 // Encode the shift operation Rs or shift_imm (except rrx). 1053 if (Rs) { 1054 // Encode Rs bit[11:8]. 1055 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0); 1056 return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift); 1057 } 1058 1059 // Encode shift_imm bit[11:7]. 1060 return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7; 1061 } 1062 1063 unsigned ARMCodeEmitter::getMachineSoImmOpValue(unsigned SoImm) { 1064 int SoImmVal = ARM_AM::getSOImmVal(SoImm); 1065 assert(SoImmVal != -1 && "Not a valid so_imm value!"); 1066 1067 // Encode rotate_imm. 1068 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1) 1069 << ARMII::SoRotImmShift; 1070 1071 // Encode immed_8. 1072 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal); 1073 return Binary; 1074 } 1075 1076 unsigned ARMCodeEmitter::getAddrModeSBit(const MachineInstr &MI, 1077 const MCInstrDesc &MCID) const { 1078 for (unsigned i = MI.getNumOperands(), e = MCID.getNumOperands(); i >= e;--i){ 1079 const MachineOperand &MO = MI.getOperand(i-1); 1080 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR) 1081 return 1 << ARMII::S_BitShift; 1082 } 1083 return 0; 1084 } 1085 1086 void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI, 1087 unsigned ImplicitRd, 1088 unsigned ImplicitRn) { 1089 const MCInstrDesc &MCID = MI.getDesc(); 1090 1091 // Part of binary is determined by TableGn. 1092 unsigned Binary = getBinaryCodeForInstr(MI); 1093 1094 if (MCID.Opcode == ARM::MOVi16 || MCID.Opcode == ARM::MOVTi16) { 1095 emitWordLE(Binary); 1096 return; 1097 } 1098 1099 // Set the conditional execution predicate 1100 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1101 1102 // Encode S bit if MI modifies CPSR. 1103 Binary |= getAddrModeSBit(MI, MCID); 1104 1105 // Encode register def if there is one. 1106 unsigned NumDefs = MCID.getNumDefs(); 1107 unsigned OpIdx = 0; 1108 if (NumDefs) 1109 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; 1110 else if (ImplicitRd) 1111 // Special handling for implicit use (e.g. PC). 1112 Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift); 1113 1114 if (MCID.Opcode == ARM::MOVi16) { 1115 // Get immediate from MI. 1116 unsigned Lo16 = getMovi32Value(MI, MI.getOperand(OpIdx), 1117 ARM::reloc_arm_movw); 1118 // Encode imm which is the same as in emitMOVi32immInstruction(). 1119 Binary |= Lo16 & 0xFFF; 1120 Binary |= ((Lo16 >> 12) & 0xF) << 16; 1121 emitWordLE(Binary); 1122 return; 1123 } else if(MCID.Opcode == ARM::MOVTi16) { 1124 unsigned Hi16 = (getMovi32Value(MI, MI.getOperand(OpIdx), 1125 ARM::reloc_arm_movt) >> 16); 1126 Binary |= Hi16 & 0xFFF; 1127 Binary |= ((Hi16 >> 12) & 0xF) << 16; 1128 emitWordLE(Binary); 1129 return; 1130 } else if ((MCID.Opcode == ARM::BFC) || (MCID.Opcode == ARM::BFI)) { 1131 uint32_t v = ~MI.getOperand(2).getImm(); 1132 int32_t lsb = CountTrailingZeros_32(v); 1133 int32_t msb = (32 - CountLeadingZeros_32(v)) - 1; 1134 // Instr{20-16} = msb, Instr{11-7} = lsb 1135 Binary |= (msb & 0x1F) << 16; 1136 Binary |= (lsb & 0x1F) << 7; 1137 emitWordLE(Binary); 1138 return; 1139 } else if ((MCID.Opcode == ARM::UBFX) || (MCID.Opcode == ARM::SBFX)) { 1140 // Encode Rn in Instr{0-3} 1141 Binary |= getMachineOpValue(MI, OpIdx++); 1142 1143 uint32_t lsb = MI.getOperand(OpIdx++).getImm(); 1144 uint32_t widthm1 = MI.getOperand(OpIdx++).getImm() - 1; 1145 1146 // Instr{20-16} = widthm1, Instr{11-7} = lsb 1147 Binary |= (widthm1 & 0x1F) << 16; 1148 Binary |= (lsb & 0x1F) << 7; 1149 emitWordLE(Binary); 1150 return; 1151 } 1152 1153 // If this is a two-address operand, skip it. e.g. MOVCCr operand 1. 1154 if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1) 1155 ++OpIdx; 1156 1157 // Encode first non-shifter register operand if there is one. 1158 bool isUnary = MCID.TSFlags & ARMII::UnaryDP; 1159 if (!isUnary) { 1160 if (ImplicitRn) 1161 // Special handling for implicit use (e.g. PC). 1162 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift); 1163 else { 1164 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift; 1165 ++OpIdx; 1166 } 1167 } 1168 1169 // Encode shifter operand. 1170 const MachineOperand &MO = MI.getOperand(OpIdx); 1171 if ((MCID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) { 1172 // Encode SoReg. 1173 emitWordLE(Binary | getMachineSoRegOpValue(MI, MCID, MO, OpIdx)); 1174 return; 1175 } 1176 1177 if (MO.isReg()) { 1178 // Encode register Rm. 1179 emitWordLE(Binary | getARMRegisterNumbering(MO.getReg())); 1180 return; 1181 } 1182 1183 // Encode so_imm. 1184 Binary |= getMachineSoImmOpValue((unsigned)MO.getImm()); 1185 1186 emitWordLE(Binary); 1187 } 1188 1189 void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI, 1190 unsigned ImplicitRd, 1191 unsigned ImplicitRn) { 1192 const MCInstrDesc &MCID = MI.getDesc(); 1193 unsigned Form = MCID.TSFlags & ARMII::FormMask; 1194 bool IsPrePost = (MCID.TSFlags & ARMII::IndexModeMask) != 0; 1195 1196 // Part of binary is determined by TableGn. 1197 unsigned Binary = getBinaryCodeForInstr(MI); 1198 1199 // If this is an LDRi12, STRi12 or LDRcp, nothing more needs be done. 1200 if (MI.getOpcode() == ARM::LDRi12 || MI.getOpcode() == ARM::LDRcp || 1201 MI.getOpcode() == ARM::STRi12 || MI.getOpcode() == ARM::LDRBi12 || 1202 MI.getOpcode() == ARM::STRBi12) { 1203 emitWordLE(Binary); 1204 return; 1205 } 1206 1207 if (MI.getOpcode() == ARM::BR_JTm) 1208 Binary = 0x710F000; 1209 else if (MI.getOpcode() == ARM::BR_JTr) 1210 Binary = 0x1A0F000; 1211 1212 // Set the conditional execution predicate 1213 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1214 1215 unsigned OpIdx = 0; 1216 1217 // Operand 0 of a pre- and post-indexed store is the address base 1218 // writeback. Skip it. 1219 bool Skipped = false; 1220 if (IsPrePost && Form == ARMII::StFrm) { 1221 ++OpIdx; 1222 Skipped = true; 1223 } 1224 1225 // Set first operand 1226 if (ImplicitRd) 1227 // Special handling for implicit use (e.g. PC). 1228 Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift); 1229 else 1230 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; 1231 1232 // Set second operand 1233 if (ImplicitRn) 1234 // Special handling for implicit use (e.g. PC). 1235 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift); 1236 else 1237 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift; 1238 1239 // If this is a two-address operand, skip it. e.g. LDR_PRE. 1240 if (!Skipped && MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1) 1241 ++OpIdx; 1242 1243 const MachineOperand &MO2 = MI.getOperand(OpIdx); 1244 unsigned AM2Opc = (ImplicitRn == ARM::PC) 1245 ? 0 : MI.getOperand(OpIdx+1).getImm(); 1246 1247 // Set bit U(23) according to sign of immed value (positive or negative). 1248 Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) << 1249 ARMII::U_BitShift); 1250 if (!MO2.getReg()) { // is immediate 1251 if (ARM_AM::getAM2Offset(AM2Opc)) 1252 // Set the value of offset_12 field 1253 Binary |= ARM_AM::getAM2Offset(AM2Opc); 1254 emitWordLE(Binary); 1255 return; 1256 } 1257 1258 // Set bit I(25), because this is not in immediate encoding. 1259 Binary |= 1 << ARMII::I_BitShift; 1260 assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg())); 1261 // Set bit[3:0] to the corresponding Rm register 1262 Binary |= getARMRegisterNumbering(MO2.getReg()); 1263 1264 // If this instr is in scaled register offset/index instruction, set 1265 // shift_immed(bit[11:7]) and shift(bit[6:5]) fields. 1266 if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) { 1267 Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift; // shift 1268 Binary |= ShImm << ARMII::ShiftShift; // shift_immed 1269 } 1270 1271 emitWordLE(Binary); 1272 } 1273 1274 void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI, 1275 unsigned ImplicitRn) { 1276 const MCInstrDesc &MCID = MI.getDesc(); 1277 unsigned Form = MCID.TSFlags & ARMII::FormMask; 1278 bool IsPrePost = (MCID.TSFlags & ARMII::IndexModeMask) != 0; 1279 1280 // Part of binary is determined by TableGn. 1281 unsigned Binary = getBinaryCodeForInstr(MI); 1282 1283 // Set the conditional execution predicate 1284 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1285 1286 unsigned OpIdx = 0; 1287 1288 // Operand 0 of a pre- and post-indexed store is the address base 1289 // writeback. Skip it. 1290 bool Skipped = false; 1291 if (IsPrePost && Form == ARMII::StMiscFrm) { 1292 ++OpIdx; 1293 Skipped = true; 1294 } 1295 1296 // Set first operand 1297 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; 1298 1299 // Skip LDRD and STRD's second operand. 1300 if (MCID.Opcode == ARM::LDRD || MCID.Opcode == ARM::STRD) 1301 ++OpIdx; 1302 1303 // Set second operand 1304 if (ImplicitRn) 1305 // Special handling for implicit use (e.g. PC). 1306 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift); 1307 else 1308 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift; 1309 1310 // If this is a two-address operand, skip it. e.g. LDRH_POST. 1311 if (!Skipped && MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1) 1312 ++OpIdx; 1313 1314 const MachineOperand &MO2 = MI.getOperand(OpIdx); 1315 unsigned AM3Opc = (ImplicitRn == ARM::PC) 1316 ? 0 : MI.getOperand(OpIdx+1).getImm(); 1317 1318 // Set bit U(23) according to sign of immed value (positive or negative) 1319 Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) << 1320 ARMII::U_BitShift); 1321 1322 // If this instr is in register offset/index encoding, set bit[3:0] 1323 // to the corresponding Rm register. 1324 if (MO2.getReg()) { 1325 Binary |= getARMRegisterNumbering(MO2.getReg()); 1326 emitWordLE(Binary); 1327 return; 1328 } 1329 1330 // This instr is in immediate offset/index encoding, set bit 22 to 1. 1331 Binary |= 1 << ARMII::AM3_I_BitShift; 1332 if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) { 1333 // Set operands 1334 Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift; // immedH 1335 Binary |= (ImmOffs & 0xF); // immedL 1336 } 1337 1338 emitWordLE(Binary); 1339 } 1340 1341 static unsigned getAddrModeUPBits(unsigned Mode) { 1342 unsigned Binary = 0; 1343 1344 // Set addressing mode by modifying bits U(23) and P(24) 1345 // IA - Increment after - bit U = 1 and bit P = 0 1346 // IB - Increment before - bit U = 1 and bit P = 1 1347 // DA - Decrement after - bit U = 0 and bit P = 0 1348 // DB - Decrement before - bit U = 0 and bit P = 1 1349 switch (Mode) { 1350 default: llvm_unreachable("Unknown addressing sub-mode!"); 1351 case ARM_AM::da: break; 1352 case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break; 1353 case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break; 1354 case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break; 1355 } 1356 1357 return Binary; 1358 } 1359 1360 void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) { 1361 const MCInstrDesc &MCID = MI.getDesc(); 1362 bool IsUpdating = (MCID.TSFlags & ARMII::IndexModeMask) != 0; 1363 1364 // Part of binary is determined by TableGn. 1365 unsigned Binary = getBinaryCodeForInstr(MI); 1366 1367 if (MCID.getOpcode() == ARM::LDMIA_RET) { 1368 IsUpdating = true; 1369 Binary |= 0x8B00000; 1370 } 1371 1372 // Set the conditional execution predicate 1373 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1374 1375 // Skip operand 0 of an instruction with base register update. 1376 unsigned OpIdx = 0; 1377 if (IsUpdating) 1378 ++OpIdx; 1379 1380 // Set base address operand 1381 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift; 1382 1383 // Set addressing mode by modifying bits U(23) and P(24) 1384 ARM_AM::AMSubMode Mode = ARM_AM::getLoadStoreMultipleSubMode(MI.getOpcode()); 1385 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(Mode)); 1386 1387 // Set bit W(21) 1388 if (IsUpdating) 1389 Binary |= 0x1 << ARMII::W_BitShift; 1390 1391 // Set registers 1392 for (unsigned i = OpIdx+2, e = MI.getNumOperands(); i != e; ++i) { 1393 const MachineOperand &MO = MI.getOperand(i); 1394 if (!MO.isReg() || MO.isImplicit()) 1395 break; 1396 unsigned RegNum = getARMRegisterNumbering(MO.getReg()); 1397 assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) && 1398 RegNum < 16); 1399 Binary |= 0x1 << RegNum; 1400 } 1401 1402 emitWordLE(Binary); 1403 } 1404 1405 void ARMCodeEmitter::emitMulFrmInstruction(const MachineInstr &MI) { 1406 const MCInstrDesc &MCID = MI.getDesc(); 1407 1408 // Part of binary is determined by TableGn. 1409 unsigned Binary = getBinaryCodeForInstr(MI); 1410 1411 // Set the conditional execution predicate 1412 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1413 1414 // Encode S bit if MI modifies CPSR. 1415 Binary |= getAddrModeSBit(MI, MCID); 1416 1417 // 32x32->64bit operations have two destination registers. The number 1418 // of register definitions will tell us if that's what we're dealing with. 1419 unsigned OpIdx = 0; 1420 if (MCID.getNumDefs() == 2) 1421 Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift; 1422 1423 // Encode Rd 1424 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift; 1425 1426 // Encode Rm 1427 Binary |= getMachineOpValue(MI, OpIdx++); 1428 1429 // Encode Rs 1430 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift; 1431 1432 // Many multiple instructions (e.g. MLA) have three src operands. Encode 1433 // it as Rn (for multiply, that's in the same offset as RdLo. 1434 if (MCID.getNumOperands() > OpIdx && 1435 !MCID.OpInfo[OpIdx].isPredicate() && 1436 !MCID.OpInfo[OpIdx].isOptionalDef()) 1437 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift; 1438 1439 emitWordLE(Binary); 1440 } 1441 1442 void ARMCodeEmitter::emitExtendInstruction(const MachineInstr &MI) { 1443 const MCInstrDesc &MCID = MI.getDesc(); 1444 1445 // Part of binary is determined by TableGn. 1446 unsigned Binary = getBinaryCodeForInstr(MI); 1447 1448 // Set the conditional execution predicate 1449 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1450 1451 unsigned OpIdx = 0; 1452 1453 // Encode Rd 1454 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; 1455 1456 const MachineOperand &MO1 = MI.getOperand(OpIdx++); 1457 const MachineOperand &MO2 = MI.getOperand(OpIdx); 1458 if (MO2.isReg()) { 1459 // Two register operand form. 1460 // Encode Rn. 1461 Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift; 1462 1463 // Encode Rm. 1464 Binary |= getMachineOpValue(MI, MO2); 1465 ++OpIdx; 1466 } else { 1467 Binary |= getMachineOpValue(MI, MO1); 1468 } 1469 1470 // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand. 1471 if (MI.getOperand(OpIdx).isImm() && 1472 !MCID.OpInfo[OpIdx].isPredicate() && 1473 !MCID.OpInfo[OpIdx].isOptionalDef()) 1474 Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift; 1475 1476 emitWordLE(Binary); 1477 } 1478 1479 void ARMCodeEmitter::emitMiscArithInstruction(const MachineInstr &MI) { 1480 const MCInstrDesc &MCID = MI.getDesc(); 1481 1482 // Part of binary is determined by TableGn. 1483 unsigned Binary = getBinaryCodeForInstr(MI); 1484 1485 // Set the conditional execution predicate 1486 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1487 1488 // PKH instructions are finished at this point 1489 if (MCID.Opcode == ARM::PKHBT || MCID.Opcode == ARM::PKHTB) { 1490 emitWordLE(Binary); 1491 return; 1492 } 1493 1494 unsigned OpIdx = 0; 1495 1496 // Encode Rd 1497 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; 1498 1499 const MachineOperand &MO = MI.getOperand(OpIdx++); 1500 if (OpIdx == MCID.getNumOperands() || 1501 MCID.OpInfo[OpIdx].isPredicate() || 1502 MCID.OpInfo[OpIdx].isOptionalDef()) { 1503 // Encode Rm and it's done. 1504 Binary |= getMachineOpValue(MI, MO); 1505 emitWordLE(Binary); 1506 return; 1507 } 1508 1509 // Encode Rn. 1510 Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift; 1511 1512 // Encode Rm. 1513 Binary |= getMachineOpValue(MI, OpIdx++); 1514 1515 // Encode shift_imm. 1516 unsigned ShiftAmt = MI.getOperand(OpIdx).getImm(); 1517 if (MCID.Opcode == ARM::PKHTB) { 1518 assert(ShiftAmt != 0 && "PKHTB shift_imm is 0!"); 1519 if (ShiftAmt == 32) 1520 ShiftAmt = 0; 1521 } 1522 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!"); 1523 Binary |= ShiftAmt << ARMII::ShiftShift; 1524 1525 emitWordLE(Binary); 1526 } 1527 1528 void ARMCodeEmitter::emitSaturateInstruction(const MachineInstr &MI) { 1529 const MCInstrDesc &MCID = MI.getDesc(); 1530 1531 // Part of binary is determined by TableGen. 1532 unsigned Binary = getBinaryCodeForInstr(MI); 1533 1534 // Set the conditional execution predicate 1535 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1536 1537 // Encode Rd 1538 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift; 1539 1540 // Encode saturate bit position. 1541 unsigned Pos = MI.getOperand(1).getImm(); 1542 if (MCID.Opcode == ARM::SSAT || MCID.Opcode == ARM::SSAT16) 1543 Pos -= 1; 1544 assert((Pos < 16 || (Pos < 32 && 1545 MCID.Opcode != ARM::SSAT16 && 1546 MCID.Opcode != ARM::USAT16)) && 1547 "saturate bit position out of range"); 1548 Binary |= Pos << 16; 1549 1550 // Encode Rm 1551 Binary |= getMachineOpValue(MI, 2); 1552 1553 // Encode shift_imm. 1554 if (MCID.getNumOperands() == 4) { 1555 unsigned ShiftOp = MI.getOperand(3).getImm(); 1556 ARM_AM::ShiftOpc Opc = ARM_AM::getSORegShOp(ShiftOp); 1557 if (Opc == ARM_AM::asr) 1558 Binary |= (1 << 6); 1559 unsigned ShiftAmt = MI.getOperand(3).getImm(); 1560 if (ShiftAmt == 32 && Opc == ARM_AM::asr) 1561 ShiftAmt = 0; 1562 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!"); 1563 Binary |= ShiftAmt << ARMII::ShiftShift; 1564 } 1565 1566 emitWordLE(Binary); 1567 } 1568 1569 void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) { 1570 const MCInstrDesc &MCID = MI.getDesc(); 1571 1572 if (MCID.Opcode == ARM::TPsoft) { 1573 llvm_unreachable("ARM::TPsoft FIXME"); // FIXME 1574 } 1575 1576 // Part of binary is determined by TableGn. 1577 unsigned Binary = getBinaryCodeForInstr(MI); 1578 1579 if (MCID.Opcode == ARM::B) { 1580 Binary = 0xEA000000; 1581 } 1582 1583 // Set the conditional execution predicate 1584 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1585 1586 // Set signed_immed_24 field 1587 Binary |= getMachineOpValue(MI, 0); 1588 1589 emitWordLE(Binary); 1590 } 1591 1592 void ARMCodeEmitter::emitInlineJumpTable(unsigned JTIndex) { 1593 // Remember the base address of the inline jump table. 1594 uintptr_t JTBase = MCE.getCurrentPCValue(); 1595 JTI->addJumpTableBaseAddr(JTIndex, JTBase); 1596 DEBUG(errs() << " ** Jump Table #" << JTIndex << " @ " << (void*)JTBase 1597 << '\n'); 1598 1599 // Now emit the jump table entries. 1600 const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs; 1601 for (unsigned i = 0, e = MBBs.size(); i != e; ++i) { 1602 if (IsPIC) 1603 // DestBB address - JT base. 1604 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase); 1605 else 1606 // Absolute DestBB address. 1607 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute); 1608 emitWordLE(0); 1609 } 1610 } 1611 1612 void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) { 1613 const MCInstrDesc &MCID = MI.getDesc(); 1614 1615 // Handle jump tables. 1616 if (MCID.Opcode == ARM::BR_JTr || MCID.Opcode == ARM::BR_JTadd) { 1617 // First emit a ldr pc, [] instruction. 1618 emitDataProcessingInstruction(MI, ARM::PC); 1619 1620 // Then emit the inline jump table. 1621 unsigned JTIndex = 1622 (MCID.Opcode == ARM::BR_JTr) 1623 ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex(); 1624 emitInlineJumpTable(JTIndex); 1625 return; 1626 } else if (MCID.Opcode == ARM::BR_JTm) { 1627 // First emit a ldr pc, [] instruction. 1628 emitLoadStoreInstruction(MI, ARM::PC); 1629 1630 // Then emit the inline jump table. 1631 emitInlineJumpTable(MI.getOperand(3).getIndex()); 1632 return; 1633 } 1634 1635 // Part of binary is determined by TableGn. 1636 unsigned Binary = getBinaryCodeForInstr(MI); 1637 1638 // Set the conditional execution predicate 1639 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1640 1641 if (MCID.Opcode == ARM::BX_RET || MCID.Opcode == ARM::MOVPCLR) 1642 // The return register is LR. 1643 Binary |= getARMRegisterNumbering(ARM::LR); 1644 else 1645 // otherwise, set the return register 1646 Binary |= getMachineOpValue(MI, 0); 1647 1648 emitWordLE(Binary); 1649 } 1650 1651 static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) { 1652 unsigned RegD = MI.getOperand(OpIdx).getReg(); 1653 unsigned Binary = 0; 1654 bool isSPVFP = ARM::SPRRegisterClass->contains(RegD); 1655 RegD = getARMRegisterNumbering(RegD); 1656 if (!isSPVFP) { 1657 Binary |= (RegD & 0x0F) << ARMII::RegRdShift; 1658 Binary |= ((RegD & 0x10) >> 4) << ARMII::D_BitShift; 1659 } else { 1660 Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift; 1661 Binary |= (RegD & 0x01) << ARMII::D_BitShift; 1662 } 1663 return Binary; 1664 } 1665 1666 static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) { 1667 unsigned RegN = MI.getOperand(OpIdx).getReg(); 1668 unsigned Binary = 0; 1669 bool isSPVFP = ARM::SPRRegisterClass->contains(RegN); 1670 RegN = getARMRegisterNumbering(RegN); 1671 if (!isSPVFP) { 1672 Binary |= (RegN & 0x0F) << ARMII::RegRnShift; 1673 Binary |= ((RegN & 0x10) >> 4) << ARMII::N_BitShift; 1674 } else { 1675 Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift; 1676 Binary |= (RegN & 0x01) << ARMII::N_BitShift; 1677 } 1678 return Binary; 1679 } 1680 1681 static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) { 1682 unsigned RegM = MI.getOperand(OpIdx).getReg(); 1683 unsigned Binary = 0; 1684 bool isSPVFP = ARM::SPRRegisterClass->contains(RegM); 1685 RegM = getARMRegisterNumbering(RegM); 1686 if (!isSPVFP) { 1687 Binary |= (RegM & 0x0F); 1688 Binary |= ((RegM & 0x10) >> 4) << ARMII::M_BitShift; 1689 } else { 1690 Binary |= ((RegM & 0x1E) >> 1); 1691 Binary |= (RegM & 0x01) << ARMII::M_BitShift; 1692 } 1693 return Binary; 1694 } 1695 1696 void ARMCodeEmitter::emitVFPArithInstruction(const MachineInstr &MI) { 1697 const MCInstrDesc &MCID = MI.getDesc(); 1698 1699 // Part of binary is determined by TableGn. 1700 unsigned Binary = getBinaryCodeForInstr(MI); 1701 1702 // Set the conditional execution predicate 1703 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1704 1705 unsigned OpIdx = 0; 1706 1707 // Encode Dd / Sd. 1708 Binary |= encodeVFPRd(MI, OpIdx++); 1709 1710 // If this is a two-address operand, skip it, e.g. FMACD. 1711 if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1) 1712 ++OpIdx; 1713 1714 // Encode Dn / Sn. 1715 if ((MCID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm) 1716 Binary |= encodeVFPRn(MI, OpIdx++); 1717 1718 if (OpIdx == MCID.getNumOperands() || 1719 MCID.OpInfo[OpIdx].isPredicate() || 1720 MCID.OpInfo[OpIdx].isOptionalDef()) { 1721 // FCMPEZD etc. has only one operand. 1722 emitWordLE(Binary); 1723 return; 1724 } 1725 1726 // Encode Dm / Sm. 1727 Binary |= encodeVFPRm(MI, OpIdx); 1728 1729 emitWordLE(Binary); 1730 } 1731 1732 void ARMCodeEmitter::emitVFPConversionInstruction(const MachineInstr &MI) { 1733 const MCInstrDesc &MCID = MI.getDesc(); 1734 unsigned Form = MCID.TSFlags & ARMII::FormMask; 1735 1736 // Part of binary is determined by TableGn. 1737 unsigned Binary = getBinaryCodeForInstr(MI); 1738 1739 // Set the conditional execution predicate 1740 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1741 1742 switch (Form) { 1743 default: break; 1744 case ARMII::VFPConv1Frm: 1745 case ARMII::VFPConv2Frm: 1746 case ARMII::VFPConv3Frm: 1747 // Encode Dd / Sd. 1748 Binary |= encodeVFPRd(MI, 0); 1749 break; 1750 case ARMII::VFPConv4Frm: 1751 // Encode Dn / Sn. 1752 Binary |= encodeVFPRn(MI, 0); 1753 break; 1754 case ARMII::VFPConv5Frm: 1755 // Encode Dm / Sm. 1756 Binary |= encodeVFPRm(MI, 0); 1757 break; 1758 } 1759 1760 switch (Form) { 1761 default: break; 1762 case ARMII::VFPConv1Frm: 1763 // Encode Dm / Sm. 1764 Binary |= encodeVFPRm(MI, 1); 1765 break; 1766 case ARMII::VFPConv2Frm: 1767 case ARMII::VFPConv3Frm: 1768 // Encode Dn / Sn. 1769 Binary |= encodeVFPRn(MI, 1); 1770 break; 1771 case ARMII::VFPConv4Frm: 1772 case ARMII::VFPConv5Frm: 1773 // Encode Dd / Sd. 1774 Binary |= encodeVFPRd(MI, 1); 1775 break; 1776 } 1777 1778 if (Form == ARMII::VFPConv5Frm) 1779 // Encode Dn / Sn. 1780 Binary |= encodeVFPRn(MI, 2); 1781 else if (Form == ARMII::VFPConv3Frm) 1782 // Encode Dm / Sm. 1783 Binary |= encodeVFPRm(MI, 2); 1784 1785 emitWordLE(Binary); 1786 } 1787 1788 void ARMCodeEmitter::emitVFPLoadStoreInstruction(const MachineInstr &MI) { 1789 // Part of binary is determined by TableGn. 1790 unsigned Binary = getBinaryCodeForInstr(MI); 1791 1792 // Set the conditional execution predicate 1793 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1794 1795 if (MI.getOpcode() == ARM::VLDRS || MI.getOpcode() == ARM::VLDRD || 1796 MI.getOpcode() == ARM::VSTRS || MI.getOpcode() == ARM::VSTRD){ 1797 emitWordLE(Binary); 1798 return; 1799 } 1800 1801 unsigned OpIdx = 0; 1802 1803 // Encode Dd / Sd. 1804 Binary |= encodeVFPRd(MI, OpIdx++); 1805 1806 // Encode address base. 1807 const MachineOperand &Base = MI.getOperand(OpIdx++); 1808 Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift; 1809 1810 // If there is a non-zero immediate offset, encode it. 1811 if (Base.isReg()) { 1812 const MachineOperand &Offset = MI.getOperand(OpIdx); 1813 if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) { 1814 if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add) 1815 Binary |= 1 << ARMII::U_BitShift; 1816 Binary |= ImmOffs; 1817 emitWordLE(Binary); 1818 return; 1819 } 1820 } 1821 1822 // If immediate offset is omitted, default to +0. 1823 Binary |= 1 << ARMII::U_BitShift; 1824 1825 emitWordLE(Binary); 1826 } 1827 1828 void 1829 ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) { 1830 const MCInstrDesc &MCID = MI.getDesc(); 1831 bool IsUpdating = (MCID.TSFlags & ARMII::IndexModeMask) != 0; 1832 1833 // Part of binary is determined by TableGn. 1834 unsigned Binary = getBinaryCodeForInstr(MI); 1835 1836 // Set the conditional execution predicate 1837 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1838 1839 // Skip operand 0 of an instruction with base register update. 1840 unsigned OpIdx = 0; 1841 if (IsUpdating) 1842 ++OpIdx; 1843 1844 // Set base address operand 1845 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift; 1846 1847 // Set addressing mode by modifying bits U(23) and P(24) 1848 ARM_AM::AMSubMode Mode = ARM_AM::getLoadStoreMultipleSubMode(MI.getOpcode()); 1849 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(Mode)); 1850 1851 // Set bit W(21) 1852 if (IsUpdating) 1853 Binary |= 0x1 << ARMII::W_BitShift; 1854 1855 // First register is encoded in Dd. 1856 Binary |= encodeVFPRd(MI, OpIdx+2); 1857 1858 // Count the number of registers. 1859 unsigned NumRegs = 1; 1860 for (unsigned i = OpIdx+3, e = MI.getNumOperands(); i != e; ++i) { 1861 const MachineOperand &MO = MI.getOperand(i); 1862 if (!MO.isReg() || MO.isImplicit()) 1863 break; 1864 ++NumRegs; 1865 } 1866 // Bit 8 will be set if <list> is consecutive 64-bit registers (e.g., D0) 1867 // Otherwise, it will be 0, in the case of 32-bit registers. 1868 if(Binary & 0x100) 1869 Binary |= NumRegs * 2; 1870 else 1871 Binary |= NumRegs; 1872 1873 emitWordLE(Binary); 1874 } 1875 1876 void ARMCodeEmitter::emitMiscInstruction(const MachineInstr &MI) { 1877 unsigned Opcode = MI.getDesc().Opcode; 1878 // Part of binary is determined by TableGn. 1879 unsigned Binary = getBinaryCodeForInstr(MI); 1880 1881 if (Opcode == ARM::FCONSTS) { 1882 unsigned Imm = getMachineOpValue(MI, 1); 1883 Binary &= ~(0x780000 >> 19); 1884 Binary |= (Imm & 0x780000) >> 19; 1885 Binary &= ~(0x3800000 >> 7); 1886 Binary |= (Imm & 0x3800000) >> 7; 1887 Binary = VFPThumb2PostEncoder(MI, Binary); 1888 } 1889 1890 // Set the conditional execution predicate 1891 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1892 1893 emitWordLE(Binary); 1894 } 1895 1896 static unsigned encodeNEONRd(const MachineInstr &MI, unsigned OpIdx) { 1897 unsigned RegD = MI.getOperand(OpIdx).getReg(); 1898 unsigned Binary = 0; 1899 RegD = getARMRegisterNumbering(RegD); 1900 Binary |= (RegD & 0xf) << ARMII::RegRdShift; 1901 Binary |= ((RegD >> 4) & 1) << ARMII::D_BitShift; 1902 return Binary; 1903 } 1904 1905 static unsigned encodeNEONRn(const MachineInstr &MI, unsigned OpIdx) { 1906 unsigned RegN = MI.getOperand(OpIdx).getReg(); 1907 unsigned Binary = 0; 1908 RegN = getARMRegisterNumbering(RegN); 1909 Binary |= (RegN & 0xf) << ARMII::RegRnShift; 1910 Binary |= ((RegN >> 4) & 1) << ARMII::N_BitShift; 1911 return Binary; 1912 } 1913 1914 static unsigned encodeNEONRm(const MachineInstr &MI, unsigned OpIdx) { 1915 unsigned RegM = MI.getOperand(OpIdx).getReg(); 1916 unsigned Binary = 0; 1917 RegM = getARMRegisterNumbering(RegM); 1918 Binary |= (RegM & 0xf); 1919 Binary |= ((RegM >> 4) & 1) << ARMII::M_BitShift; 1920 return Binary; 1921 } 1922 1923 /// convertNEONDataProcToThumb - Convert the ARM mode encoding for a NEON 1924 /// data-processing instruction to the corresponding Thumb encoding. 1925 static unsigned convertNEONDataProcToThumb(unsigned Binary) { 1926 assert((Binary & 0xfe000000) == 0xf2000000 && 1927 "not an ARM NEON data-processing instruction"); 1928 unsigned UBit = (Binary >> 24) & 1; 1929 return 0xef000000 | (UBit << 28) | (Binary & 0xffffff); 1930 } 1931 1932 void ARMCodeEmitter::emitNEONLaneInstruction(const MachineInstr &MI) { 1933 unsigned Binary = getBinaryCodeForInstr(MI); 1934 1935 unsigned RegTOpIdx, RegNOpIdx, LnOpIdx; 1936 const MCInstrDesc &MCID = MI.getDesc(); 1937 if ((MCID.TSFlags & ARMII::FormMask) == ARMII::NGetLnFrm) { 1938 RegTOpIdx = 0; 1939 RegNOpIdx = 1; 1940 LnOpIdx = 2; 1941 } else { // ARMII::NSetLnFrm 1942 RegTOpIdx = 2; 1943 RegNOpIdx = 0; 1944 LnOpIdx = 3; 1945 } 1946 1947 // Set the conditional execution predicate 1948 Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift; 1949 1950 unsigned RegT = MI.getOperand(RegTOpIdx).getReg(); 1951 RegT = getARMRegisterNumbering(RegT); 1952 Binary |= (RegT << ARMII::RegRdShift); 1953 Binary |= encodeNEONRn(MI, RegNOpIdx); 1954 1955 unsigned LaneShift; 1956 if ((Binary & (1 << 22)) != 0) 1957 LaneShift = 0; // 8-bit elements 1958 else if ((Binary & (1 << 5)) != 0) 1959 LaneShift = 1; // 16-bit elements 1960 else 1961 LaneShift = 2; // 32-bit elements 1962 1963 unsigned Lane = MI.getOperand(LnOpIdx).getImm() << LaneShift; 1964 unsigned Opc1 = Lane >> 2; 1965 unsigned Opc2 = Lane & 3; 1966 assert((Opc1 & 3) == 0 && "out-of-range lane number operand"); 1967 Binary |= (Opc1 << 21); 1968 Binary |= (Opc2 << 5); 1969 1970 emitWordLE(Binary); 1971 } 1972 1973 void ARMCodeEmitter::emitNEONDupInstruction(const MachineInstr &MI) { 1974 unsigned Binary = getBinaryCodeForInstr(MI); 1975 1976 // Set the conditional execution predicate 1977 Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift; 1978 1979 unsigned RegT = MI.getOperand(1).getReg(); 1980 RegT = getARMRegisterNumbering(RegT); 1981 Binary |= (RegT << ARMII::RegRdShift); 1982 Binary |= encodeNEONRn(MI, 0); 1983 emitWordLE(Binary); 1984 } 1985 1986 void ARMCodeEmitter::emitNEON1RegModImmInstruction(const MachineInstr &MI) { 1987 unsigned Binary = getBinaryCodeForInstr(MI); 1988 // Destination register is encoded in Dd. 1989 Binary |= encodeNEONRd(MI, 0); 1990 // Immediate fields: Op, Cmode, I, Imm3, Imm4 1991 unsigned Imm = MI.getOperand(1).getImm(); 1992 unsigned Op = (Imm >> 12) & 1; 1993 unsigned Cmode = (Imm >> 8) & 0xf; 1994 unsigned I = (Imm >> 7) & 1; 1995 unsigned Imm3 = (Imm >> 4) & 0x7; 1996 unsigned Imm4 = Imm & 0xf; 1997 Binary |= (I << 24) | (Imm3 << 16) | (Cmode << 8) | (Op << 5) | Imm4; 1998 if (IsThumb) 1999 Binary = convertNEONDataProcToThumb(Binary); 2000 emitWordLE(Binary); 2001 } 2002 2003 void ARMCodeEmitter::emitNEON2RegInstruction(const MachineInstr &MI) { 2004 const MCInstrDesc &MCID = MI.getDesc(); 2005 unsigned Binary = getBinaryCodeForInstr(MI); 2006 // Destination register is encoded in Dd; source register in Dm. 2007 unsigned OpIdx = 0; 2008 Binary |= encodeNEONRd(MI, OpIdx++); 2009 if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1) 2010 ++OpIdx; 2011 Binary |= encodeNEONRm(MI, OpIdx); 2012 if (IsThumb) 2013 Binary = convertNEONDataProcToThumb(Binary); 2014 // FIXME: This does not handle VDUPfdf or VDUPfqf. 2015 emitWordLE(Binary); 2016 } 2017 2018 void ARMCodeEmitter::emitNEON3RegInstruction(const MachineInstr &MI) { 2019 const MCInstrDesc &MCID = MI.getDesc(); 2020 unsigned Binary = getBinaryCodeForInstr(MI); 2021 // Destination register is encoded in Dd; source registers in Dn and Dm. 2022 unsigned OpIdx = 0; 2023 Binary |= encodeNEONRd(MI, OpIdx++); 2024 if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1) 2025 ++OpIdx; 2026 Binary |= encodeNEONRn(MI, OpIdx++); 2027 if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1) 2028 ++OpIdx; 2029 Binary |= encodeNEONRm(MI, OpIdx); 2030 if (IsThumb) 2031 Binary = convertNEONDataProcToThumb(Binary); 2032 // FIXME: This does not handle VMOVDneon or VMOVQ. 2033 emitWordLE(Binary); 2034 } 2035 2036 #include "ARMGenCodeEmitter.inc" 2037
