/external/llvm/lib/CodeGen/ |
RegAllocBase.h | 67 unsigned NumRegs; 70 LiveUnionArray(): NumRegs(0), Array(0) {} 73 unsigned numRegs() const { return NumRegs; } 80 assert(PhysReg < NumRegs && "physReg out of bounds");
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RegisterClassInfo.cpp | 78 unsigned NumRegs = RC->getNumRegs(); 81 RCI.Order.reset(new unsigned[NumRegs]); 100 RCI.NumRegs = N + CSRAlias.size(); 101 assert (RCI.NumRegs <= NumRegs && "Allocation order larger than regclass"); 107 if (StressRA && RCI.NumRegs > StressRA) 108 RCI.NumRegs = StressRA; 112 if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs) 117 for (unsigned I = 0; I != RCI.NumRegs; ++I)
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RegisterClassInfo.h | 30 unsigned NumRegs; 34 RCInfo() : Tag(0), NumRegs(0), ProperSubClass(false) {} 36 return makeArrayRef(Order.get(), NumRegs); 81 return get(RC).NumRegs;
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VirtRegMap.cpp | 65 unsigned NumRegs = MF->getRegInfo().getNumVirtRegs(); 66 Virt2PhysMap.resize(NumRegs); 67 Virt2StackSlotMap.resize(NumRegs); 68 Virt2SplitMap.resize(NumRegs);
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RegAllocBase.cpp | 55 unionVRegs(new LiveVirtRegBitSet[PhysReg2LiveUnion.numRegs()]); 58 for (unsigned PhysReg = 0; PhysReg < PhysReg2LiveUnion.numRegs(); ++PhysReg) { 92 NumRegs = NRegs; 108 const unsigned NumRegs = TRI->getNumRegs(); 109 if (NumRegs != PhysReg2LiveUnion.numRegs()) { 110 PhysReg2LiveUnion.init(UnionAllocator, NumRegs); 112 Queries.reset(new LiveIntervalUnion::Query[PhysReg2LiveUnion.numRegs()]); 119 for (unsigned r = 0; r != NumRegs; ++r) 122 NumRegs = 0 [all...] |
ExecutionDepsFix.cpp | 134 const unsigned NumRegs; 149 : MachineFunctionPass(ID), RC(rc), NumRegs(RC->getNumRegs()) {} 251 assert(unsigned(rx) < NumRegs && "Invalid index"); 263 assert(unsigned(rx) < NumRegs && "Invalid index"); 274 assert(unsigned(rx) < NumRegs && "Invalid index"); 306 for (unsigned rx = 0; rx != NumRegs; ++rx) 330 for (unsigned rx = 0; rx != NumRegs; ++rx) 346 LiveRegs = new LiveReg[NumRegs]; 349 for (unsigned rx = 0; rx != NumRegs; ++rx) { 380 for (unsigned rx = 0; rx != NumRegs; ++rx) [all...] |
LiveVariables.cpp | 427 for (unsigned Reg = 1, NumRegs = TRI->getNumRegs(); Reg != NumRegs; ++Reg) { 509 unsigned NumRegs = TRI->getNumRegs(); 510 PhysRegDef = new MachineInstr*[NumRegs]; 511 PhysRegUse = new MachineInstr*[NumRegs]; 513 std::fill(PhysRegDef, PhysRegDef + NumRegs, (MachineInstr*)0); 514 std::fill(PhysRegUse, PhysRegUse + NumRegs, (MachineInstr*)0); 666 for (unsigned i = 0; i != NumRegs; ++i) 670 std::fill(PhysRegDef, PhysRegDef + NumRegs, (MachineInstr*)0); 671 std::fill(PhysRegUse, PhysRegUse + NumRegs, (MachineInstr*)0) [all...] |
MachineLICM.cpp | 496 unsigned NumRegs = TRI->getNumRegs(); 497 BitVector PhysRegDefs(NumRegs); // Regs defined once in the loop. 498 BitVector PhysRegClobbers(NumRegs); // Regs defined more than once. 533 BitVector TermRegs(NumRegs); [all...] |
/external/llvm/lib/Target/ARM/ |
Thumb1FrameLowering.cpp | 346 bool NumRegs = false; 359 NumRegs = true; 363 if (NumRegs)
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ARMBaseRegisterInfo.cpp | 133 unsigned NumRegs = SubIndices.size(); 134 if (NumRegs == 8) { 145 } else if (NumRegs == 4) { 182 } else if (NumRegs == 2) { [all...] |
ARMExpandPseudoInsts.cpp | 107 unsigned char NumRegs; // D registers loaded or stored 381 unsigned NumRegs = TableEntry->NumRegs; 392 if (NumRegs > 1 && TableEntry->copyAllListRegs) 394 if (NumRegs > 2 && TableEntry->copyAllListRegs) 396 if (NumRegs > 3 && TableEntry->copyAllListRegs) 446 unsigned NumRegs = TableEntry->NumRegs; 466 if (NumRegs > 1 && TableEntry->copyAllListRegs) 468 if (NumRegs > 2 && TableEntry->copyAllListRegs [all...] |
ARMBaseInstrInfo.cpp | [all...] |
ARMISelDAGToDAG.cpp | [all...] |
ARMLoadStoreOptimizer.cpp | 290 unsigned NumRegs = Regs.size(); 291 if (NumRegs <= 1) 300 else if (Offset == -4 * (int)NumRegs + 4 && haveIBAndDA) 302 else if (Offset == -4 * (int)NumRegs && isNotVFP) 313 if (NumRegs <= 2) 320 NewBase = Regs[NumRegs-1].first; 352 for (unsigned i = 0; i != NumRegs; ++i) [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
FunctionLoweringInfo.cpp | 231 unsigned NumRegs = TLI.getNumRegisters(Ty->getContext(), ValueVT); 232 for (unsigned i = 0; i != NumRegs; ++i) {
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LegalizeDAG.cpp | 326 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes; 340 for (unsigned i = 1; i < NumRegs; i++) { 448 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes; 459 for (unsigned i = 1; i < NumRegs; i++) { [all...] |
LegalizeIntegerTypes.cpp | 703 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), VT); 704 // The argument is passed as NumRegs registers of type RegVT. 706 SmallVector<SDValue, 8> Parts(NumRegs); 707 for (unsigned i = 0; i < NumRegs; ++i) { 720 for (unsigned i = 1; i < NumRegs; ++i) { [all...] |
SelectionDAGBuilder.cpp | 228 unsigned NumRegs = 231 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 232 NumParts = NumRegs; // Silence a compiler warning. 505 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, 510 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 511 NumParts = NumRegs; // Silence a compiler warning. 591 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT); 593 for (unsigned i = 0; i != NumRegs; ++i) 596 Reg += NumRegs; 662 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT) [all...] |
/external/llvm/include/llvm/MC/ |
MCRegisterInfo.h | 141 unsigned NumRegs; // Number of entries in the array 169 NumRegs = NR; 222 assert(RegNo < NumRegs && 306 return NumRegs;
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/external/llvm/lib/Target/ARM/MCTargetDesc/ |
ARMMCCodeEmitter.cpp | [all...] |
/external/v8/src/ |
frames.cc | [all...] |
/external/llvm/lib/Target/X86/ |
X86FastISel.cpp | [all...] |
/external/llvm/lib/Target/Mips/ |
MipsISelLowering.cpp | [all...] |
/external/llvm/lib/Transforms/Scalar/ |
LoopStrengthReduce.cpp | 766 unsigned NumRegs; 775 : NumRegs(0), AddRecCost(0), NumIVMuls(0), NumBaseAdds(0), ImmCost(0), 785 return ((NumRegs | AddRecCost | NumIVMuls | NumBaseAdds 787 || ((NumRegs & AddRecCost & NumIVMuls & NumBaseAdds 794 return NumRegs == ~0u; 853 ++NumRegs; [all...] |